JP3185211B2 - Matrix data multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Fields B Overview of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving the Problems (FIG. 1) F Function G Example G ₁ Configuration of One Example (First Example) (FIGS. 1 to 3) G ₂ Operation of One Embodiment (FIGS. 1 to 11) H Effects of the Invention A Industrial Field of the Invention The present invention relates to a matrix data multiplication apparatus suitable for digital image processing and the like.

B SUMMARY OF THE INVENTION The present invention provides an inner product operation circuit for calculating an inner product of a matrix,
In a matrix data multiplying device including a rearrangement circuit for rearranging matrix data, a required constant matrix is decomposed into a plurality of sparse matrices, and elements of one sparse matrix are set to 0, +1 and -1, and the other By using the elements of the low-order sparse matrix as data elements of a constant matrix, the circuit scale of the inner product operation circuit is reduced, the configuration is simplified, and the number of operations is reduced to improve the operation speed. It is.

C Prior Art Various discrete orthogonal transforms suitable for digital image processing have been known, and among them, a discrete cosine transform (Di
The screte cosine tramsform (DCT) passes through band compression and the processing method is relatively simple.

If this DCT is of order N, all of the first row The second and subsequent rows are transformed and inverse transformed using a matrix composed of the elements of cos ｛(2x + 1) kπ / 2N｝ (x = 0,1, ‥‥ N−1; k = 1, ‥‥ N−1). (IDCT)
Is defined, and in the case of two dimensions, it is expressed as follows.

[Y] = [N] · [X] · ^t [N] ‥‥ (1a) [X] = ^t [N] · [Y] · [N] ‥‥ (1b) Note that the matrix size is 2 ^N In the case of row 2 ^N columns, 1 /
Although a coefficient of 2 ^{N + 1} is applied, description of this coefficient is omitted because it is equivalent to a data shift of N + 1 bits. Also, (1
If it is defined that the coefficients a) and (1b) are multiplied by 1/2 ^N-1 respectively, the DCT and the IDCT become symmetric.

In the meantime, a multiplication device including an inner product operation circuit and a rearrangement circuit (corner turner) as shown in FIG. 12 has been conventionally used for multiplication of matrix data as in the equations (1a) and (1b).

In FIG. 12, (10) and (20) denote inner product operation circuits, each of which has, for simplicity, a quartic configuration corresponding to a matrix having a scale of 4 rows and 4 columns, and is provided via a corner turner (30). Connected.

That is, a data matrix [X] as shown in the following equation (2) is input from the terminal IN, and an inner product operation with a coefficient matrix [A] as shown in equation (3) is performed in one inner product operation circuit (10). Done.

The inner product operation circuit (10) has three unit delay units (11 ₁ ),
(11 ₂ ) and (11 ₃ ) are cascaded in reverse order, and four latches (12 ₁ ) and (1
2 ₂ ), (12 ₃ ) and (12 ₄ ) are respectively connected, and multipliers (13 ₁ ) cascaded to the latches (12 ₁ ) to (12 ₄ ), respectively
- (13 ₄₎ to the coefficient ROM (14 ₁₎ to (14 ₄₎ are respectively connected, the output of which is connected to the adder (15) each multiplier (13 ₁₎ to (13 _4), finite impulse response (Finite Impulse Res
ponse, FIR) type transversal filter.

Similarly, the inner product operation circuit (20) also has an FIR transversal filter configuration, and the sign of each corresponding element is “10”.
Is replaced by “2”, and redundant description is omitted. However, the coefficients _bij stored in the ROMs (24 ₁ ) to (24 ₄ )
Different from the coefficients a _{ij of} 4 ₁ ) to (14 ₄ ).

Corner Turner (30) is a pair of RAM (31) and (32)
And input-side and output-side selector switches (33) and (34)
And both switches (33) and (34) are a pair of switches.
During a period in which data is written to one of the RAMs (31) and (32), the data is read out from the other and linked together. The capacities of the RAMs (31) and (32) are each 16 words, corresponding to a matrix having a size of 4 rows and 4 columns as described above.

Next, multiplication of matrix data of the conventional example shown in FIG. 12 will be described with reference to FIG.

From the input terminal IN, the data of the input matrix [X] in units of 16 words as shown in FIG. 13A is stored in the first column (x ₁₁ , x ₂₁ , x ₃₁ , x ₃₁₎ .
₄₁₎ are supplied in the order of ~ fourth column _{(x 14, x 24, x} 34, x 44).

Time from the input start time t ₀ of the unit data of three cycles
At time t ₁ when 3T has elapsed, the unit delay units (11 ₁ ) and (11 ₂ )
And (11 ₃ ) output data x ₁₁ , x ₂₁ and x in the first column
With ₃₁ is present, the fourth data x ₄₁ is a delay unit (1
Present at the input terminal of the 1 _3).

In this state, the common Yi Neiburu pulse is supplied to each latch, four data x ₁₁ of the first row, x _21, x ₃₁ and x ₄₁ are four latches (12 _1), (12 ₂₎ , (12 ₃ ) and (12 ₄ ), respectively, and as shown in FIGS. 13, B, D, F and H, are held for 4 T time from the time t ₂ after the elapse of 4 T time from the input start time t _0. You.

_{ROM (14 1), (14} 2), (14 3) and the coefficient of each column (14 ₄₎ The coefficient matrix [A] a _i1, a _i2, a _i3 and a _i4 (i = 1,2,
3, 4) are stored, FIG. C, E, as shown in G and J, for each cycle of t ₂ time points after a corresponding multiplier (13 _1), (13 _2), (13 ₃ ) and (13 ₄ ) are sequentially supplied, and the corresponding latches (12 ₁ ), (12 ₂ ), (1
2 ₃ ) and (12 ₄ ) held in the first column of data x _i1 (i =
1,2,3,4).

That is, in t ₂ after the time of 1, 2, 3 and 4 th of each cycle, the coefficient a _1j of 1, 2, 3 and 4 rows of the coefficient matrix, a _2j, a _3j and a
_4j (j = 1,2,3,4) is the data x ₁₁ of the first column of the input matrix,
is multiplied by the x _21, x ₃₁ and x _41.

In the adder (15), the output is summed for each multiplier (13 ₁₎ to (13 _4), as shown in FIG. K, shown in the following equation (4) at t ₂ after the time of 4 cycles Product matrix [U]
, The data u ₁₁ , u ₂₁ , u ₃₁ and u ₄₁ of the first column are obtained.

[U] = [A] · [X] ‥‥‥ (4) On the other hand, as shown in FIG. 7A, at time t ₂ , data x ₁₂ , x ₂₂ , x ₃₂ and 2 x ₄₂ input starts,
As before, at the time point t ₃ after 4T period from t ₂ time, the second
Column of data x _12, x _22, x ₃₂ and x ₄₂ respectively latch (1
2 ₁ ), (12 ₂ ), (12 ₃ ) and (12 ₄ ). In addition, for each cycle of the t ₃ point onward, ROM (1
From 4 ₁ ), (14 ₂ ), (14 ₃ ) and (14 ₄ ), similarly to the above, the coefficients a _i1 , a _i2 , a _i3 and a _i4 (i =
1, 2, 3, 4) are sequentially output.

Thereafter, in the same manner as described above, the data u ₁₂ , u ₂₂ , u ₃₂ and u ₄₂ of the second column of the product matrix [U] as shown in the above equation (4) are obtained in four cycles after time t _3. Can be

In the same manner, at the next t ₄ after the time of 4 cycles, data u ₁₃ ~u ₄₃ of the third column of the matrix product [U] is obtained, in the next t ₅ after the time of 4 cycles, the product Of the matrix [U]
Data u ₁₄ ~u ₄₄ columns are obtained.

The 16-word column-order data of the matrix [U] obtained as described above is stored in the RAMs (31) and (3) of the corner turner (30).
It is written alternately in 2). By changing the address for writing and the address for reading, RAM (31)
The data of the matrix [U] alternately read out in row order from (32) and (32) is supplied to the second inner product operation circuit (20), and multiplied with the second coefficient matrix [B] in the same manner as described above. The data of the product matrix [Y] expressed by the following equation (5) is
Derived to OUT.

[Y] = [U]. [B] = [A]. [X]. [B] ‥‥ (5) D Problems to be Solved by the Invention By the way, when the size of the matrix is 8 rows and 8 columns, The constant matrix [N] in the expression (1) is represented by the following expression (6).

Here, the elements a to n are, as shown in FIG.
This is a cosine of a predetermined angle in units of / 16.

Further, as is apparent from the equation (1) that defines DCT and IDCT, the element y _ij of the matrix [Y] is expressed by a linear expression of the element x _ij of the matrix [X].

Therefore, as shown in FIG. 15, the elements x _{11 to} x of 8 rows and 8 columns
₈₈ is entered 64 Next vector in column order matrix [Xc]
A matrix represented by the following equation (7) holds between the matrix and the matrix [Yc], in which elements y _{11 to} y ₈₈ of 8 rows and 8 columns are output in column order and become a 64th-order vector.

 [Yc] = [M] · [Xc] (7) where [M] is a constant matrix of 64 rows and 64 columns.

However, in the above-described conventional matrix data multiplication apparatus, when performing the operation of the equation (7), the calculation is performed at once using, for example, a 64th-order inner product operation circuit. There is a problem that the operation becomes complicated and the number of operations increases, thereby restricting the operation speed.

In view of the foregoing, it is an object of the present invention to provide a matrix data multiplication device which has a small circuit scale, a simple configuration, a reduced number of operations, and a high speed operation.

E Means for Solving the Problems A first aspect of the present invention provides a matrix data multiplication apparatus including an inner product operation circuit for calculating an inner product of a matrix and a rearrangement circuit for rearranging the data components of the matrix in a predetermined order. A first inner product operation circuit (42) of order 4 with +1 and -1;
A 16th-order second inner product operation circuit with coefficients 0, +1 and -1 (4
4) and a fourth-order third inner product operation circuit (45) including a memory in which data components of a constant matrix are stored, and the input data of 8 rows and 8 columns is provided by a first rearrangement circuit (41). First through
And supplies the output of the first inner product operation circuit to the second inner product operation circuit via the second rearranging circuit (43), and outputs the output of the second inner product operation circuit. This is a matrix data multiplying device that is directly supplied to a third inner product operation circuit and derives an output of the third inner product operation circuit via a third rearrangement circuit (46).

According to the present invention, the scale of the inner product calculation circuit is small, the configuration is simple, and the number of calculations is reduced, thereby enabling high-speed calculation.

G Embodiment Hereinafter, an embodiment of a matrix data multiplication device according to the present invention will be described with reference to FIGS. 1 to 11.

G ₁ Configuration of One Embodiment FIG. 1 shows the configuration of one embodiment of the present invention, and FIG. 2 and FIG. 3 show the configuration of main parts thereof.

In FIG. 1, eight rows and eight columns of data are input in column order from the input terminal IN, as shown in the matrix [Xc] of FIG. 31 described above, and are transmitted via a first corner turner (41) of 64 words. hand,
It is supplied to a fourth-order first inner product calculation circuit (42). The output of the inner product operation circuit (42) is passed through the second corner turner (43) of 64 words to the 16th-order second inner product operation circuit (44).
Supplied to The output of the inner product operation circuit (44) is the third order of the fourth order.
Is supplied to the inner product arithmetic circuit (45) of the inner product arithmetic circuit (45).
Is output to an output terminal OUT via a 64-word third corner turner (46).

As described later, the coefficient of the first inner product calculation circuit (42) is
There are only +1 and −1, and the coefficients of the second inner product operation circuit (44) are only 0, +1 and −1. The coefficient of the third inner product calculation circuit (45) is a value unique to DCT.

In FIG. 2, (50) is a fourth-order inner product operation circuit, which corresponds to the inner product operation circuit (42) in FIG. 1, and includes three unit delay units (51 ₁ ), (51 ₂ ), (51 ₂ ) 51 ₃ ) are connected in cascade in reverse order, and four latches (52 ₁ ), (52 ₂ ), (52 ₃ ), and (52 ₄ ) are connected to the output terminal, both connection midpoints, and the input terminal, respectively. You. The outputs of the latches (52 ₁ ) to (52 ₄ ) are supplied to the positive contacts of the switches (53 ₁ ) to (53 ₄ ), respectively, and via the two's complement circuits (54 ₁ ) to (54 ₄ ). And supplied to the negative contacts of the switches (53 ₁ ) to (53 ₄ ). The outputs of the switches (53 ₁ ) to (53 ₄ ) are supplied to the adder (55).

Each switch (53 ₁ ) to (53 ₄ ) is a complement circuit (54 ₁ )
(54 ₄ ) constitutes a multiplier having coefficients of +1 and −1, and can be switched independently by the system control circuit (56).

As is well known, the two's complement circuits (54 ₁ ) to (54 ₄ ) include a negation circuit and an addition circuit.

In FIG. 3, reference numeral (60) denotes a 16th-order inner product operation circuit, which corresponds to the inner product operation circuit (44) in FIG. 1, and includes 15 unit delay units (61 ₁ ), (61 ₂ ) to (61 ₂ ). 61 ₁₅₎ connected in cascade in reverse order, its output, each connecting node and the input terminal to the 16 latches (62 _1), (62 ₂₎ to (62 ₁₆₎ are respectively connected.
The outputs of the latches (62 ₁ ) to (62 ₁₆ ) are supplied to the positive contacts of the three-contact selector switches (63 ₁ ) to (63 ₁₆ ), respectively, and the two's complement circuits (64 ₁ ) to (64 ₁₆ ) ) Are supplied to the negative contacts of the switches (63 ₁ ) to (63 ₁₆ ). Switch (63 ₁₎ to the coefficient 0 to the third contacts (63 ₁₆₎ are supplied, the switch (63 ₁₎ to (63 ₁₆₎
Are supplied to the adder (65).

Each switch (63 ₁ ) to (63 ₁₆ ) is a complement circuit (64 ₁ )
(64 ₁₆ ) constitutes a multiplier having coefficients of only 0, +1 and −1, and can be switched independently by the system control circuit (66).

Operation of G ₂ one embodiment Next, with reference also to Figure 4-Figure 11, the operation of the embodiment of Figure 1.

In the embodiment of FIG. 1, a constant matrix [M] of 64 rows and 63 columns for DCT is decomposed into six matrices as shown in the following equation (8).

[M] = [W] · [V] · [TS] · [R] · [L] · [Q] / 8 ８ (8) The matrices [Q], [R] and [W] are the first, The matrices [L], [TS], and [V] correspond to the first and second corner turners (41), (43), and (46), respectively.
And the third inner product operation circuits (42), (44) and (45), respectively. Each of the matrices [Q] to [W] has 64 rows and 64 columns, and as shown in FIGS. 4 to 11, is a sparse matrix containing a large number of 0 elements.

In FIGS. 4 to 11, + and-represent +1 and -1, respectively, and the same applies to the following figures showing other matrices.

In corner turner (41), as shown in FIG.
In each row and each column of the matrix [Q], only one location is +1 and the remaining 63 elements are all 0, so that the input data X of 64 words is rearranged.

In the inner product operation circuit (42), the rearranged data QX undergoes an operation process represented by a matrix [L] in FIG. As is apparent from FIG.
Is a sparse matrix with only +1 and -1 elements, 16 diagonal 4-row, 4-column matrices of the same shape, and all other parts are sparse matrices with 0 elements, as shown in FIG. The arithmetic processing can be performed by the fourth-order inner product arithmetic circuit (50).

In FIG. 2, data QX in units of 64 words is supplied from an input terminal IN, and four data are respectively supplied to four latches (52 ₁ ), (52 ₂ ), (52 ₃ ), and (52 ₄ ). Captured,
Holds for 4T hours.

Four switches (53 ₁ ), (53 ₂ ), (53 ₃ ), (53 ₄ )
Is switched to the + side or the-side depending on whether the element of the 4-row, 4-column sub-matrix of the matrix [L] is +1 or −1, and each of the latches (52 ₁ ) to (52 ₄ ) + To retained data
The coefficient is multiplied by 1 or −1, added by the adder (55), and output from the terminal OUT.

64-word data output from the inner product operation circuit (42)
The LQXs are rearranged in the second corner turner (43) as represented by a matrix [R] shown in FIGS. 6 and 7A to 7D.

The rearranged data RLQX is subjected to a calculation process represented by the matrix [TS] in FIG. 8 in the second inner product calculation circuit (44). As can be seen from the figure, this matrix [TS] has 16 rows and 16 columns, and four small matrices having only +1, -1 and 0 elements are arranged diagonally, and the other parts are all 0.
Since the matrix is a sparse matrix of elements, arithmetic processing can be performed by a 16th-order inner product arithmetic circuit (60) as shown in FIG.

In FIG. 3, data RLQX in units of 64 words is supplied from an input terminal IN, and 16 data are fetched into 16 latches (62 ₁ ) to (62 ₁₆ ) and held for 16T time.

The 16 switches (63 ₁ ) to (63 ₁₆ ) correspond to one of the matrix [TS].
6 rows and 16 columns of submatrix elements of 0, + 1, by whether it is a -1, 0 side, the + side or - is switched to the side, are held in the respective latches (62 ₁₎ to (62 ₁₆₎ The obtained data is multiplied by a coefficient of 0, +1 or −1, added by an adder (65), and output from a terminal OUT.

64-word data output from the inner product operation circuit (44)
TSRLQX further includes a third inner product operation circuit (45)
It is subjected to an arithmetic operation represented by the matrix [V] in FIG. As apparent from FIG. 28, this matrix [V] is a sparse matrix having four rows and four columns, each of which is arranged diagonally and four other elements are all sparse matrices. The arithmetic processing can be performed by a normal fourth-order inner product arithmetic circuit (45) as shown in FIG.

64-word data output from the inner product operation circuit (45)
VTSRLQX is in the third corner (46)
The desired output data WVTSRLQX is obtained by rearrangement as shown by the matrix [W] shown in FIGS. 11 and 11A to 11D.

In the embodiment of FIG. 1, each inner product operation circuit (42),
Matrices [L] and [TS] representing the arithmetic processing of (44) and (45)
Since [V] and [V] are both sparse matrices, the number of multiplication circuits can be reduced, and the size of each inner product operation circuit can be reduced.

As for the inner product operation circuits (42) and (44), since the coefficients of the matrices [L] and [TS] are only 0 and +1 and −1, as shown in FIGS. The configuration of the multiplier can be simplified, and no rounding error occurs during the inner product operation.

Further, the matrices [L], [TS] and [V] are such that the small matrices forming them are all arranged diagonally, and the transposed matrices have the same shape. , First
This can be dealt with by a configuration similar to that of the embodiment shown in FIG.

The matrix [TS] and [V] are combined to form a matrix [VTS].
Is formed, a single ordinary 16th-order inner product calculation circuit can be used instead of the 16th and 4th order inner product calculation circuits (44) and (45), respectively.

H Effects of the Invention As described in detail above, according to the present invention, a desired constant matrix is decomposed into a plurality of sparse matrices, and one sparse matrix element is set to 0,
In addition to +1 and −1, the other low-order sparse matrix element is used as a data component of a constant matrix. Therefore, the circuit scale of the inner product operation circuit is small, and the configuration is simplified.
A matrix data multiplication device in which the number of calculations is reduced and the calculation speed is improved can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a matrix data multiplication device according to the present invention, FIGS. 2 and 3 are block diagrams showing a configuration of a main part of an embodiment of the present invention, and FIGS. No.
11 is a diagram showing a matrix for explaining the operation of the main part of one embodiment of the present invention, FIG. 12 is a block diagram showing a configuration example of a conventional matrix data multiplication device, and FIG. 13 is an operation of the conventional example FIG. 14 and FIG. 15 are diagrams for explaining the present invention. (14 ₁₎ to (14 _4), (24 ₁₎ to (24 ₄₎ is ROM, (41),
(43), (46), (81), (83), (85), and (87) are rearranging circuits, and (42), (44), (45), (47), (4)
8), (49), (82), (84), and (86) are inner product operation circuits, (54 ₁ ) to (54 ₄ ), (64 ₁ ) to (64 ₁₅ ), and (75 ₁ )
(75 ₈ ) is a two's complement circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 51 no. 5, p. 1304-1307 Signal Processing, vol. 5 no. 1, p. 81-85 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/14 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A matrix data multiplying device comprising: an inner product operation circuit for calculating an inner product of a matrix; and a rearranging circuit for rearranging the data components of the matrix in a predetermined order. 1, a 16th-order second inner product operation circuit having coefficients 0, +1 and -1; and a fourth-order third inner product operation circuit including a memory in which data components of a constant matrix are stored. Providing input data of 8 rows and 8 columns to the first inner product operation circuit via a first rearrangement circuit, and outputting the output of the first inner product operation circuit via a second rearrangement circuit. Supplying the output of the second inner product arithmetic circuit directly to the third inner product arithmetic circuit, and supplying the output of the third inner product arithmetic circuit to a third sorting circuit A matrix data multiplying device, wherein the matrix data multiplying device is derived through