JPH05300026A - Discrete cosine transformer device and inverse discrete cosine transformer device - Google Patents

Abstract

PURPOSE:To simplify the configuration by decreasing the scale of an inner product arithmetic operation circuit and to attain high speed arithmetic operation by decreasing number of times of the arithmetic operation. CONSTITUTION:Data of 8-row 8-column are inputted from an input terminal IN in the order of columns and fed to a 1st 4-degree inner product arithmetic operation circuit 42 via a 1st rearrangement circuit 41. An output of the inner product arithmetic operation circuit 42 is fed to a 2nd octal inner product arithmetic operation circuit 44 via a 64-word 2nd rearrangement circuit 43. An output of the inner product arithmetic operation circuit 44 is fed to a 3rd 4-degree inner product arithmetic operation circuit 45, and an output of the inner product arithmetic operation circuit 45 is fed to an output terminal OUT via the 64-word 3rd rearrangemenent circuit 46.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform device and an inverse discrete cosine transform device suitable for digital image processing and the like.

[0002]

2. Description of the Related Art Conventionally, various discrete orthogonal transforms suitable for digital image processing have been known, and among them, discrete cosine transform (discrete cosine transform) is known.
sform: DCT) is suitable for band compression and has a relatively simple processing method.

In the DCT of the Nth order, 1 / √2 is all in the first row, and cos {(2x + 1) kπ / 2N} (x = 0, 1 ... N-1; k in the second row and below. = 1 ... N-1) using a matrix [N] consisting of elements
CT) is defined and is two-dimensional, it is expressed as follows.

[0004]

[Equation 1] [Y] = [N] [X] ^t [N]

[Equation 2] [X] = ^t [N] [Y] [N]

When the matrix size is 2 ^N rows and 2 ^N columns,
A coefficient of 1/2 ^{N + 1 is applied to} the equation ( ¹ ), but since it is equivalent to a data shift of N + 1 bits, the description of this coefficient is omitted.

By the way, for the multiplication of the matrix data represented by the equations (1) and (2), a multiplication device including an inner product calculation circuit and a rearrangement circuit as shown in FIG. 24 has been conventionally used.
In FIG. 24, 10 and 20 are inner product arithmetic circuits,
For simplification, each has a quaternary configuration corresponding to a matrix of a size of 4 rows and 4 columns, and is connected via a rearrangement circuit 30.

That is, a data matrix [X] such as the following formula 3 is input from the terminal IN, and one inner product calculating circuit 10 performs an inner product calculation with the coefficient matrix [A] such as the formula 4. Be done.

[0008]

[Equation 3]

[Equation 4]

The inner product calculation circuit 10 includes three unit delay units 1
1 ₁ , 11 ₂ and 11 ₃ are cascade-connected in reverse order, and four latches 12 ₁ and 1 are provided at the output end, both connection midpoints and the input end.
Multipliers 13 _{1 to} 13 to which 2 ₂ , 12 ₃ and 12 ₄ are respectively connected and cascaded to the respective latches 12 _{1 to} 12 _4
4 the coefficient ROM 14 ₁ to 14 ₄ are respectively connected, the outputs of the multipliers _131-134 are connected to an adder 15, a finite impulse response (Finite Impuls
e Response (FIR) type transversal filter configuration.

Similarly, the inner product calculation circuit 20 also has a FIR type transversal filter configuration, and the tens digit of the code of each corresponding element is changed to "2" to omit duplicated description. However, the coefficient b stored in the ROMs 24 _{1 to} 24 _4
ij is different from the coefficients a _ij of the ROMs 14 _{1 to} 14 ₄ .

The rearrangement circuit 30 includes a pair of RAMs 31 and 32, and input side and output side changeover switches 33 and 34.
And both switches 33 and 34 have a pair of RAs.
During the period when data is written to one of M31 and M32,
The data is read from the other side so that the data is read in conjunction with each other. The RAMs 31 and 32 have a capacity of 4 as described above.
There are 16 words each corresponding to a matrix having a size of 4 rows.

Next, the conventional matrix data multiplication of FIG. 24 will be described with reference to FIG.

From the input terminal IN, as shown in FIG.
Data a of the input matrix [X] in units of 16 words is the first column
(X₁₁, X_{twenty one}, X₃₁, X₄₁) -4th column (x₁₄, X_{twenty four}, X
₃₄, X ₄₄) In order.

[0014] In t ₁ when the time 3T for three cycles from the input start point t ₀ has elapsed the unit data, the unit delay 11 _1, 11 ₂ and 11 ₃ of the data x ₁₁ of the first column to the output terminals, x ₂₁ and x ₃₁ are present, and the fourth data x ₄₁ is present at the input of the delay device 11 ₃ .

In this state, a common enable pulse is supplied to each latch, and the four data x ₁₁ in the first column,
x ₂₁ , x ₃₁ and x ₄₁ have four latches 12 ₁ , 12 ₂ , 1
2 ₃ and 12 ₄ , respectively, and in FIG. 25B,
As shown in D, F, and H, 4T from the input start time t ₀
It is held for 4T hours from time t ₂ after the passage of time.

ROM14₁, 14₂, 14₃And 14_Four
Is the coefficient a of each column of the coefficient matrix [A]. _i1, A_i2, A_i3as well as
a_i4(I = 1, 2, 3, 4) is stored, and
As shown in C, E, G and J, t₂1 size after time
Corresponding multiplier 13 for each clou₁, 13₂, 13₃Over
And 13_FourAre sequentially supplied to the corresponding latches 12
₁, 12₂, 12₃And 12_FourThe first row of data held by
Data x_i1It is multiplied by (i = 1, 2, 3, 4).

That is, in the 1st, _2nd , 3rd and 4th cycles after time t ₂ , the coefficients a _1j , a _2j , a _3j and a _4j (j = 1, 2, 3, 4) is multiplied with the first column of data x ₁₁ , x ₂₁ , x ₃₁ and x ₄₁ of the input matrix.

In the adder 15, each of the multipliers 13 ₁ to 1
3 ₄ output is addition of, as shown in the K in the figure, t ₂
The data u ₁₁ , u ₂₁ , u ₃₁ and u ₄₁ in the first column of the product matrix [U] as shown in the following equation 5 are obtained in four cycles after the time point.

[0019]

[Equation 5] [U] = [A] [X]

On the other hand, as shown in A of the figure, the data x ₁₂ , x ₂₂ , x ₃₂ and x ₄₂ of the second column of the matrix [X] at time t _2.
Is started, and 4T from the time point t ₂ as described above.
At time t ₃ after time, the data x ₁₂ , x ₂₂ , x in the second column
₃₂ and x ₄₂ are latched in latches 12 ₁ , 12 ₂ , 12 ₃ and 12 ₄ , respectively. Also, 1 after t ₃
ROM 14 ₁ , 14 ₂ , 14 ₃ and 1 for each cycle
4 ₄ in the same manner as described above, the coefficient a _i1 each column of the matrix [A], a _i2, a _i3 and a _i4 (i = 1,2,3,4) are sequentially output.

Thereafter, in the same manner as described above, 4 after time t ₃
In the cycle, the data u ₁₂ , u ₂₂ , u _32, and u ₄₂ in the second column of the product matrix [U] as shown in the above equation 5 are obtained.

In the same manner, the data u ₁₃ to u in the third column of the product matrix [U] are obtained in four cycles after the next time t _4.
43 is obtained, and the data u _{14 to} u _{44 in} the fourth column of the product matrix [U] are obtained in the next 4 cycles after the time point t ₅ .

1 of the matrix [U] obtained as described above
The 6-word column-order data is the RAM 3 of the rearrangement circuit 30.
Alternately written to 1 and 32. RA is changed by changing the write address and the read address.
Matrix alternately read from M31 and M32 in row order [U]
Is supplied to the second inner product arithmetic circuit 20 and is multiplied by the second coefficient matrix [B] in the same manner as described above.
The data of the product matrix [Y] represented by the following equation 6 is derived at the terminal OUT.

[0024]

[Equation 6] [Y] = [U] [B] = [A] [X] [B]

[0025]

By the way, when the scale of the matrix is 8 rows and 8 columns, the constant matrix [N] of the equation 1 is expressed by the following equation 7.

[0026]

[Equation 7] Here, the elements a to n have an angle of π /, as shown in FIG.
It is a cosine with a specified angle in units of 16.

Also, the number 1 that defines DCT and IDCT
As is clear from the equation, the element y _ij of the matrix [Y] is expressed by a linear equation of the element x _ij of the matrix [X].

Therefore, as shown in FIG. 27, elements x _{11 to} x ₈₈ of 8 rows and 8 columns are input in column order to form a vector of 64th order [Xc], and elements y _{11 to} y of 8 rows and 8 columns. ₈₈ is output in column order and becomes a 64th order vector [Yc]
The relationship expressed by the following equation 8 is established.

[0029]

## EQU8 ## [Yc] = [M] [Xc] where [M] is a constant matrix of 64 rows and 64 columns.

However, in the conventional matrix data multiplication device as described above, when the operation of the equation 8 is performed, for example, 6
Since the calculation is performed all at once using the fourth-order inner product arithmetic circuit, there are problems that the circuit scale becomes enormous, the configuration becomes complicated, the number of arithmetic operations increases, and the arithmetic speed is restricted.

In view of the above points, an object of the present invention is to provide a matrix data multiplication device which has a small circuit scale, a simple structure, and a reduced number of operations, which enables high-speed operations.

[0032]

A first means of the present invention is a discrete cosine transform device including an inner product arithmetic circuit for calculating the inner product of a matrix and a rearrangement circuit for rearranging the data components of the matrix in a predetermined order. Where the coefficients are +1 and -1
And a coefficient of 0, +
An 8th-order second inner product arithmetic circuit 44 of 1 and -1 and a third inner product arithmetic circuit 45 including a memory in which the data components of the constant matrix are stored are provided, and the input data of 8 rows and 8 columns is 1
Is supplied to the first inner product arithmetic circuit via the rearrangement circuit 41, and the output of the first inner product arithmetic circuit is supplied to the second inner product arithmetic circuit via the second rearrangement circuit 43.
The output of the second inner product arithmetic circuit is directly supplied to the third inner product arithmetic circuit, and the output of the third inner product arithmetic circuit is derived via the third rearrangement circuit 46. Is a discrete cosine transform device.

The second means of the present invention is an inverse discrete cosine transform device comprising an inner product calculating circuit for calculating the inner product of a matrix and a rearrangement circuit for rearranging the data components of the matrix in a predetermined order. A fourth inner product calculation circuit 72 including a memory in which data components are stored, and coefficients 0, +1
And an −1st fifth inner product arithmetic circuit 73 of −1 and a fourth sixth inner product arithmetic circuit 75 of coefficients +1 and −1 are provided, and input data of 8 rows and 8 columns is input to the fourth Rearrangement circuit 7
1 to the fourth inner product calculation circuit,
Of the inner product arithmetic circuit is directly supplied to the fifth inner product arithmetic circuit, and the output of the fifth inner product arithmetic circuit is supplied to the sixth inner product arithmetic circuit via the fifth rearrangement circuit 74. In addition, the inverse discrete cosine transform device is characterized in that the output of the sixth inner product calculating circuit is derived via the sixth rearrangement circuit 76.

A third means of the present invention is serially supplied to a discrete cosine transform device provided with an inner product calculating circuit for calculating the inner product of a matrix and a rearrangement circuit for rearranging the data components of the matrix in a predetermined order. Parallelizing circuit 81 for parallelizing a predetermined number of matrix data, and coefficients of +1 and −
Quaternary first inner product arithmetic circuit with 1 and coefficients 0, +1
And an −1st second inner product arithmetic circuit that is −1 and a third inner product arithmetic circuit that includes a memory in which the data components of the constant matrix are stored, and the first, second, and third inner product arithmetic operations are performed. Each of the predetermined number of circuits is arranged in parallel, and input data of 8 rows and 8 columns is supplied to the parallelization circuit through the first rearrangement circuit 41, and each data of the parallel data output from the parallelization circuit. Is supplied to each of the predetermined first inner product arithmetic circuits (adding circuits 42 ' _{1 to} 42' ₄ ), and the output of each of the first inner product arithmetic circuits directly corresponds to the above-mentioned corresponding one of the predetermined number. The second inner product arithmetic circuits 44 _{1 to} 44 ₄ are supplied, and the outputs of the respective second inner product arithmetic circuits are directly supplied to the corresponding third inner product arithmetic circuits 45 _{1 to} 45 ₄ of the predetermined number. At the same time, the outputs of the predetermined number of third inner product arithmetic circuits are converted into serial data. The discrete cosine transform device is characterized in that after (circuit 82), it is derived through a third rearrangement circuit 46.

The fourth means of the present invention is to calculate the inner product of matrices.
The inner product calculation circuit that performs the calculation and the data components of the matrix in a predetermined order
Inverse discrete cosine transformation with a rearrangement circuit for rearranging
In the conversion device, the queue data serially supplied is stored.
A parallelization circuit 91 that parallelizes every fixed number and a constant matrix data
Fourth inner product arithmetic circuit including a memory storing data components
And an eighth-order fifth dot product with coefficients 0, +1 and -1
Arithmetic circuit and sixth inner product of order 4 with coefficients +1 and -1
An arithmetic circuit is provided, and the fourth, fifth, and sixth inner product arithmetic operations are performed.
Each of the above paths is arranged in parallel and the input data of 8 rows and 8 columns is arranged.
Data via the fourth rearrangement circuit 71.
Of the parallel data output from the parallel circuit
Each data is assigned to the corresponding fourth inner product of the predetermined number
Arithmetic circuit 72 ₁~ 72_FourAnd the above fourth inner product calculation
The output of the circuit directly corresponds to the fifth of the predetermined ones.
Inner product arithmetic circuit 73₁~ 73_FourTo each of the above 5th
The output of the dot product arithmetic circuit directly corresponds to the above predetermined number
In addition to supplying to the sixth inner product calculating circuit,
Sixth inner product calculating circuit (adding circuit 75 '₁~ 75 '_Four)
6th after converting the output of serial number into serial data (circuit 92)
The rearrangement circuit 76 of FIG.
It is a featured inverse discrete cosine transform device.

[0036]

According to the present invention, it is possible to reduce the scale of the inner product arithmetic circuit, simplify the configuration, and reduce the number of arithmetic operations to enable high-speed arithmetic.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the matrix data multiplication device according to the present invention will be described below with reference to FIGS. That is, the structure of one embodiment of the present invention is shown in FIG.
The structure of the main part is shown in FIGS.

In FIG. 1, data of 8 rows and 8 columns is input from the input terminal IN in column order as shown in the vector [Xc] of FIG. 27, and the first rearrangement circuit 41 of 64 words is input. It is supplied to the first-order inner product calculation circuit 42 of the fourth order via the. The output of the inner product arithmetic circuit 42 is supplied to the 8th-order second inner product arithmetic circuit 44 via the second rearrangement circuit 43 of 64 words. The output of the inner product calculating circuit 44 is supplied to the third inner product calculating circuit 45 of the fourth order,
The output of 5 is led to the output terminal OUT via the third rearrangement circuit 46 of 64 words.

As will be described later, the coefficients of the first inner product calculating circuit 42 are only +1 and -1, and the coefficients of the second inner product calculating circuit 44 are only 0, +1 and -1. Further, the coefficient of the third inner product calculating circuit 45 has a value peculiar to DCT.

In FIG. 2, a fourth-order inner product calculating circuit 50 corresponds to the inner product calculating circuit 42 of FIG. 1, and three unit delay devices 51 ₁ , 51 ₂ , 51 ₃ are cascaded in reverse order. Thus, four latches 52 ₁ , 52 ₂ , 52 ₃ , 52 ₄ are connected to the output terminal, both connection midpoints and the input terminal, respectively. The output of latch 52 ₁ to 52 ₄ is supplied to a + side contact of the switch 53 ₁ to 53 ₄ respectively, via the two's complement circuit 54 ₁ to 54 _4, the switch 53 ₁ to 53
It is supplied to each of the ₄ negative contacts. Switch 53 ₁ ~
Each output of 53 ₄ is supplied to the adder 55.

Each of the switches 53 _{1 to} 53 ₄ constitutes a multiplier having coefficients of +1 and −1 together with each of the complement circuits 54 _{1 to} 54 ₄ , and they are independently switched by the system control circuit 56.

As is well known, the 2's complement circuits 54 _{1 to} 54 ₄ are composed of a negation circuit and an addition circuit.

In FIG. 3, reference numeral 60 designates an eighth-order inner product arithmetic circuit.
Which corresponds to the inner product calculation circuit 44 of FIG.
There are eight changeover switches 61₁~ 61₈To each first contact of
8 complement circuits 62 as supplied₁~ 62₈Through
Then switch 61₁~ 61 ₈Supplied to each second contact of
Be done. Switch 61₁~ 61₈The third contact of is a coefficient 0
Are supplied respectively, and the switch 61₁~ 61₈Each output of
Are adders 63 ₁~ 63₈Is supplied to.

The outputs of the adders 63 _{1 to} 63 ₈ are supplied to 16 latches 65 ₀ and 65 _{1 to} 65 ₁₅ through switches 64 ₁ to 64 _8, respectively. Each one of these
Pair of latches 65 ₀ , 65 ₁ ; 65 ₂ , 65 ₃ ... 65
The outputs of ₁₄ and 65 ₁₄ are eight changeover switches 66 ₁ and 66 ₂
It is supplied to the contacts of each pair of ... 66 _8. Switch 6
6 _1-66 sum the outputs of ₈ each 63 _{1-63 8}
Is supplied to.

The outputs of the latches 65 _{0 to} 65 ₁₅ are supplied to the parallel / serial converter 67, respectively. The output terminal OUT is derived from the converter 67.

The change-over switch 61 _{1-61 8} where, together with the complement circuit 62 ₁ to 62 _8, the coefficient is 0, + 1, -1 only multipliers constitute respectively, switch 64 _1-6
4 ₈ and 66 _{1 to} 66 ₈ are independently switched by the system control circuit 68.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.

In the embodiment of FIG. 1, the constant matrix [M] of 64 rows and 64 columns for DCT is decomposed into 6 matrices as shown in the following equation (9).

[0049]

[M] = [W] [V] [TS] [R] [L] [Q] / 8

The matrices [Q], [R] and [W] correspond to the first, second and third rearrangement circuits 41, 43 and 46, respectively, and the matrices [L], [TS] and [V]. ] Is the first, second and third inner product arithmetic circuits 42, 44 and 45
Respectively correspond to. The matrices [Q] to [W] are all 64
As shown in FIGS. 4 to 11, each row has 64 columns, and each sparse matrix (Sparse Mat) includes a large number of 0 elements.
rix).

In FIGS. 4 to 11, + and-represent +1 and -1, respectively, and the same applies to the subsequent figures showing other matrices.

In the rearrangement circuit 41, as shown in FIG. 4, only one place is +1 for each row and each column of the matrix [Q].
Since the remaining 63 elements are all 0, the 64 words of input data [Xc] are rearranged.

In the inner product calculation circuit 42, the rearranged data [Q] [Xc] is subjected to calculation processing as represented by the matrix [L] in FIG. As is clear from the figure, this matrix [L] has only +1 and -1 elements, and 16 small 4-matrix 4-matrixes of the same shape are lined up diagonally and all other parts are sparse with 0 elements. Since it is a matrix, it can be processed by the quadratic inner product calculating circuit 50 as shown in FIG.

In FIG. 2, from the input terminal IN, 64 words
Data [Q] [Xc] in units of code are supplied,
4 pieces of data 4 pieces of latch 52₁, 52₂, 52₃,
52 _FourAnd held for 4T hours.

Four switches 53 ₁ , 53 ₂ , 53 ₃ ,
53 _4, the elements of four rows and four columns of submatrix of the matrix [L] is +1
By either -1 or is, the + side or - is switched to the side, the coefficient of +1 or -1 to the data held in the respective latches 52 to 52 ₄ are multiplied and summed by the adder 55, It is output from the terminal OUT.

The 64-word data [L] [Q] [Xc] output from the inner product calculating circuit 42 is converted into the matrix [R] shown in FIGS. 6 and 7 to 10 in the second rearrangement circuit 43. Sorted as represented.

This rearranged data [R] [L]
[Q] [Xc] is the second inner product calculation circuit 44
The arithmetic processing as represented by the matrix [TS] in FIGS. 11 and 12 is performed. As is clear from the figure, this matrix [TS]
Are 0, +1 and −1 respectively, and at least one of the elements in each odd row of each column or the elements in the even rows below it is 0, 16
Since four small matrixes each having 16 rows and 16 columns are arranged diagonally and all other parts are sparse matrices, the operation can be performed by the 8th-order inner product operation circuit 60 as shown in FIG.

Since the matrix [TS] is all 0 except for the small matrix on the 16 × 16 diagonal line, it can be calculated by a 16th-order inner product calculation circuit. Moreover, since all the elements of the sub-matrix are 0 and ± 1, only the input data, the value through the 2's complementer for that value, and the value selected from the three values of 0 are selected. All you have to do is add. Further, if each 16 × 16 submatrix of the matrix [TS] is examined carefully, it is always 0 in either the 0th row or the 1st row of each column. And the second of each row
Either line 3 or line 3 is always 0. Similarly, either the 2k-th row or the 2k + 1-th row of each column is always 0 (k = 2 to 7). Therefore, in practice, the circuit of FIG. 3 using eight adders can be used.

Normally, a 16th-order inner product arithmetic circuit requires 16 adders, but as described above, either the 2k-th row or the 2k + 1-th row of each column is always 0 (k = 0
.About.7), it can be calculated by eight adders as shown in FIG. That is, the 16 latches in FIG. 3 are set to 0 by a clear signal (not shown) at the calculation start time.

The latch 65 ₀ has [TS _ii ] (i = 1 to 1).
4) line 0 and the input vector (when i = 1,
The 0th to 15th elements of [R] [L] [Q] [Xc], i
= 2, 16 to 3 of [R] [L] [Q] [Xc]
When the first element, i = 3, [R] [L] [Q]
The 32nd to 47th elements of [Xc], when i = 4,
(48th to 63rd elements of [R] [L] [Q] [Xc])
The intermediate calculation result and the calculation result are stored.

The latch 65 ₁ has [TS _ii ] (i = 1 to 1).
The intermediate calculation result of the first line of 4) and the input vector and the calculation result are stored. Select 1 is [TS _ii ] (i
= 1 to 4), the value from the input terminal is selected when the non-zero value in the 0th row or the 1st row is 1, and when it is -1, the value from the input terminal is 2 The value (-
(Value multiplied by 1) is selected, and both the 0th line and the 1st line are 0
If 0, 0 is selected.

Select 9 is selected when the 0th line is not 0.
Latch 65₀To the side and latch when the first row is not 0
65₁Turn it to the side. Either 0th line or 1st line
One is always 0, so select 9 is selected as above
The latch 65 ₀And latch 65₁Both of
There is no contradiction of choice. Also, the 0th line and the 1st line
If both lines are 0, either one may be selected.
Control signals for select 1 and select 9 are sent to the control circuit 68.
More controlled.

For example, at the j-th cycle (j = 0 to 15), the j-th element of the above-mentioned input vector is input from the input terminal. What kind of calculation is performed in FIG. 3 at this time will be described below.

When the element at the 0th row and the jth column of the above [TS _ii ] (i = 1 to 4) is 1, the value stored in the latch 65 ₀ (calculated by the j-1th cycle) The 0th
The intermediate calculation result of the row and the input data) is input to the adder 63 ₁ via the switch 66 ₁ , and the j-th element of the input vector is also input to the adder 63 ₁ via the switch 61 _1. To be done. Then, in the adder 63 ₁ , j−
The intermediate calculation result of the 0th row and the input data calculated up to the first cycle and the j-th element of the input vector are added, and the addition result is the switch 64 ₁
It is stored in the latch 65 ₀ via.

When the element at the 0th row and the jth column of the above [TS _ii ] (i = 1 to 4) is -1, the value stored in the latch 65 ₀ (by the j-1th cycle) The calculated intermediate calculation result of the 0th row and the input data) is input to the adder 63 ₁ via the switch 66 ₁ and multiplied by -1 with respect to the j-th element of the input vector. The value is also input to the adder 63 ₁ via the switch 61 ₁ . Then, in the adder 63 ₁ , the intermediate calculation result of the 0th row and the input data calculated up to the j−1th cycle, and the value obtained by multiplying the jth element of the input vector by −1. Is performed and the result of this addition is stored in the latch 65 ₀ via the switch 64 ₁ .

That is, when the element in the 0th row and the jth column is ± 1, the mid-calculation results of the 0th row and the input data are updated (± j for the jth element of the input vector). The addition of the value multiplied by 1) is performed.

When the element in the 1st row and the jth column of the above-mentioned [TS _ii ] (i = 1 to 4) is 1, the value stored in the latch 65 ₁ (calculated by the j-1th cycle) Was done, first
The intermediate calculation result of the row and the input data) is input to the adder 63 ₁ via the switch 66 ₁ , and the j-th element of the input vector is also input to the adder 63 ₁ via the switch 61 _1. To be done. Then, in the adder 63 ₁ , j−
The intermediate calculation result of the first row and the input data calculated up to the first cycle and the j-th element of the input vector are added, and the addition result is the switch 64 ₁
It is stored in the latch 65 ₁ via.

When the element in the 1st row and the jth column of the above-mentioned [TS _ii ] (i = 1 to 4) is -1, the value stored in the latch 65 ₁ (by the j-1th cycle) The calculated intermediate result of the calculation of the first row and the input data) is input to the adder 63 ₁ via the switch 66 ₁ and multiplied by -1 with respect to the j-th element of the input vector. The value is also input to the adder 63 ₁ via the switch 61 ₁ . Then, in the adder 63 ₁ , intermediate calculation results of the first row and the input data calculated up to the j−1th cycle, and a value obtained by multiplying the jth element of the input vector by −1. Are added and the result of this addition is stored in the latch 65 ₁ via the switch 64 ₁ .

That is, when the element in the 1st row and the jth column is ± 1, the mid-calculation results of the 1st row and the input data are updated (± for the jth element of the input vector). The addition of the value multiplied by 1) is performed.

When the elements in the 0th row and the jth column and the 1st row and the jth column are both 0, one of the latches is selected by the switch 66 ₁ and is switched via the adder 63 _1. 6
4 ₁ but is again stored in the selected latched, so this time 0 the switch 61 ₁ is input to the selected adders 63 _1, the adder 63 _1, substantially, the addition is not performed. That is, the data is not updated in both the substantial latches 65 ₀ and 65 ₁ .

In this manner, after 16 cycles, the latch 65 ₀ stores the calculation result of the 0th row and the input data, and the latch 65 ₁ receives the 1st row. It means that the calculation result with the data is stored.

Similarly, the latches 65 _{2 to} 65 ₁₅ have [T
S _ii ] (i = 1 to 4), the intermediate calculation results of the 2nd to 15th lines and the input vector are stored, and after 16 cycles, the calculation result (the 2nd to 15th lines and the input data) (Calculation result of) is stored.

These calculation results are input to the parallel / serial converter 67, the calculation result of the 0th row and the input data, the calculation result of the 1st row and the input data ,. ． ． It is serially output in the order of the calculation result of the 15th line and the input data.

Thus, calculation with 16 × 16 matrix [TS ₁₁ ], calculation with 16 × 16 matrix [TS ₂₂ ], 16 × 16
The calculation with the matrix [TS ₃₃ ] and the calculation with the 16 × 16 matrix [TS ₄₄ ] are performed in 16 cycles each.
That is, the calculation with the matrix [TS] is performed over 64 cycles.

The 64-word data [TS] [R] [L] [Q] [Xc] output from the inner product arithmetic circuit 44 is further processed by the third inner product arithmetic circuit 45 in FIGS.
[V] of the above matrix [V] is received. As is clear from the figure, this matrix [V] has 4 rows and 4 rows, respectively.
Since four sub-matrixes of columns are arranged diagonally and all other parts are sparse matrices with 0 elements, the arithmetic processing can be performed by the ordinary quadratic inner product arithmetic circuit 45 as shown in FIG.

64-word data [V] [TS] [R] [L] [Q] [Xc] output from the inner product calculating circuit 45.
In the third rearrangement circuit 46 shown in FIG.
6 to 19 are rearranged as represented by the matrix [W], and desired output data [W] [V] [TS] [R]
[L] [Q] [Xc] is obtained.

Actually,

[Equation 10] [Yc] = [M] [Xc] = [W] [V] [TS] [R] [L] [Q] [Xc] / 8 Since this output result is not divided by 8, However, this is not necessary in the figure, since it is sufficient to shift the value by 3 bits and no circuit is required.

In the embodiment shown in FIG. 1, matrices [L] and [T] representing the arithmetic processing of the inner product arithmetic circuits 42, 44 and 45, respectively.
Since S] and [V] are both sparse matrices, it is possible to reduce the number of multiplications and reduce the size of each inner product calculation circuit.

Further, for the inner product arithmetic circuit 42, the coefficients of the matrix [L] are only 0, +1 and -1, and for the inner product arithmetic circuit 44, the coefficients of the matrix [TS] are 0, +1 and-. Since only one element does not form two +1 or -1 elements in each row, the configuration of each multiplier can be simplified as shown in FIGS. 2 and 3, and a rounding error occurs during inner product calculation. There is nothing to do.

Here, as shown in FIG. 27, elements x _{11 to} x ₈₈ of 8 rows and 8 columns are input in the column order, and an element y of 8 rows and 8 columns is input.
_{The case where 11 to} y ₈₈ are output in the column order has been described, but when inputting and outputting in the other order, the rearrangement circuit 4
This can be dealt with by replacing 1 and 46 with a rearrangement circuit that rearranges data in another appropriate order.

As described above, according to the above-mentioned device, the scale of the inner product calculating circuit can be reduced, the structure can be simplified, and the number of calculations can be reduced to enable high-speed calculation.

Further, FIG. 20 is a block diagram of an example of the inverse discrete cosine transform device according to the present invention. In this figure, data of 8 rows and 8 columns is supplied from an input terminal IN to a fourth inner product arithmetic circuit 72 of the fourth order via a fourth rearrangement circuit 71 of 64 words. The output of the inner product calculating circuit 72 is supplied to the eighth-order fifth inner product calculating circuit 73. The output of the inner product arithmetic circuit 73 is supplied to the fourth inner product arithmetic circuit 75 of the fourth order via the fifth rearrangement circuit 74 of 64 words.
The output of the inner product calculation circuit 75 is led to the output terminal OUT via the sixth rearrangement circuit 76 of 64 words.

That is, in the embodiment of FIG. 20, ID
A constant matrix [IM] of 64 rows and 64 columns for CT is decomposed into 6 matrices as shown in the following Expression 10.

[0084]

[IM] = ^t [Q] [L] ^t [R] ^t [TS] ^t [V] ^t [W] / 8

The matrices ^t [W], ^t [R] and ^t [Q] respectively correspond to the fourth, fifth and sixth rearrangement circuits 71, 74 and 76, and the matrices ^t [V], ^t [V], ^t [V]. TS] and [L] are the fourth, fifth and sixth inner product arithmetic circuits 72, 7
3 and 75, respectively. Here, in the above-mentioned matrices [L], [TS], and [V], the small matrices forming them are all arranged on a diagonal line, and each transposed matrix
^{Since t} [L], ^t [TS], and ^t [V] have the same shape, the same structure as that of the embodiment of FIG. By the way, [L] = ^t [L].

[0086] However, the inner product computation circuit 73 for performing an operation of ^t [TS], since ^t [TS] is at least 0 either the even column elements of adjacent its right an odd column of each row, for example, FIG. Calculation is performed with the configuration of 21.

In FIG. 21, reference numeral 60 'denotes an eighth-order inner product arithmetic circuit, which corresponds to the inner product arithmetic circuit 73 of FIG.
Five unit delay devices 61 ′ ₁ , 61 ′ _{2 to} 61 ′ ₁₅ are cascade-connected in reverse order, and 16 latches 62 ′ ₁ , 62 ′ _{2 to} 62 are provided at the output end, each connection midpoint and the input end. ′ ₁₆ are respectively connected to each pair of latches 62 ′ ₁ , 62 ′ ₂ ; 6
2 _'3, 62' _4, ... 62 _'15, 62' ₁₆ output is 8
The changeover switches 63 ′ ₁ , 63 ′ _2, ... 63 ′ ₈ are supplied to each pair of contacts. Switch 63 ' _{1 to} 63'
Each output of the _8, 8 of the change-over switch 64 _{'1-64' 8}
Is supplied to each + side contact of the
5 through _{'1-65' 8,} the switch 64 _'1-64'
It is supplied to each negative side contact of ₈ . Switch 64 ' _{1 to} 6
4 'in the third contacts ₈ are supplied coefficient 0, respectively, the switch 64' _1-64 'each output of ₈ adder 66' is supplied to the.

Changeover switch 64 '₁~ 64 '₈Is the complement
Circuit 65 '₁~ 65 '₈With the coefficients 0, +1, -1
And a switch 63 '.₁~ 6
3 ' ₈Together with the system control circuit 67 ',
It can be switched to vertical.

Therefore, in FIG. 21, the input terminal IN
From 64 words in units of data [TS] [R] [L]
[Q] [Xc] is supplied, and 16 pieces of data are taken into ₁₆ latches 62 ′ _{1 to} 62 ′ ₁₆ ,
Hold for T hours.

The eight switches 63 ′ _{1 to} 63 ′ ₈ are switched to the non-zero side depending on which one of the adjacent elements of the 16 × 16 submatrix of the matrix [TS] is 0. , 8 out of the data held in each of the latches 62 ' _{1 to} 62' ₁₆ . However, when the elements adjacent to each other are both 0, the corresponding switches 63 ′ _{1 to} 63 ′ ₈ may be switched to either side.

The eight switches 64 ' ₁ to 64' ₈ depend on whether the element of the 16-row by 16-column sub-matrix corresponding to the extracted eight data is 0, +1 or -1. , 0 side, + side or − side, and the eight data thus taken out are multiplied by the coefficient of 0, +1 or −1, added by the adder 66 ′ and output from the terminal OUT. ..

Further, FIG. 22 shows a discrete cosine transform device according to the present invention in which the above-mentioned first, second and third inner product arithmetic circuits 42, 44 and 45 are respectively arranged in parallel to increase the operating speed. It is a thing. In this figure, after performing the operation of [Q] in the rearrangement circuit 41,
With respect to this output [Q] [Xc], four sets of serially output data are parallelized by the conversion circuit 81 and input to the four-input addition circuits 42 ′ _{1 to} 42 ′ ₄ .

[0093] 'first row of the ₁ [L], the fifth row, the ninth row ... second line 61 is calculated, 4 input adder circuit 42' This four-input adder circuit 42, ₂ [ The second line, the sixth line, the tenth line ... The 62nd line of L] are calculated, and in the 4-input addition circuit 42 ′ ₃ , the 3rd line, the 7th line of [L], 11th line: 4th-input addition circuit 4 by calculating the 63rd line
The fourth row of the 2 _'4 [L], line 8, line 12 -
.... Calculate the 64th line.

The operation [R] is a simple rearrangement,
It is 16 data of the 1st line, the 5th line, the 9th line ... 61st line of [L] [Q] [Xc] and the 2nd line, 6th line, 16th data in 10th line ... 62nd line, 3rd line, 7th line, 11th line ... 6th line
16 pieces of data on the 3rd line, 4th line, 8th line, 1st line
2nd line ... 4 sub-matrices of the operation [TS] divided into 4 groups with 16 data in the 64th line [T
This is for enabling the calculation of S ₁₁ ] [TS ₂₂ ] [TS ₃₃ ] [TS ₄₄ ].

Therefore, in the case of the circuit of FIG. 22, the values of the first row of [L] [Q] [Xc] from the 4-input adding circuit 42 ' ₁
The value of the fifth line, the value of the ninth line ... The value of the 61st line is output, and the 4-input adder circuit 42 ′ ₂ outputs [L] [Q] [X.
c] second row value, sixth row value, tenth row value
..Values in the 62nd row are output and 4-input addition circuit 42 '
The values of ₃ to [L] [Q] [Xc] on the third line, the value on the seventh line, the value on the eleventh line ... The value on the 63rd line are output, and the 4-input addition circuit 42 is output. ' ₄ to [L] [Q] [Xc]
The value of the 4th line, the value of the 8th line, the value of the 12th line ...
Since the value on the 64th line is output, a circuit for performing the operation [R] is not necessary, and the 4-input addition circuits 42 ' ₁ to 4'
The output of the 2 _'4, respectively inner product computation circuits 44 ₁ to 44 ₄
You can input to.

That is, in the inner product calculation circuit 44 ₁ , [L]
The value of [Q] [Xc] on the first line, the value on the fifth line, the value on the ninth line ... The value on the 61st line is used to calculate [TS ₁₁ ]. Similarly, the inner product arithmetic circuits 44 ₂ , 44 ₃ , and 44 ₄ respectively perform [TS ₂₂ ] [TS ₃₃ ] [TS ₄₄ ].
Is calculated.

Further, the inner product calculating circuit 44₁Inner product output
Arithmetic circuit 45₁Input to the inner product arithmetic circuit 45₁Then
[V₁₁] Is performed. Inner product calculation circuit 45₂, 45₃,
45 _FourBut in the same way, [V_{twenty two}] [V₃₃] [V
₄₄] Is performed.

Thus, from the outputs of the inner product arithmetic circuits 45 _{1 to} 45 ₄ , [V] [TS] [R] [L] [Q] [Xc].
Is output, so if this is serialized by the conversion circuit 82 and finally [W] is performed by the rearrangement circuit 46,
The output [Yc] is obtained.

Further, FIG. 23 shows that in the inverse discrete cosine transform device according to the present invention, the fourth, fifth and sixth inner product arithmetic circuits 72, 73 and 75 are parallelized to increase the operating speed. It is intended. In this figure, after the calculation of ^t [W] is performed by the rearrangement circuit 71, four data that are serially output for this output ^t [W] [Yc] are set as one set and the conversion circuit 91 is set.
In and parallelized, and inputs to the inner product computation circuit 72 ₁ to 72 _4.

This inner product calculation circuit 72₁~ 72_FourThen
^t[V₁₁] ~^t[V₄₄] Is performed. This inner product operation time
Road 72₁~ 72_FourOutput of the inner product calculation circuit 73
₁~ 73 _FourTo enter. This inner product calculation circuit 73₁~ 73
_FourThen^t[TS₁₁] ~^t[TS₄₄] Is performed.

The outputs of the inner product arithmetic circuits 73 _{1 to} 73 ₄ are input to the 4-input adder circuits 75 ' ₁ to 75' ₄ as they are. In the 4-input adder circuit 75 _{'1-75' 4} performs calculation of [L _11] - [L _44]. Thus, from the output of 4-input adder circuit 75 _{'1-75' 4} [L] ^t [R]
^{Since t} [TS] ^t [V] ^t [W] [Yc] is output, if this is serialized by the conversion circuit 92, and finally ^t [Q] is performed by the rearrangement circuit 76, the output [Xc ]
Is required.

[0102]

As described above in detail, according to the present invention,
The required constant matrix is decomposed into a plurality of sparse matrices, and the elements of one sparse matrix are 0, +1 and -1, and the elements of the other low-order sparse matrix are the data components of the constant matrix. Therefore, the circuit scale of the inner product arithmetic circuit is small, the configuration is simple, and the discrete cosine transform device and the inverse discrete cosine transform device in which the number of calculations is reduced and the calculation speed is improved can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a discrete cosine transform device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a main part thereof.

FIG. 3 is a block diagram showing a configuration of a main part thereof.

FIG. 4 is a diagram showing a matrix for explaining the operation of the main part thereof.

FIG. 5 is a diagram showing a matrix for explaining the operation of the main part thereof.

FIG. 6 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 7 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 8 is a diagram showing a matrix for explaining the operation of the main part thereof.

FIG. 9 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 10 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 11 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 12 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 13 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 14 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 15 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 16 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 17 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 18 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 19 is a diagram showing a matrix for explaining the operation of the main part.

FIG. 20 is a configuration diagram of an example of an inverse discrete cosine transform device according to the present invention.

FIG. 21 is a block diagram showing a configuration of a main part thereof.

FIG. 22 is a configuration diagram of another example of the discrete cosine transform device according to the present invention.

FIG. 23 is a configuration diagram of another example of the inverse discrete cosine transform device according to the present invention.

FIG. 24 is a block diagram showing a configuration of a conventional device.

FIG. 25 is a time chart diagram for explaining the operation of the conventional device.

FIG. 26 is a diagram for explaining the present invention.

FIG. 27 is a diagram for explaining the present invention.

[Explanation of symbols]

41 1st rearrangement circuit 42 4th order inner product arithmetic circuit whose coefficients are +1 and -1 43 2nd rearrangement circuit 44 8th order 2nd inner product whose coefficients are 0, +1 and -1 Arithmetic circuit 45 Third inner product arithmetic circuit including memory storing data components of constant matrix 46 Third rearrangement circuit

Claims (4)

[Claims] 1. An inner product calculation circuit for calculating an inner product of a matrix,
In a discrete cosine transform device including a rearrangement circuit for rearranging data components of a matrix in a predetermined order, a fourth-order first inner product arithmetic circuit having coefficients of +1 and -1, and a coefficient of 0, +1 and -1 The second inner product arithmetic circuit of the 8th order and the third inner product arithmetic circuit including the memory in which the data components of the constant matrix are stored are provided, and the input data of 8 rows and 8 columns is converted into the first rearrangement circuit. To the first inner product arithmetic circuit, and to supply the output of the first inner product arithmetic circuit to the second inner product arithmetic circuit via the second rearrangement circuit. Is directly supplied to the third inner product arithmetic circuit and the output of the third inner product arithmetic circuit is derived via a third rearrangement circuit. .. 2. An inner product calculating circuit for calculating an inner product of a matrix,
In an inverse discrete cosine transform device including a rearrangement circuit for rearranging data components of a matrix in a predetermined order, a fourth inner product arithmetic circuit including a memory in which data components of a constant matrix are stored, and coefficients of 0, +1 and An eighth-order fifth inner product arithmetic circuit which is −1 and a fourth-order sixth inner product arithmetic circuit whose coefficients are +1 and −1 are provided, and the input data of 8 rows and 8 columns is fourth sorted circuit. To the fourth inner product arithmetic circuit, the output of the fourth inner product arithmetic circuit is directly supplied to the fifth inner product arithmetic circuit, and the output of the fifth inner product arithmetic circuit is supplied to the fifth inner product arithmetic circuit. The inverse discrete cosine is characterized in that the sixth inner product arithmetic circuit is supplied through the rearrangement circuit and the output of the sixth inner product arithmetic circuit is derived through the sixth rearrangement circuit. Converter. 3. An inner product calculating circuit for calculating an inner product of a matrix,
In a discrete cosine transform device including a rearrangement circuit that rearranges the data components of a matrix in a predetermined order, a parallelization circuit that parallelizes matrix data that is serially supplied for each predetermined number, and a coefficient of +1 and -1 A certain fourth-order inner product arithmetic circuit, an eighth-order second inner product arithmetic circuit whose coefficients are 0, +1 and -1, and a third inner-product arithmetic operation including a memory in which data components of a constant matrix are stored. A circuit, and the predetermined number of the first, second, and third inner product arithmetic circuits are arranged in parallel, and input data of 8 rows and 8 columns is input to the parallelization circuit through the first rearrangement circuit. Each data of the parallel data supplied and output from the parallelization circuit is supplied to each of the predetermined number of the first inner product arithmetic circuits, and the output of each of the first inner product arithmetic circuits is directly input to the predetermined number of the predetermined inner product arithmetic circuits. Corresponding to the second inner product arithmetic circuit in The output of each of the second inner product arithmetic circuits is directly supplied to the corresponding third inner product arithmetic circuit of the predetermined number, and the output of the predetermined third inner product arithmetic circuits is serialized. A discrete cosine transform device characterized in that it is converted into data and then derived through a third rearrangement circuit. 4. An inner product calculating circuit for calculating an inner product of a matrix,
In an inverse discrete cosine transform device including a rearrangement circuit that rearranges the matrix data components in a predetermined order, a parallelization circuit that parallelizes the matrix data that is serially supplied for each predetermined number, and a constant matrix data component A fourth inner product arithmetic circuit including a stored memory; an eighth-order fifth inner product arithmetic circuit whose coefficients are 0, +1 and -1; and a fourth-order sixth inner product arithmetic coefficient whose coefficients are +1 and -1 An arithmetic circuit, the fourth, fifth, and sixth inner product arithmetic circuits are arranged in parallel, and the input data of 8 rows and 8 columns is input to the parallelizing circuit via a fourth rearrangement circuit. And each data of the parallel data output from the parallelization circuit is supplied to the corresponding fourth inner product calculation circuit in the predetermined number, and the output of each fourth inner product calculation circuit is directly output. The fifth inner product corresponding to the predetermined number To the corresponding sixth inner product arithmetic circuit among the predetermined number, and at the same time to supply the output of each of the fifth inner product arithmetic circuits to the corresponding sixth inner product arithmetic circuit. An inverse discrete cosine transform device characterized in that the output is converted into serial data and then derived through a sixth rearrangement circuit.