JP3182287B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (hereinafter referred to as a DSP) for controlling the switching of such registers and memories during debugging when transferring data between debug registers and memories of a microprocessor.
And a register / memory switching control device for a microprocessor.

[0002]

2. Description of the Related Art Due to advances in semiconductor technology and microprocessor architecture, the memory space of a processor is divided into a program memory space and a data memory space, and RISC processors, DSPs and the like adopting a Harvard architecture for speeding up instruction execution. Practical use is progressing.

[0003] The signal processing performed by such a DSP can perform high-precision processing as compared with analog processing. In addition, arbitrary characteristics such as filter characteristics can be stably and uniformly obtained by setting parameters. It has the feature that it is not necessary to make fine adjustments due to the accuracy of parts as compared with the analog configuration, and has been rapidly spreading in various fields in recent years. As an application field of this DSP, it is used in a wide field of digital signal processing such as voice, communication, measurement, image, and sound.

FIG. 4 is a schematic configuration diagram of a conventional microprocessor.

In FIG. 4, reference numeral 1 denotes a program counter in which the address of the next program to be executed is stored;
Is an instruction register for temporarily reading and storing an instruction code stored in the program memory 2, and 4 is an instruction register for temporarily storing an instruction code stored in the program memory 2. An instruction decoder for decoding an instruction code stored therein; 5, an immediate data register for storing immediate data; 6, data for storing data required for calculation, a result during calculation, or a calculation result including a final result of calculation. Memory, 7
Is an address register for designating an address at the time of data read / write in the data memory 6, and 8 is for executing arithmetic processing according to the instruction code decoded by the instruction decoder 4 while using the arithmetic data of the data memory 6. An operation unit 9 for storing operation data transmitted via a data bus in accordance with an instruction decoded by the instruction decoder 4;
Reference numeral 10 denotes an accumulator that accumulates and stores the operation results performed by the operation unit 8.

Reference numeral 11 denotes the address of the program counter 1 or the operation data of the address register 7, the data register 9, or the accumulator 10 when debugging a program to be debugged (for example, an operation program). Is temporarily stored in the debug register 11, and the address or operation data stored in the debug register 11 is transmitted to a debug processing device (not shown) via an external interface (not shown). Is done.

In the above configuration, the address of the program counter 1 generates an address of the program memory 2 in which an instruction to be executed next is stored in synchronization with the rising of a clock (not shown).

In accordance with the address of the program counter 1, the instruction code of the operation program is sent from the program memory 2 to the instruction register 3, and the instruction register 3 loads the instruction code. And to the immediate data register 5.

Next, the instruction decoder 4 increments the address of the address register 7 by
Alternatively, a control command such as decrement is transmitted. In accordance with this, the address data is transmitted from the address register 7, and after the data in the data memory 6 corresponding to the address data is read, the data is transmitted to the data register 9 and the like via the data bus.

On the other hand, the arithmetic unit 8 performs arithmetic processing using the arithmetic data stored in the data register 9, and the processing result is temporarily stored in the accumulator 10 and then transmitted and stored in the data memory 6 as appropriate. Is done.

Further, when the arithmetic processing is to be continued, the arithmetic data stored in the data memory 6 is sent to the data register 9, and the arithmetic unit 8 uses this arithmetic data,
The arithmetic processing is continued, and the final result of the arithmetic operation at this time is stored in the data memory 6 from the accumulator 10, thereby ending a series of arithmetic processing.

By the way, the arithmetic program stored in the program memory 2 may have an error. In order to find out and correct the error (hereinafter referred to as debugging), the arithmetic processing in the arithmetic unit 8 is temporarily interrupted. At that time, the address of the program counter 1 or the address register 7, the data register 9, or the accumulator 10
Is sent to the debug register 11 and is sent from the debug register 11 to a debug processing device having a display via an external interface, so that debugging can be performed.

Here, the bit width of the normal program bus is limited, and as shown in FIG. 5A, such a program bus, for example, the bits of the program memory 2 to the instruction register 3 and the bits of the instruction register 3 to the instruction recorder 4 are used. Assuming that the width is 16 bits, the data stored in the accumulator 10 is stored in the first 6 bits of the program in the debug register 11.
A debugging instruction (opcode) for transferring the data is provided, and the next five bits are a transfer source register of the data,
That is, a code indicating the accumulator 10 is arranged, and a code indicating a transfer destination register of the data, that is, a debug register 11 is arranged in the next 5 bits.

In order to send the operation data or the address of the program counter 1 to the debug register 11 when debugging the operation program, the program counter 1, address register 7, data Codes indicating the register 9, the accumulator 10, and the debug register 11 are transferred from the debug processing device to the debug register 1 via an external interface.
1 and then the debugging instruction is sent to the program memory 2 via the data bus.

The instruction for debugging is sent to the instruction register 3, the instruction register 3 loads the instruction, and the instruction code is sent to the instruction decoder 4. The instruction decoder 4 shown in FIG. The code indicating the transfer source register is stored in the program counter 1, the address register 7, the data register 9, and the accumulator 10, and the code indicating the transfer destination register is stored in the debug register 11.
As a result, the address of the program counter 1 or the operation data of the address register 7, the data register 9, and the accumulator 10 is transmitted to the debug register 11 and then transmitted to the debug processing device via the external interface. become.

[0016]

However, debugging instructions are used only when debugging a program or system software, and are usually not used by a user. The codes indicating the transfer source register and the transfer destination register must be sent to the program counter 1, the address register 7, the data register 9, the accumulator 10, and the debug register 11 via the data bus and the program bus.

For this reason, in the bit width of the program bus, only the codes indicating the transfer source register and the transfer destination register occupy 10 bits out of the 16 bits. When a user executes an instruction (opcode), an opcode for operation or the like cannot be effectively allocated to the program bus.

[0018]

The microprocessor according to the present invention comprises a program counter storing an address of a program to be executed next, a register storing operation data, an address transferred from the program counter during debugging, or the register A debug register for storing the operation data transferred from the memory, a memory for storing the operation data, and a debug program transmitted through the debug register during debugging, and a memory for storing the debug data transmitted from the memory. An instruction decoder for decoding instructions of the debug program; an operation unit for performing an operation based on the operation data stored in the register in accordance with the instruction from the instruction decoder; Address transferred from the data, in order to store the operation data which is transferred from the register, the register from the instruction decoder /
In response to the memory switching signal, a write signal is sent to the debug register. On the other hand, at the start of the operation, the memory stores the address transferred from the program counter and the operation data transferred from the register.
A register / memory switching control unit for receiving a register / memory switching signal from the instruction decoder and transmitting a write signal to the memory, wherein a bit distribution of an instruction transmitted from the memory is In addition to the read / write signal, it is characterized by comprising a code indicating a transfer source or a transfer destination of the register or the debug register.

[0020]

The debug / memory switching control unit selects the debug register at the time of debugging, and sends the operation data before the interruption during the arithmetic processing or the address of the program counter to the debug processing device via the debug register. I do.

On the other hand, at the end of debugging, the address of the program counter is returned to the program counter,
The operation program is sent to the memory via the debug register, and the debug / memory switching control unit selects the memory to write the operation data after the interruption during the operation processing to the memory.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a schematic block diagram of a microprocessor including a register / memory switching control unit during debugging according to the present invention. In FIG. 1, components having the same functions as those in FIG. 4 of the conventional example are denoted by the same reference numerals, and the description thereof is omitted. Similarly, it is 16 bits.

Here, the first point in which the configuration of the present invention is different from that of the prior art is that the operation data sent to the data memory 6 during normal operation processing or the address of the program counter 1 is stored in the debug register 11 during debugging. The debug register 11 is selected so as to be transmitted, while the register / switch is performed so as to select the data memory 6 so that the operation result or the like when the operation is performed by the operation unit 8 after the end of debugging is transmitted to the data memory 6. Memory switching control unit 12
With the instruction decoder 4 and the data memory 6,
And the debug register 11.

On the other hand, FIG. 5B shows the bit allocation of the program bus connected to the program memory 2 in the present invention. Is allocated so as to designate a 5-bit code indicating one of the transfer source register and the transfer destination register in addition to the 1-bit data read / write signal. Along with this, the bit width used for the operation code at the time of execution of the operation is not restricted among the total bit width of the program bus regardless of the time of debugging or the time of execution of the operation. Can be used effectively.

The operation of the register / memory switching control unit 12 at the time of debugging of the microprocessor of the present invention or after the debugging is completed to transfer data between the debug register / memory will be described below.

The operation data obtained by execution of the operation is to be stored in the address register 7, the data register 9, or the accumulator 10. However, since such a storage processing procedure is the same as the conventional example, In the following, a description will be given of processing after transferring the address of the program counter 1, the address register 7, the data register 9, and the operation data stored in the accumulator 10 to the debug register 11.

First, at the time of debugging, the debugging processor sends a debugging program to the debugging register 11 via the external interface, and then sends the debugging program to the program memory 2 via the data bus. The program memory 2 stores a debugging program.

The instruction code of the debugging program is sent to an instruction register 3, which loads the instruction code, and the instruction code is stored in an instruction decoder 4.
Sent to

The instruction decoder 4 includes an accumulator 10, a data register 9, an address register 7,
And a read signal to the program counter 1 and a register / memory switching signal to the register / memory switching control unit 12.

Thus, the register / memory switching control unit 12 sends a write signal to the debug register 11 so that the address of the program counter 1 or the operation data of the address register 7, the data register 9, or the accumulator 10 is changed. The data is sent to and stored in the debug register 11 via the data bus.

Here, the address and the operation data stored in the debug register 11 are sent to the debug processing device via the external interface, so that the debug operation can be performed.

When the debugging operation is completed, the instruction decoder 4 sets the register / memory switching control unit 1
2, the register / memory switching control unit 12 sends the read signal to the debug register 11 to send the address when the operation was interrupted earlier to the program counter 1,
An arithmetic program is sent to the program memory 2 from the debug processing device via the debug register 11.

Thus, the instruction decoder 4 sends a register / memory switching signal to the register / memory switching control unit 12, selects the data memory 6, and sends a write signal to the address register 7. The address register 7 sends an address signal to the data memory 6, and the register / memory switching control unit 12 sends a write signal to the data memory 6. As a result, the operation data stored in the accumulator 10 is stored in the data memory 6 thereafter.

In this way, the arithmetic unit 8 can continue the interrupted arithmetic processing, and when the debug processing unit issues an instruction for the debug processing again, the program counter 1, the address register 7, the data register The address and the operation data are transmitted again from the register 9 and the accumulator 10 to the debug register 11, and the above-described debug processing is repeatedly performed.

FIG. 2 is an example of a circuit diagram of the register / memory switching control unit 12, and FIG.
(Set signal of debug register 11), and REGR
FIG. 3B shows a logical value of REGSEL (selection signal of debug register 11) of DFF in ST (reset signal of debug register 11), and FIG. 3B shows MWR (write signal of data memory 6) and REGWR (REGWR signal in REGSEL signal). FIG. 4 is a diagram showing logical values of a debug register 11 (write signal of the data memory 6) and MEMWR (write signal of the data memory 6). These diagrams are used when writing to the debug register 11 or the data memory 6, and are driven by active low. It shall be. FIG. 3C shows MRD (read signal of data memory 6) and REGS.
It is a figure which shows the logical value of REGRD (read signal of the debug register 11) and MEMRD (read signal of the data memory 6) in an EL signal. Such a figure is used at the time of reading of the debug register 11 or the data memory 6, It shall be driven by active low.

Here, the correspondence between the signal lines shown in FIG. 2 and the signal lines shown in FIG. 1 will be described. REGSET and REGRST in FIG. 2 are connected from the instruction decoder 4 in FIG. MWR and MRD corresponding to the register / memory switching signal
Is the register / from the instruction decoder 4 in FIG.
This corresponds to a read / write signal connected to the memory switching control unit 12.

On the other hand, REGWR and REGRD of FIG.
1 corresponds to the read / write signal connected to the debug register 11 from the debug / memory switching control unit 12 in FIG. 1, and MEMWR and MEMRD are the debug / memory signals in FIG.
This corresponds to a read / write signal connected to the data memory 6 from the memory switching control unit 12.

Thus, the above REGSET and REGR
The ST signal is finally connected to the A1 terminals of the OR1 to OR4 circuits, the MWR signal is connected to the A2 terminals of the OR1 and OR2 circuits, respectively, and the MRD signal is connected to the OR3,
And the A2 terminal of the OR4 circuit.

In the configuration of FIG. 2, when the debug / memory switching control unit 12 selects the debug register 11, the signal of the second stage in FIG.
Is "0" and REGSEL is "1", REGWR becomes "0", which enables writing to the debug register 11. At the same time, the first of FIG.
The signal of the stage, that is, MRD is “0”, REGSEL “0”
At this time, the MEMRD becomes "0", which makes it possible to read the operation data from the data memory 6.

On the other hand, in the configuration of FIG. 2, when the debug / memory switching control unit 12 selects the data memory 6, the signal of the first stage in FIG. 3B, that is, MWR is "0" and REGSEL is When it is "0", the MEMWR becomes "0", whereby writing to the data memory 6 becomes possible. Thereafter, the result of the arithmetic processing in the arithmetic unit 8 is sent to the data memory 6. At the same time, in order to continue the interrupted arithmetic processing by the arithmetic unit 8, FIG.
The signal of the second stage of (c), that is, MRD is “0”, REG
When SEL is “1”, REGRD becomes “0”, whereby data stored in the debug register 11 can be read. The read address of the debug register 11 is stored in the program counter 1 and in the debug register 11. Are returned to the program memory 2 respectively.

As described above, the debug / memory switching control unit 12 selects the debug register 11 at the time of debugging, so that the result of the arithmetic processing before interruption during the arithmetic processing is processed via the debug register 11 for debugging processing. On the other hand, by selecting the data memory 6 at the end of debugging, the result of the arithmetic processing after the interruption during the arithmetic processing can be written into the data memory 6 and stored in the debug register 11 until then. The address of the program counter 1 and the operation program are returned to the original registers.

By the way, the present invention is not limited to the case where the bit width of the program bus is 16 bits, but the present invention can be applied to 32 bits, and even 48 bits.
In such a case, the bit allocation of the transfer target register of the program bus in FIG. 5B is determined by the total number of the program counter 1, the address register 7, the data register 9, the accumulator 10, and the like.

[0044]

As is apparent from the above description, according to the present invention, when data is transferred between a debug register and memory after debugging or after debugging is completed, in addition to the 1-bit read / write signal, The data transfer between the debug register and the memory can be performed only by designating a code indicating one of the transfer target registers of the transfer source register and the transfer destination register.

Further, when the user executes an instruction (opcode) other than the debug instruction, the bit width used for the opcode out of the total bit width of the program bus is smaller than that of the conventional program bus. Can be effectively allocated to the program bus.

Therefore, in the related art, if the codes indicating the transfer source register and the transfer destination register are two bits or more, the present invention can provide a remarkable effect.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a microprocessor including a register / memory switching control device of the present invention.

FIG. 2 is a circuit diagram of a register / memory switching control unit shown in FIG.

FIG. 3 is a diagram showing logical values of a register / memory switching control unit shown in FIG. 2;

FIG. 4 is a schematic configuration diagram of a conventional microprocessor.

FIG. 5 is a conceptual diagram illustrating bit allocation of a bus according to the related art and the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Program counter 2 Program memory 3 Instruction register 4 Instruction decoder 5 Immediate data register 6 Data memory 7 Address register 8 Operation part 9 Data register 10 Accumulator 11 Debug register 12 Register / memory switching control part

──────────────────────────────────────────────────続 き Continuation of the front page (72) Akira Yoshida 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-4-276822 (JP, A) JP JP-A-5-233347 (JP, A) JP-A-57-109058 (JP, A) JP-A-1-144135 (JP, A) JP-A-5-233377 (JP, A) JP-A-57-23150 (JP , A) JP-A-62-98437 (JP, A) JP-A-1-121945 (JP, A) JP-A-2-12436 (JP, A) Real opening 63-9651 (JP, U) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/28-11/36 G06F 9/30-9/42

Claims (2)

(57) [Claims] An address of a program to be executed next is stored.
Stores the program counter and operation data
Register and the above program counter when debugging.
From the address transferred from the above or from the above register
A debug register for storing the calculated operation data,
In addition to storing the above operation data, when debugging,
Debug program sent via program register
Memory for storing the RAM and a device transmitted from the memory.
Instructions for decoding the instructions of the programming program
A decoder and an instruction from the instruction decoder
According to the operation data stored in the register
An operation unit that performs an operation based on
The debug register is transferred from the above program counter.
Address received from the above register
Instruction deco
Receiving the register / memory switching signal from the
Sends a write signal to the bag register and starts operation
When the memory is transferred from the program counter
Address, operation transferred from the above register
To store the data,
Receiving the register / memory switching signal from the
Register / memory switching controller for sending write signal to memory
And the bit allocation of the instruction sent from the memory is
In addition to the arithmetic data read / write signal,
Indicates the source or destination of the debug register or transfer
Microprocessor characterized by being composed of code
Rosessa . 2. The method according to claim 1, wherein the instruction decoder is a debugger.
In accordance with the instructions of the
Address in the program counter
Data and send the data through the debug register.
Send the program to be bagged to the above memory,
After that, the instruction decoder is
Decoding the instruction of the operation program sent from the
Instruction to the debug / memory switching control unit, and
After the debug, the register / memory switching control unit
According to the instruction from the instruction decoder,
Sending a write signal to the memory, thereby
Memory, a program is subject to the debug execution
Operation data transferred from the above register when
2. The microcomputer according to claim 1, wherein
Rosessa .