JP3180928B2 - Time division multiplex signal receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for setting up a time-division multiplex line for digital signals between one master station and a plurality of mobile stations via a common communication medium. To a time-division multiplexed signal receiving circuit.

[0002]

2. Description of the Related Art In a system for transmitting and receiving a burst digital signal such as a time division multiplex line or packet transmission,
FIG. 4 shows a conventional configuration example of a receiving circuit that extracts a reception timing from a reception demodulation output and sequentially determines a reception data sequence. In FIG. 4, reference numeral 11 denotes a phase comparator, which is a reception demodulation output DEM-OU obtained from a reception demodulator (not shown).
T is input, the phase of the change timing is compared with the reception timing RT output from the present configuration, and a phase comparison output indicating the relative phase lag / advance state is supplied to the outside. Reference numeral 12 denotes a pulse addition / removal circuit, which is a clock signal C supplied from the clock oscillator 13 corresponding to each of the phase delay / lead states indicated by the phase comparison output.
A clock CLK ′ that has been subjected to pulse addition / removal processing is output to LK. The pulse addition / removal circuit 12 receives an enable signal EN for controlling activation / stop of the pulse addition / removal processing operation, and activates the pulse addition / removal processing operation while receiving the digital signal. If it is not received, it can be stopped. The enable signal EN is generated by detecting or predicting the arrival of a burst digital signal by some other external means. An oscillator 13 generates the clock signal CLK. Reference numeral 14 denotes a frequency divider, which divides the frequency of the clock signal CLK ′ to which the pulse addition / removal obtained from the pulse addition / removal circuit 12 has been applied, feeds it back to the phase comparator 11 as a reception timing RT, and outputs the same to the outside. . Reference numeral 15 denotes a judgment circuit which receives the reception demodulation output DEM-OUT according to the timing of RT, and judges and outputs a series of the reception data RD.

With the above configuration, when the enable signal EN is raised and the operation of the pulse addition / removal circuit 12 is activated, the reference numerals 11, 12, and 14 function as a known Cesna-type digital PLL (Phase Locked Loop). .
That is, if the output RT of the frequency divider 14 is delayed with respect to the change timing of the reception demodulation output DEM-OUT, a pulse is added to CLK by the phase comparator 11, so that the phase of RT is advanced by one cycle of CLK. Can be Conversely, if the phase of RT advances, the pulse is removed from CLK, so that the phase of RT is delayed by one cycle of CLK. The above operation forms a digital phase locked loop,
Since the reception timing RT that is phase-synchronized with the DEM-OUT change timing is obtained, the normal determination operation by the determiner 15 is maintained. Further, in a state where the enable signal EN falls and the operation of the pulse addition / removal circuit 12 is stopped, the two clock signals CLK and CLK ′ are the same because the pulse addition / removal process is stopped. Is in a free-run state while maintaining the latest synchronization phase. Therefore, if the rise and fall operations of the enable signal EN are performed in synchronization with the effective arrival section of the burst digital signal, the phase drift of the reception timing RT due to noise occurs in the section where no digital signal is received. By maintaining the synchronization phase, a so-called flywheel operation can be realized, and in a section where a digital signal is being received, a stable phase synchronization operation can be obtained from the beginning of the section. .

[0004]

However, in the above-mentioned conventional configuration, time-division multiplex communication is performed between one master station and a plurality of (M) slave stations in a point-to-multipoint manner. In this case, a problem occurs in the receiving operation of the master station. To clarify this problem, FIG. 3 shows an example of a time chart of a possible reception operation in the master station. In the figure, S
D _1, SD _2, ..., each SD _M is burst number 1,
Time division transmission data of M slave stations transmitted at timings 2, 2,..., M, DEM-OUT schematically shows the eye pattern of the reception demodulation output of the master station, and RT schematically shows the reception timing. Note that DEM-OUT corresponding to SD ₁ , SD ₂ ,..., SD _M omits the delay time from transmission to reception demodulation output in order to make the correspondence easy to understand. , Reception timing RT indicates an ideal reception timing rising at the center point of the eye opening of the DEM-OUT eye pattern.

[0005] RT ₀ lowermost of Figure shows a free-run state of RT when shutting down the phase-locked operation, [Delta] [phi _1, [Delta] [phi ₂ in FIG, ..., [Delta] [phi _M each RT ₀ and RT
Is shown. As in the example shown,
In the point-to-multipoint time division multiplex communication, the phase of the transmission timing from a plurality of slave stations is generally unique to each slave station due to variations such as propagation delay between the master station and the slave station and transmission processing delay of the slave station. Δφ ₁ , Δφ
₂ ,..., Δφ _M are uncorrelated and different values. Therefore, burst-like digital signals that are temporally adjacent to each other may partially collide with the master station reception input. Therefore, a fixed-length non-signal section (guard space, FIG.
In the example described above, one symbol section is generally provided to prevent collision.

The receiving circuit provided in the master station must extract the ideal reception timing RT shown in FIG. 3 even under the above-mentioned conditions. However, in the conventional configuration shown in FIG. Since the synchronization phase of RT held when EN falls is always synchronized with the latest burst, if the next incoming burst is a digital signal from another slave station having a different phase as shown in FIG. The above-mentioned synchronization holding is invalidated, and an initial pull-in operation is required for each burst. For the initial pull-in operation, it is inevitable to add a preamble signal dedicated to reception timing synchronization at the beginning of each burst, which causes a significant reduction in transmission efficiency. Therefore, in order to solve this problem, the circuits having the conventional configuration shown in FIG. 4 are provided by the number of multiplexes (the maximum number of slave stations corresponding to the master station = M) times, and the output of the reception timing RT obtained from each circuit is obtained. Although a configuration in which switching is used sequentially is required, in this configuration, the circuit scale increases in proportion to the number of multiplexes M, and there is a problem in miniaturization and low power consumption. An object of the present invention is to realize a periodic burst transmission such as a time-division multiplexed signal, when a master station receives burst-like digital signals having different phases from a plurality of slave stations. In order to solve the problems arising in the configuration and to realize this, the circuit must be miniaturized and the IC
Another object of the present invention is to provide a time division multiplexed signal receiving circuit which can be easily implemented.

[0007]

SUMMARY OF THE INVENTION A time division multiplexed signal receiving circuit according to the present invention is provided for receiving each burst in a time division multiplexed frame.
Judgment of signal demodulation output and synchronized reception timing RT
Time division for inputting to the circuit and judging and outputting the received data sequence
In the multiplex signal receiving circuit, the change in the received demodulated output
Delay of the phase of the reception timing RT with respect to the timing
Phase comparison that outputs a phase comparison output ε indicating the lag / advance state
And a preset indicating the start timing of each burst.
Phase offset provided externally in synchronization with the reset signal PR.
Initial value Δφi (i is the bar in the time-division multiplex frame)
And the initial value Δφi
On the other hand, a phase offset Δφ obtained by integrating the phase comparison output ε
Phase offset generation circuit that outputs
Burst number of the time-division multiplexed frame according to the control signal
In the storage area corresponding to the number i,
The phase offset Δφ in the imaging is stored and the next
At the beginning of the burst in the frame
The phase off is set as the initial value Δφi of the phase offset.
A phase offset storage circuit to be given to the set generation circuit;
Transmission frequency that is an integer (N) times the frequency of the reception timing
Divides the clock signal having
Outputs the free-run reference frequency dividing phase φo whose period is N
N dividing counter, the phase offset Δφ and the reference
The reception timing for obtaining the reception timing RT from the divided phase φo
Signal timing calculation means, and
Designation and reading of storage area corresponding to burst number i
The control signal for controlling writing is written in the phase offset
To the memory and to the tie at the beginning of the burst.
Generating the preset signal PR indicating the
Burst timing generation to be supplied to the phase offset generation circuit
A division multiplex signal receiving circuit when an adult circuit, before
The reception timing calculation means calculates the phase offset Δφ
And the reference frequency-divided phase φo.
The phase φ of the RT is defined as φ = [φo + Δφ] mod N (where
And [•] mod N is divided by N (equivalent to 2π radians).
The most significant bit of the remainder obtained by the expression
Output as reception timing RT and give to the determination circuit
And an adder to be provided to the phase comparator.
It is a sign .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Configuration] FIG. 1 is a diagram showing a configuration example of a time division multiplexed signal receiving circuit according to the present invention. In the figure, reference numeral 1 denotes a phase comparator, which includes a reception demodulation output DEM-OUT and a reception timing R.
T, and outputs a phase comparison output ε indicating the delay / advance state of the RT phase with respect to the DEM-OUT change timing. The phase comparator 1 can be realized by a D-type flip-flop when ε is binary-quantized, and by a counter and a register when ε is multi-valued. Reference numeral 2 denotes a phase offset generating circuit which outputs a phase offset Δφ obtained by integrating the phase comparison output ε. The integration function can be realized using, for example, an up-down counter or an accumulator (integrator) including an adder and a register. Note that the phase offset generation circuit 2 includes:
A preset signal PR indicating the start timing of each burst in the time division multiplex frame and an initial value Δφ _i (i is a burst number in the time division multiplex frame, 1 ≦ i ≦ M) of the phase offset Δφ are input, It is assumed that the initial value Δφ _i of the phase offset is preset in the phase offset generation circuit 2 at the timing of the beginning of each burst in synchronization with the preset signal PR. 3 is a phase offset memory circuit, stores the phase offset [Delta] [phi as an initial value [Delta] [phi _i at the end of the timing of the burst in the storage area corresponding to the burst number i division multiplexed within a frame time according to the control signal CONT supplied from the outside , and outputs the [Delta] [phi _i at the beginning of the timing of the burst in the next frame (burst number i) the phase offset generating circuit 2. Reference numeral 4 denotes an oscillator, which generates a clock signal CLK having an oscillation frequency that is an integer (N) times the frequency of the reception timing RT.

Reference numeral 5 denotes an N frequency dividing counter, and the oscillator 4
By dividing the CLK from N by N, one cycle (2
A free-run reference frequency dividing phase φ ₀ where N is N (equivalent to π radians) is output. Reference numeral 6 denotes an adder modulo N, and outputs a remainder obtained by dividing the result obtained by adding the phase offset Δφ and the reference frequency-divided phase φ ₀ by N. The most significant bit (MBS) of the output is output to the outside as a reception timing RT. Reference numeral 7 denotes a determination circuit which receives the reception demodulation output DEM-OUT according to the reception timing RT, and determines and outputs a sequence of the reception data RD. Reference numeral 8 denotes a burst timing generation circuit which controls the phase offset storage circuit 3 to designate a storage area corresponding to the burst number i in the time-division multiplexed frame and to control read / write.
And the preset signal PR indicating the timing of the start of the burst, and supplies them to the phase offset storage circuit 3 and the phase offset generation circuit 2, respectively.
Note that the timing of the burst reception from the slave station is synchronized with the timing of the burst transmission from the master station to the slave station as long as the system operates normally.
And PR can all be generated based on the burst transmission timing of the own station (master station).

[Operation] The operation of the present invention based on the configuration example of FIG. 1 will be described below. In the configuration of FIG. 1, the phase of the reception timing RT appearing at the output of the adder 6 modulo N is φ
Then, the following equation (1) is clearly established. phi = [phi ₀ + [Delta] [phi] _modN ............... (1) (where, [·] _modN is N (2 [pi radians or equivalent) remainder when divided by) wherein (1) according to phi ₀ and the MBS FIG. 2 shows the relationship between RT ₀ and φ and the RT of the MBS.
Shown in In the figure, φ ₀ and φ are shown in the upper row, and RT is shown in the lower row.
₀ and RT are indicated by solid and dashed lines, respectively. As shown in the figure, each of φ ₀ and φ becomes a periodic staircase waveform which returns to 0 each time it rises from 0 to 1 by N−1, and φ has a phase lead of φ ₀ by Δφ.
Therefore, RT is a time offset corresponding to a phase offset of Δφ with respect to RT ₀ .

[0011]

[Outside 1] (The preceding example in FIG. 2). From the above, by controlling the phase offset Δφ, the phase of RT which is the MBS of the output of the adder 6 modulo N is set to 1
It is clear that an arbitrary value can be set in steps of / N periods (corresponding to 2π / N radians). On the other hand, Δφ is
Since this is a value obtained by integrating the phase comparison output ε indicating the delay / advance state of the RT phase with respect to the change timing of OUT,
The loop composed of the phase comparator 1, the phase offset generating circuit 2 and the adder 6 modulo N is a negative feedback closed loop acting in a direction to cancel the phase shift indicated by ε in steps of 1 / N cycle, that is, It can be seen that a digital PLL is configured.

Now, using the above digital PLL configuration,
The operation when one master station receives time-division multiplexed signals from a plurality of slave stations will be described below. As already shown in FIG. 3, reception demodulation output DEM when a time-division multiplexed signal of burst numbers 1, 2,...
When the reception timing RT is ideally synchronized with −OUT, the RT must have a phase offset of Δφ ₁ , Δφ ₂ ,... Δφ _M with respect to the free-run state RT ₀ of RT. Due to the function of the digital PLL, at the end timing of each reception burst, the actual reception timing RT is synchronized with the value closest to RT in FIG. 3, and the phase φ of RT is (1)
Since the value is given by the equation, the output Δφ of the phase offset generating circuit 2 at this time is a value closest to the above Δφ ₁ , Δφ ₂ ,..., Δφ _M. The above-mentioned Δφ is stored in the phase offset storage circuit 3 at the end timing of each burst by the burst timing generation circuit 8, and is output to the phase offset generation circuit 2 at the start timing of the burst in the next frame. Is preset as the initial value of. The preset enables a reception operation in which the synchronization state is maintained from the beginning of each burst.

Here, the frequency accuracy of the output CLK of the oscillator 4 for effective operation of the above-mentioned memory holding operation will be examined. Now, the reception timing RT respectively f _RT and f _CLK the frequency of CLK, f _CLK of the error (frequency offset) of Delta] f _CLK, the timing memory holding operation per one slave station between the master station and the slave station, That is, the free-run time is T
_{When F is} set and the allowable value of the free-running phase shift at the RT between the master station and the slave station during the free-run is defined as 1 / N cycle or less, the following equation is established. The left side of the above equation (4) is a free-run phase shift at the reception timing RT. (2), (3), (4) from equation, the frequency accuracy Delta] f _CLK / f _CLK of f _CLK of the next (5)
It becomes an expression.

As a specific example, a "second generation cordless telephone system (TDMA.TD of 8 slots / frame)
D) ”and examine equation (5). The parameters of _fRT , M, and _TF in the present system are as follows. f _RT = 192 kHz (modulation speed) M = 4
(Number of slave stations connected simultaneously) Assuming that a practical value, N = 32, is set as the parameter N (frequency division number) of the digital PLL, f
_{Since CLK} = N · f _RT = 6,144 kHz, (5)
From the equation, the frequency accuracy of f _CLK is However, the above are the industrially low-cost, compact, and easily achievable precisions.

With the above configuration, even if the reception timings of the M bursts arriving from the M slave stations are different from each other, the phase offset of each burst can be handled in a time-division manner. It can be seen that the operation of extracting the reception timing and the operation of holding the memory can be realized independently for each case.

[0016]

As described above in detail, according to the structure of the present invention, although the digital PLL constituting the phase locked loop provided in the master station is a single circuit, the transmission timings of the digital PLLs are mutually different. In the burst reception from a plurality of slave stations having different phases, the synchronization of the reception timing can be ensured, so that the receiving circuit can be reduced in size and economy. In addition, since all circuits can be constituted by binary logic circuits, there is an advantage that the circuit is suitable for IC.

[Brief description of the drawings]

FIG. 1 is a configuration example diagram of a time division multiplexed signal receiving circuit according to the present invention.

FIG. 2 is a time chart illustrating the operation of the present invention.

FIG. 3 is a time chart for explaining the operation of the conventional technique.

FIG. 4 is a circuit diagram of a conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Phase offset generation circuit 3 Phase offset storage circuit 4 Oscillator 5 N frequency dividing counter 6 Adder 7 Judgment circuit 8 Burst timing generation circuit 11 Phase comparator 12 Pulse addition / removal circuit 13 Oscillator 14 Divider 15 Judgment circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H04L ^7/ 00-7/10

Claims (1)

(57) [Claims] 1. A method for each burst in a time division multiplex frame.
The reception demodulation output and the synchronized reception timing RT are determined.
Time to input to the constant circuit and judge and output the series of received data
In the division multiplex signal receiving circuit, the reception of the reception demodulation output with respect to a change timing
Phase comparison indicating phase delay / advance state at timing RT
A phase comparator for outputting an output ε, and a head of each burst
Externally in synchronization with the preset signal PR indicating the timing of
The initial value of the phase offset Δφi given by
Preset burst number in division multiplex frame)
And the product of the phase comparison output ε with the initial value Δφi.
Phase offset generator that outputs the calculated phase offset Δφ
Time division according to raw circuit and externally applied control signal
In the storage area corresponding to the burst number i of the multiplex frame
The phase at the end of the burst.
The offset of the corresponding bar in the next frame.
Initial value of the phase offset at the beginning of the strike
The phase given to the phase offset generation circuit as Δφi
An offset storage circuit, and a frequency of the reception timing.
A clock signal having a transmission frequency of an integer (N) times is divided by N
A free-run base in which one cycle is N
A divide-by-N counter that outputs a quasi-divided phase φo;
The reception from the offset Δφ and the reference frequency-divided phase φo
Receiving timing calculating means for determining the timing RT;
The burst number i in the time-division multiplex frame is recorded
The control signal for designating a storage area and controlling reading and writing.
Signal to the phase offset storage circuit and
The preset indicating the start timing of the burst
Generates a signal PR and supplies it to the phase offset generation circuit
-Division multiplexing with a burst timing generation circuit
A signal receiving circuit, wherein the receiving timing calculating means includes the phase offset Δ
φ and the reference frequency-divided phase φo, and
The phase φ of the ringing RT is given by φ = [φo + Δφ] mod N (where
And [•] mod N is divided by N (equivalent to 2π radians).
The most significant bit of the remainder obtained by the expression
Output as reception timing RT and give to the determination circuit
And an adder to be provided to the phase comparator.
Time-division multiplexed signal receiving circuit.