JP3177693B2 - Push-pull output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a push-pull type output stage in which an NPN transistor and a PNP transistor are not connected to each other in a complementary manner. Connect to
The present invention relates to a push-pull output circuit in which a collector of a lower NPN transistor is used as an output terminal.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional push-pull type output circuit of this type. The collector of the upper NPN transistor Q1 is connected to the power supply line E via a resistor R1 (120Ω), and the emitter is connected to the collector of the lower NPN transistor Q2 via a Schottky barrier diode D1. Schottky barrier diode D
1 has an anode connected to the emitter of the upper NPN transistor Q1 and a cathode connected to the lower NPN transistor Q1.
2 collectors. NPN to power line E
The collector of the driving transistor Q3 is of the resistance R2.
(2 kΩ), the emitter of which is connected to the resistor R3
(1 kΩ) to the ground line.
The collector of the driving transistor Q3 is connected to the base of the upper NPN transistor Q1, and the emitter of the driving transistor Q3 is connected to the lower NPN transistor Q1.
2 base. The base of the driving transistor Q3 is connected to the input terminal 1, and the collector of the lower-stage NPN transistor Q2 is connected to the output terminal 2. The Schottky barrier diode D1 is connected to the upper NPN
This is for preventing the type transistor Q1 and the lower-stage NPN type transistor Q2 from being simultaneously turned on.

[0003] When the input to the input terminal 1 input voltage V _IN is drive transistor Q3 is at the low level is in the OFF state, the upper NPN transistor Q1 is connected to the power supply line E its base via a resistor R2 While the base of the lower-stage NPN transistor Q2 goes to the ground level via the resistor R3 and is turned off. Therefore, the output voltage V _OUT from the output terminal 2 becomes a high-level voltage V _OUT-H obtained by dropping the power supply voltage Vcc of the power supply line E by the resistor R1, the upper-stage NPN transistor Q1, and the Schottky barrier diode D1.

Conversely, when the input voltage V _IN is at a high level and the driving transistor Q3 is in the ON state, the upper NPN transistor Q1 is turned off while the lower NPN transistor Q1 is turned off.
The PN transistor Q2 is turned on by the voltage across the resistor R3. Therefore, the output voltage V _OUT becomes the low level voltage V _OUT-L .

[0005] high-level voltage V _OUT-H is, ignoring the base current of the upper NPN transistor Q1, an estimated, the high level voltage V _OUT-H = supply voltage Vcc- base-emitter voltage of the upper NPN transistor Q1 V _BE- Forward voltage V _F of Schottky barrier diode D1
It is determined by ‥‥ (1).

The high-level voltage V _OUT-H and the low-level voltage V _OUT-L are specifically described as follows.

It is assumed that the power supply voltage Vcc = 3V. The base-emitter voltage V _{BE of the} upper-stage NPN transistor Q1 = 0.
7V, when a forward voltage V _F = 0.4V of the Schottky barrier diode D1, a high level voltage V _{OUT-H is, V OUT-H = Vcc-} V BE -V F = 3-0.7-0. 4 = 3-1.1 = 1.9 [V]〕 (2) Also, the low level voltage V _OUT-L is
Collector-emitter voltage V _{CE of} transistor Q2 =
Assuming 0.3V, V _OUT-L = V _CE = 0.3 [V] ‥‥‥‥‥‥‥‥‥‥
‥‥‥‥‥‥ (3)

As is apparent from the equation (2), the high level voltage V _OUT-H changes according to the power supply voltage Vcc. Also,
The subtracted 1.1V is the base-emitter voltage V _BE = 0.7V of the upper-stage NPN transistor Q1.
Of the upper and lower NPN transistors Q1 and Q2 at the same time.
Schottky barrier diode D1 for preventing N
With the forward voltage V _F = 0.4V. That is, V _OUT-H = Vcc-1.1 [V] ‥‥‥‥‥‥‥‥‥‥
‥‥‥‥‥‥ (4). By transforming this, V _OUT-H /Vcc=1−1.1/Vcccc
‥‥‥‥‥‥ (5), and the lower the power supply voltage Vcc, the lower the power supply voltage Vcc
The rate of reduction of the high level voltage V _OUT-H with respect to cc increases, and if a low voltage power supply voltage Vcc is used, the operation as a push-pull type output circuit becomes impossible.

When the power supply voltage Vcc = 5V and when Vcc = 3V
The following shows an example of the rate of decrease of the high level voltage V _OUT-H with respect to the power supply voltage Vcc.

When Vcc = 5 V, V _OUT-H = 5 V−1.1 V = 3.9 [V] Therefore, the high level voltage V _{OUT-H with} respect to the power supply voltage Vcc
The ratio of the decrease is (3.9 ÷ 5) × 100 = 78 [%] ‥‥‥‥‥‥‥
‥‥‥‥‥ (6)

When Vcc = 3 V, V _OUT-H = 3 V−1.1 V = 1.9 [V] Therefore, the high-level voltage V _{OUT-H with} respect to the power supply voltage Vcc is obtained.
The rate of decrease is (1.9 ÷ 3) × 100 ≒ 63 [%] ‥‥‥‥‥‥‥
‥‥‥‥‥ (7)

The low level voltage V _OUT-L is equal to the power supply voltage Vcc.
Regardless of the size of the lower NPN transistor Q2
Is determined by the collector-emitter voltage V _CE .

Therefore, in the conventional push-pull type output circuit described above, the lower the power supply voltage Vcc, the higher the level of the high-level voltage V _{OUT-H with} respect to the power supply voltage Vcc.
May increase, and the push-pull type output circuit may not be operable.

High level voltage V with respect to power supply voltage Vcc
_In order to improve and reduce the rate of decrease of _OUT-H , it is necessary to eliminate the Schottky barrier diode D1 for preventing the upper NPN transistor Q1 and the lower NPN transistor Q2 from turning on at the same time. It is becoming.

FIG. 4 shows a Schottky barrier diode D
1 indicates the potential of each part when the driving transistor Q3 is turned on. The base-emitter voltage V _{BE of the} lower NPN transistor Q2 is V _BE = 0.7V. In order for the lower-stage NPN transistor Q2 to be turned on, the voltage across the resistor R3 needs to be at least 0.7V. Drive transistor Q3 base-emitter voltage V _BE
= 0.7V, this driving transistor Q3
Requires at least 1.4 V as its base voltage. Therefore, the input voltage V _{IN is set} to 1.5
It is assumed that V or more is applied.

When the driving transistor Q3 is turned on, the power supply line E supplies a resistor R2 and the driving transistor Q
3. A current flows through the resistor R3. The voltage across the resistor R3 becomes 0.7 V, and the lower-stage NPN transistor Q2 is turned on. The collector of the lower NPN transistor Q2
An emitter-to-emitter voltage V _CE = 0.3 V is generated at the output terminal 2, and the output voltage V _OUT becomes the low level voltage V _OUT-L . on the other hand,
When a current flows through the drive transistor Q3, the collector voltage of the driving transistor Q3 as its collector-emitter voltage V _CE = 0.4V, 0.7V +
0.4V = 1.1V. Base-emitter voltage V _BE = 0.7 V of upper-stage NPN transistor Q1 and forward voltage V _F = 0.4 of Schottky barrier diode D1
V, the collector voltage of the lower NPN transistor Q2 is 0.3V, and 0.7V + 0.4V + 0.3V = 1.
Since it is 4V, even if the base voltage of the upper NPN transistor Q1 becomes 1.1V, the upper NPN transistor Q1 does not reverse to the ON state and keeps the OFF state.

If the Schottky barrier diode D1
If there is no, since 0.7V + 0.3V = 1.0V, the base of the upper-stage NPN transistor Q1 is 1.1V.
If there is V, the upper NPN transistor Q1 is inverted to the ON state, and both the upper and lower NPN transistors Q1 and Q2 are turned ON at the same time. That is, the Schottky barrier diode D1 having the forward voltage V _F = 0.4V is connected to both the upper and lower NPN transistors Q
1 and Q2 are prevented from turning on at the same time. That is, it is possible to prevent a very large through current from flowing through both the NPN transistors Q1 and Q2 due to the simultaneous ON, thereby preventing the NPN transistors Q1 and Q2 from being destroyed.

[0018]

However, as described above, when the power supply voltage Vcc is reduced to, for example, 3 V, the ratio of the decrease in the high-level voltage V _{OUT-H to} the power supply voltage Vcc becomes large, and the push-pull type output is reduced. The circuit may not be able to operate. To avoid this, it is necessary to eliminate the Schottky barrier diode D1.

FIG. 5 shows a Schottky barrier diode D
1 shows the potential of each part when the drive transistor Q3 is turned on with the input voltage V _IN = 1.5 V after removing 1. When the driving transistor Q3 is turned on, the resistor R3
Is 0.7 V, the lower NPN transistor Q2 is turned on. Then, 0.3 V is generated at the output terminal 2 as the low level voltage V _OUT-L . On the other hand, when a current flows through the driving transistor Q3, the collector voltage of the driving transistor Q3 becomes 0.7V +
0.4V = 1.1V. The base-emitter voltage V _{BE of the} upper NPN transistor Q1 is 0.7 V, the lower N
Since the collector voltage of the PN transistor Q2 is 0.3V and 0.7V + 0.3V = 1.0V (the forward voltage V _F of the Schottky barrier diode D1 = 0.4)
V is not present), and when the base voltage of the upper-stage NPN transistor Q1 becomes 1.1 V, this transistor Q1 is turned off.
Invert from state to ON state. That is, both the upper and lower NPN transistors Q1 and Q2 are turned on at the same time.

The above can be summarized as follows. That is, when the power supply voltage Vcc is reduced, the rate of decrease of the high-level voltage V _OUT-H with respect to the power supply voltage Vcc becomes large, and it becomes impossible to operate as a push-pull type output circuit. Therefore, it is necessary to reduce the rate of decrease of the high level voltage V _OUT-H with respect to the power supply voltage Vcc. For this purpose, the Schottky barrier diode D1
Can be removed, but in this case, both NPN transistors Q1 and Q2 of the output stage to be subjected to the push-pull operation are operated.
2 are turned on at the same time. Since the resistance value of the resistor R1 is small, when both the NPN transistors Q1 and Q2 are turned on at the same time, the current flowing through the both NPN transistors Q1 and Q2 becomes a very large through current, and the NPN transistors Q1 and Q2 are destroyed. Would.

The present invention has been made in view of the above circumstances, and has been made to eliminate the Schottky barrier diode so that the push-pull type output circuit operates under a lower power supply voltage. It is another object of the present invention to prevent both NPN transistors of an output stage connected vertically from being simultaneously turned on.

[0022]

The present invention is as follows to solve the above-mentioned problems. That is, the present invention
The push-pull type output circuit of
And both the upper and lower transistors are N
Use a PN type transistor,
Directly to the collector of the lower NPN transistor.
Connect, connect the connection point to the output terminal, upper NPN type
Connect the collector of the transistor to the power supply line,
Ground the emitter of the PN transistor to ground level
And drives the upper NPN transistor.
Upper drive transistor and lower NPN transistor
And the lower drive transistor that drives the
The transistor for the upper drive is provided independently.
Grounds its emitter directly to ground level,
The stage drive transistor has its emitter connected to the lower stage NPN.
Ground via a resistor for adjusting the base voltage of the transistor
And is grounded to the ground level.

[0023]

The push-pull type output circuit according to the present invention comprises an upper stage NP
Between the N-type transistor and the lower NPN transistor
Directly without going through a Schottky barrier diode
And both upper and lower NPN transistors
It can be prevented from turning on at the same time. And
Since the Schottky barrier diode was omitted,
Even if the source voltage is lowered, the original function of the push-pull type output circuit
Performance can be demonstrated.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a push-pull type output circuit according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a push-pull type output circuit in which NPN transistors are vertically connected as output stages.

In the output stage, the collector of the upper NPN transistor Q10 is connected to the power supply line E via a resistor R11 (120Ω), and the collector of the lower NPN transistor Q20 is connected to the upper NPN transistor Q10.
And the emitter of the lower-stage NPN transistor Q20 is grounded to the ground level. A connection point between the emitter of the upper-stage NPN transistor Q10 and the collector of the lower-stage NPN transistor Q20 serves as an output terminal 12 for outputting the output voltage V _OUT to the next stage circuit.
It is connected to the. A Schottky barrier diode as in the conventional example is not inserted between the upper NPN transistor Q10 and the lower NPN transistor Q20.

The base of the upper-stage NPN transistor Q10 is connected to the collector of an NPN-type upper-stage drive transistor Q31, and the connection point is connected to the power supply line E via a resistor R12 (3 kΩ). The emitter of Q31 is grounded. The base of the lower NPN transistor Q20 is connected to the emitter of the lower driving transistor Q32 of the NPN type. The collector of the lower drive transistor Q32 is connected to the power supply line E via a resistor R13 (2 kΩ), and the emitter is grounded via a resistor R14 (1 kΩ). The base of the upper drive transistor Q31 is connected to the collector of an NPN upper control transistor Q41, the collector of which is connected to the power supply line E via a resistor R15 (3 kΩ), and the emitter is grounded. The base of the lower drive transistor Q32 is NP
The collector is connected to the collector of the N-type lower control transistor Q42, the collector is connected to the power supply line E via the resistor R16 (3 kΩ), and the emitter is grounded. The bases of both control transistors Q41 and Q42 are connected to each other and are connected to an input terminal 1 for applying an input voltage V _IN.
1 connected.

Next, the operation of the push-pull type output circuit configured as described above will be described.

When the input voltage V _IN applied to the input terminal 11 is at a low level of 0.7 V or less, both control transistors Q41 and Q42 are off. When the control transistors Q41 and Q42 are in the OFF state, the base voltages of both the drive transistors Q31 and Q32 are at the high level and the transistors are turned ON. Since the upper drive transistor Q31 is ON and its collector voltage is low, the upper NPN transistor Q10 is
The state becomes the F state. On the other hand, the lower drive transistor Q3
2 is ON and its emitter voltage is at a high level, so that the lower NPN transistor Q20 is ON. Even without a Schottky barrier diode,
The lower NPN transistors Q10 and Q20 are not simultaneously turned on. Lower stage NPN transistor Q20
Is in the ON state, the output voltage V
_OUT has a low-level voltage V of the collector-emitter voltage V _CE = 0.3 V of the lower NPN transistor Q20.
Output as _OUT-L .

Next, when the input voltage V _IN applied to the input terminal 11 is at a high level exceeding 0.7 V, both control transistors Q41 and Q42 are ON.
When the control transistors Q41 and Q42 are in the OFF state, the base voltages of both the drive transistors Q31 and Q32 are at a low level and are OFF. Since the upper drive transistor Q31 is in the OFF state and the collector voltage is at the high level, the upper NPN transistor Q10 is in the ON state. On the other hand, since the lower drive transistor Q32 is in the OFF state and its emitter voltage is at the low level, the lower NPN transistor Q20 is
The state becomes the FF state. The upper and lower NPN transistors Q10 and Q20 are not simultaneously turned on.

Since the upper NPN transistor Q10 is in the ON state and the lower NPN transistor Q20 is in the OFF state, the following high level voltage V _OUT-H is output to the output terminal 12 as the output voltage V _OUT. You. That is, the power supply voltage Vcc is set to 3 V, and the base-emitter voltage V _BE of the upper NPN transistor Q10 is set to 0.7 V. It is also assumed that the base current of upper NPN transistor Q10 is ignored. The high level voltage V _OUT-H is as follows: V _OUT-H = Vcc-V _BE = 3-0.7 = 2.3 [V]
‥‥‥‥‥‥ (8) High level voltage V _{OUT-H with} respect to power supply voltage Vcc
Is the ratio of (2.3２3) × 100 ≒ 77 [%] ‥‥‥‥‥‥‥
‥‥‥‥‥ (9) This is almost the same as 78 [%], which is the rate of decrease of the high-level voltage V _OUT-H with respect to the power supply voltage Vcc expressed by the equation (6) when the power supply voltage Vcc = 5 V in the conventional example. It is not a significant drop. When the power supply voltage Vcc = 3 V in the conventional example, the power supply voltage Vcc
The ratio of the decrease of the high level voltage V _{OUT-H to} (7)
As shown by the equation, it is considerably large at 63 [%], which may make it impossible to operate as a push-pull type output circuit.

However, in the embodiment of the present invention, the power supply voltage V
Even when cc is set as low as 3 V, the ratio of the decrease of the high level voltage V _OUT-H to the power supply voltage Vcc is 77 as described above.
[%], And can operate sufficiently as a push-pull type output circuit. In order to do so, the Schottky barrier diode is removed. However, both the upper and lower NPN transistors Q10 and Q20 are not turned on at the same time.
The N-type transistors Q10 and Q20 can be protected from destruction. In other words, the reliability as a push-pull type output circuit can be ensured, and the same function as the push-pull type output circuit using a 5V type power supply conventionally used is provided as a push-pull type output circuit of a 3V type power supply. Can be given.

As another embodiment, a circuit configuration as shown in FIG. 2 can be considered. This is because PNP transistors Q51, Q52, Q53, and Q54 are used in place of the resistors R12, R13, R15, and R16 in the circuit configuration of FIG. 1, and a PNP transistor Q55 and a resistor R17 are used.
(10 kΩ) and a constant current power supply I ₀ . With this configuration, the resistors R12, R13, R15, R
16, Q31, Q32, Q41, Q
42 is limited. As compared with the above embodiment, the circuit configuration is simplified by the smaller number of resistors. The operation is the same as in the above embodiment.

[0034]

As described above, according to the push-pull type output circuit of the present invention, the Schottky barrier diode can be used.
The upper NPN transistor and the lower NPN transistor
Even if directly connected to a transistor, both upper and lower NPN
Type transistors are not turned on at the same time.
Push-pull type with N-type transistor protected from shoot-through current
Reliability as an output circuit can be ensured. Only
Also removed the Schottky barrier diode
Even if the power supply voltage is set lower, the
As with the sprue type output circuit, the original function is effectively demonstrated.
Can be made. For example, 5
Function equivalent to push-pull type output circuit using V-system power supply
As a push-pull type output circuit of 3V system power supply
It has the effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a push-pull output circuit in which NPN transistors are vertically connected as output stages according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a push-pull output circuit according to another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a push-pull output circuit in which NPN transistors are vertically connected as output stages according to a conventional example.

FIG. 4 shows a conventional example in which a drive transistor is ON.
FIG. 9 is a circuit state diagram showing the potential of each unit in the case of performing the operation.

FIG. 5 is a circuit state diagram showing a potential of each part when a Schottky barrier diode is removed and a drive transistor is turned on in a conventional example.

[Explanation of symbols]

11 Input terminal 12 Output terminal E Power line Vcc Power supply voltage V _IN Input voltage V _OUT Output voltage Q10 Upper NPN transistor Q20 Lower NPN transistor Q31 Upper Driving transistor Q32: Lower driving transistor Q41: Upper control transistor Q42: Lower control transistor

Claims (1)

(57) [Claims] 1. An upper stage transformer as a push-pull output stage.
Both the transistor and the lower transistor are of the NPN type.
Used, emitter of upper NPN transistor and lower NP
Connect directly to the collector of the N-type transistor,
Connect the connection point to the output terminal and connect the upper stage NPN transistor
Connect the collector to the power line and connect the lower NPN transistor
That the emitter of the star is grounded to the ground level
, An upper drive to drive the upper NPN transistor
Drive transistor and lower NPN transistor
Separate lower drive transistors from each other
And the upper drive transistor has its emitter
Ground to the ground level directly, and
The transistor has its emitter connected to the lower NPN transistor.
Ground to ground level via base voltage adjustment resistor
A push-pull output circuit.