JP3173017B2 - Adaptive filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive filter used for identifying an unknown system. Such an adaptive filter leaks to an echo canceller for removing an echo generated in a 2-wire / 4-wire conversion unit, an equalizer for removing intersymbol interference received on a transmission path, and a microphone for acoustic input. It is applied to a noise canceller for removing noise to be included, a howling canceller for removing howling caused by acoustic coupling from a speaker to a microphone, and the like.

[0002]

2. Description of the Related Art Usually, identification of an unknown system using an adaptive filter is performed by inputting the same signal to the unknown system to be identified and the adaptive filter, and subtracting the output of the adaptive filter from the output of the unknown system. (Hereinafter, referred to as an error signal) by updating the coefficients of the adaptive filter.
Applications of identification of unknown systems using such adaptive filters include echo cancellers, equalizers, and noise filters.
Cancellers, howling cancellers, and the like are known. (Adaptive signal processing, (Ad
active Signal Processin
g), Prentice-Hall (Prentice-H)
all), 1985; hereinafter, "Document 1") Since the basic operation of the adaptive filter in these applications is almost the same, here, the prior art will be described using an echo canceller as an example. The echo canceller uses an adaptive (adaptive) filter having a transfer function that approximates the impulse response of the echo, and responds to the echo leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire / 4-wire conversion circuit. By generating a pseudo echo (echo replica), an operation is performed so as to suppress an echo that enters a receiving circuit and interferes with a received signal. That is, the path from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire / 4-wire conversion circuit is an adaptive canceller in the echo canceller.
This corresponds to an unknown system to be identified by a filter. At this time, each tap coefficient of the adaptive filter is sequentially corrected by correlating a difference signal obtained by subtracting an echo replica from a mixed signal in which an echo and a received signal are mixed, and a transmission signal. As a typical example of such adaptive filter coefficient correction, that is, a convergence algorithm of an echo canceller, an LMS algorithm (LMS algorithm) is used.
ALGORITHM) "Reference 2" and the Learning Identification Method (LEARNING)
IDENTIFICATIONMETHOD; LIM)
(IEEE Transactions on Automatic Control (IEEE TRANSA)
CTIONS ONAUTOMATIC CONTROL
L) Vol. 12, No. 3, 1967, pp. 282-287; hereinafter, "Document 3") is known.

FIG. 6 is a block diagram showing an example of the configuration of a conventional echo canceller. After being subtracted echo replica <br/> Rica e _k in the echo e _k subtractor 3 a transmission signal supplied to the input terminal 1 is generated leaks to the receiver side a 2-wire / 4-wire conversion circuit 2 , Output terminal 4. On the other hand, the transmission signal supplied to the input terminal 1 is an adaptive
Also supplied to the first tap circuit 60 ₁ of the filter. First
The first output of the tap circuit 60 ₁ is transmitted to the second tap circuit 60 ₂ adjacent. A second output of the first tap circuit 60 ₁ is supplied to the adder 61. Second tap circuit 60 ₂
The the first third tap circuit the output of 60 ₃ generated from the signal received from the first tap circuit 60 _1, transmits the second output to the adder 61. Similarly, the i-th tap circuit 60 _i sends the first output generated from the signal received from the (i−1) -th tap circuit 60 _i-1 to the (i + 1) -th tap circuit 60 _{i + 1} .
The second output is transmitted to the adder 61. Where i is 2 ≦ i
N is an integer satisfying ≦ N−1, where N represents the number of taps of the adaptive filter. The first tap circuit 60 ₁ is an input terminal 1
A first output generated from the signal received from the second tap circuit 60 _2, it transmits a second output to the adder 61. Nth
Tap circuit 60 _N transmits the second output generated from the signal received from the (N-1) th tap circuit 60 _N-1 to the adder 61. The adder 61 includes an i-th tap circuit 60 _i (1 ≦ i ≦
N), add all the second outputs supplied from
Supplies as a replica e _k to the subtractor 3.

The difference signal and the constant μ ₁ output from the subtracter 3 are supplied to the i-th tap circuit 60 _i . Where μ
₁ is called the step size and is deeply involved in coefficient updating. FIG. 7 shows a block diagram of the i-th tap circuit 60 _i (1 ≦ i ≦ N). However, when i = 1, no delay element 70 is provided. When i = N, the output 74 is not used. The input signal 73 is input terminal 1 or the (i-1) th tap circuit 6
0 _i−1 , the output signal 74 is the (i +
1) A signal transmitted to the tap circuit, an input signal 75 is a difference signal output from the subtractor 3, an output signal 76 is a signal supplied to the adder 61, and an input signal 77 is a step size μ _1.
It is. The input signal 73 is supplied to the delay element 70 and is delayed by one sample period.
+1) Coefficient generation circuit 7 while being supplied to the tap circuit
1 and to the multiplier 72. Input signal 77 is also supplied as an input signal 75 and the step size mu ₁ is the difference signal to the coefficient generation circuit 71. Coefficient generating circuit 71
Calculates the coefficient value generated by using these input signals as a multiplier 7
Feed to 2. Multiplier 72 multiplies the signal from coefficient generation circuit 71 by the signal from delay element 70, and outputs the result as output signal 76.

FIG. 8 is a block diagram of the coefficient generation circuit 71 assuming the LMS algorithm. The input signal 84 is the output signal of the delay element 70 in FIG. 7, the input signal 75 is the difference signal,
The input signal 77 is a step size μ ₁ and the output signal 85 is a coefficient value. The input signal 84 and the input signal 75 are output from the multiplier 8
Multiplied by 0, the correlation between the transmission signal of the echo canceller and the difference signal is obtained. The output of the multiplier 80 is multiplied by a step size μ ₁ in the multiplier 81 and supplied to the adder 82.
The adder 82 adds the output of the multiplier 81 and the output of the delayed delay element 83 and supplies the result to the delay element 83. The output of the delay element 83, which is a coefficient value, is output as an output signal 85 every clock.

It is assumed that a transmission signal is x _k (k is an index indicating time), an echo is e _k , and an additional noise received by e _k is δ _k . _Considering that the echo canceller generally performs an adaptive operation only during single talk when there is no received signal and only the echo e _k exists, the signal u _k supplied to the subtractor 3 is composed of an echo and additional noise. It is represented by u _k = e _k + δ _k (1) The purpose of the echo canceller is to generate a replica e _k of the echo e _k in equation (1) and use it to cancel the echo. Difference signal d which is the output signal of subtracter 3
_k is generally [delta] _k is e _k - when compared to the e _k considering that sufficiently small, is expressed by the following equation. _{d k = e k - e k} ... (2) In the formula (2), - called (e _k e _k) is the residual echo. In the LMS algorithm, the m-th _{cm, k} of the adaptive filter is updated according to the following equation. _{c m, k = c m,} k-1 + μ 1 · d k · x km-1 ... (3) Expressed Equation (3) for all N coefficients in matrix _{form, c k = c k-1} + μ ₁ · d _k · x _k−1 (4) Here, the vector c _k and the vector x _k are respectively given by the following equations. _{c k = [c 0, k} c 1, k ...... c N-1, k] T ... (5) x k = [x k x k-1 ...... x k-N + 1] T ... (6) on the other hand. In the LIM, the coefficient is updated according to equation (7) instead of equation (4). _{c k = c k-1 +} (α / Nσ x 2) · d k · x k-1 ... (7) α is the step size for LIM, sigma _x ² is an average power input to the adaptive filter is there. σ _x
² is used to make the value of the step size α inversely proportional to the average power so as to perform stable convergence. σ _x ²
There are several methods for obtaining the value, but for example, the value can be obtained by Expression (8).

[0007]

(Equation 1)

The step size in equations (4) and (7) defines the speed of convergence of the adaptive filter and the residual echo level after convergence. In the case of LMS,
convergence as mu ₁ is large becomes faster, the residual echo level increases. Conversely, in order to achieve a sufficiently low residual echo level, it is necessary to employ a commensurately small μ ₁ , which causes a reduction in the convergence speed. The same applies to the step size α of the LIM.

In the identification of an unknown system, a case where a long flat delay is included at the head of the impulse response of the unknown system to be identified is frequently seen particularly in an echo canceller for a satellite link. Even for an impulse response including such a long flat delay, it is necessary for the conventional echo canceller to have a sufficient number of taps to have a tap number corresponding to the impulse response length. Actually, since the tap coefficients of the flat delay unit become zero, it is useless to use these coefficients for calculating the filter output. A method for solving this problem and efficiently performing system identification even for an impulse response including a long flat delay is described in “Transactions of the Institute of Electronics, Communication and Communication Engineers, 1984, No. 595” (hereinafter, “No. 595”). Reference 4 "). This method reduces the amount of calculation by using only coefficients at positions corresponding to the substantial response in the filter output calculation for an impulse response consisting of a flat delay and a substantial waveform response. Hereinafter, the method described in Reference 4 will be briefly described.

FIG. 9 is a block diagram showing the echo canceller described in Reference 4. 9 is different from the echo canceller shown in FIG.
0 _1, 90 _2, ..., after passing through a control circuit 92 exits the 90 _N, each tap circuits 90 _1, 90 _2, ..., 90 closed circuit points and respective tap circuits 60 ₁ has a back to _N, 60 _2, …,
, _90N and each tap circuit 90 ₁ , 90 ₂ ,..., 90 _N. The control circuit 92 includes the tap circuits 90 ₁ , 90
_2, ..., 90 by using the coefficient values obtained from _N, the operation on which coefficients to determine whether to stop, each tap circuits 90 ₁ that information as a control signal, 90 _2, ..., and supplies the 90 _N. Each of the tap circuits 90 ₁ , 90 ₂ ,..., 90 _N stops the operation on the unnecessary coefficient by the signal supplied from the control circuit 92.

[0011] FIG. 10 shows a block diagram of a tap circuit 90 _i. The difference from the tap circuit 60 _i shown in FIG. 7 is that the input signal 75 is supplied to the coefficient generation circuit 71 via the selector 101.
And the coefficient generated by the coefficient generation circuit 71 is supplied to the multiplier 72 via the selector 102. The selector 102 selects the output of the coefficient generation circuit 71 or zero and supplies it to the multiplier 72. Selector 1
01 is an input signal 75 or zero to select the coefficient generation circuit 71
To supply. The selectors 101 and 102 are both connected to the control circuit 9
Zero is selected from 2 by the control signal 105 supplied to each tap coefficient. Therefore, when the selector 101 selects zero, the signal supplied to the coefficient generation circuit 71 becomes zero, and when the selector 102 selects zero, the multiplicand in the multiplier 72 becomes zero, and the coefficient update amount and the corresponding tap circuit output become zero. Becomes When the control signal 105 is 0, the selectors 101 and 102 select and output zero. Next, the control circuit 92 will be described.

FIG. 11 is a block diagram of the control circuit 92. The control circuit 92 is supplied with values of tap coefficients and tap numbers from N taps of the adaptive filter.
The control circuit 92 detects the minimum value of the tap coefficient value corresponding to the tap number corresponding to the tap number stored in the control circuit, and stores the minimum value in the control circuit instead of the tap number corresponding to the minimum value. A new set of tap numbers is constructed by replacing the value at the head of the queue that has been set as a new tap number, and the N of the adaptive filter is set.
Feed to tap. The input signal 115 to the control circuit 92 is output from each tap circuit 90 ₁ , 90 ₂ ,..., 90 _N and supplied to the control circuit 92, and the output signal 116 is output from the control circuit 92 to each tap circuit 90 ₁ , 90 _2. , ..., a control signal supplied to the 90 _N. Therefore, although shown by one line in the figure, the input signal 115 and the output signal 116
Is an N multiplex signal. The input signal 115 is first supplied to an absolute value circuit 111 to be converted into an absolute value.
2 is transmitted. The minimum value detection circuit 112 detects the minimum of these absolute value signal components, and transmits the corresponding tap number to a first-in first-out circuit (FIFO) 113 and a storage device 114. When a signal is supplied from the minimum value detection circuit 112, the FIFO 113 transmits the earliest input one sample among the sample values stored at that time to the storage device 114. The storage device 114 stores 0 or 1 corresponding to each of the N tap numbers to be subjected to the filtering operation. When a signal is transmitted from the FIFO 113, the value corresponding to the tap number is changed from 0 to 1. change. On the other hand, the value corresponding to the tap number supplied from the minimum value detection circuit 112 to the storage device 114 is changed from 1 to 0. Therefore, 0 in storage device 114
The total number M of 1 is constant, and the total number M of 1 is the number of effective taps to which a coefficient is allocated, and the number NM of 0 is the number of taps to which no coefficient is allocated. The signal composed of the sequence of 0s and 1s obtained by the above operation is output from the storage device 114 to the output signal 116.
After that, each tap circuit 90 ₁ , 90 ₂ ,
..., value of Me i-th output signal 116 which is supplied to the 90 _N (0 or 1) is a control signal for the tap circuit 90 _i.
The tap circuit 90 _i controls the selectors 101 and 102 using the i-th numerical value of the output signal 116 as the control signal 105 in FIG.

[0013]

As described with reference to FIG. 10, in the method described in Reference 4, the control signal 10
When 0 is supplied as 5, zero is output as the output of the selector 102. Therefore, the coefficient generation circuit 71 is not substantially used and is wasted. Further, the number of 1s equal to the number of effective taps is arranged at equal intervals as the initial value of the storage device 114 in FIG. Arrange them in order. When such an initial value is used, when the impulse response having a long flat delay is approximated, the tap number corresponding to the waveform response unit is set to the FIFO 113.
It takes a long time to move to a position close to the output in, and to be supplied to the storage device 114 and assigned a tap. Therefore, there is a problem that the convergence time becomes long.

An object of the present invention is to provide an adaptive filter having a small hardware scale and a short convergence time.

[0015]

According to the present invention, an input signal is set to one.
A delay element array consisting of a cascade connection of a plurality of delay elements for sample period delay, and a plurality of coefficient circuits for multiplying the output and coefficient of some of the delay elements constituting the delay line,
Receiving the output of the delay elements constituting the delay element row,
And Matrigel <br/> box switch to transmit selectively to certain coefficient circuit part of the output, an adder summing the output of said plurality of coefficient circuits receives an output of said plurality of coefficient circuits, wherein at least and a control circuit for generating control signals for the matrix switch, the coefficient circuit the Matrigel
A delay element output which is supplied from the box switches, or external
Et supplied error signal and the coefficient update scan supplied from the outside
A coefficient circuit that generates successive coefficients using the step size,
The output of the coefficient circuit is supplied from the matrix switch.
A multiplier for multiplying the output of the delay element obtained by the
Is output .

Further, the present invention provides an absolute value circuit in which a control circuit receives a coefficient value of an output of a coefficient generating circuit and converts the coefficient value into an absolute value, and a minimum value detecting circuit for detecting a minimum value among the outputs of the absolute value circuit. A maximum value detection circuit for detecting a maximum one of the absolute value circuit outputs; a first delay element for delaying an output of the maximum value detection circuit; an output of the first delay element; A first coincidence detection circuit for detecting coincidence with an output of the value detection circuit, a counter for counting the output of the first coincidence detection circuit, a second delay element for delaying the counter output, A second coincidence detection circuit for judging the coincidence between the output of the delay element and the counter output, and a first-in first-out circuit that receives the output of the minimum value detection circuit, stores the output in the deepest portion of the stack, and outputs the value of the shallowest portion And the output of the first-in first-out circuit Receiving the output of the maximum value detection circuit, determining whether a difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is equal to or less than a predetermined threshold, and is equal to or greater than the threshold. A determination circuit that feeds back the output of the first-in first-out circuit to the first-in first-out circuit; receives the output of the determination circuit and the output of the minimum value detection circuit, and sequentially rewrites the stored contents to output the second match detection circuit. A storage device that rewrites all the stored contents using the output of the maximum value detection circuit in response to the output of the storage device.
And a selector for selecting and outputting the output of the delay element according to the output of the counter, and supplying the selector output to the third delay element and simultaneously outputting the control signal as a control signal. .

[0017]

With the adaptive filter of the present invention, the hardware scale can be reduced by sequentially switching a limited number of tap coefficients and assigning them to different taps. Further, in the adaptive filter of the present invention, when a limited number of taps are assigned to the substantial waveform response part of the impulse response, first, a rough position of the waveform response part is estimated, and taps are provided near the estimated position. After concentrating, the convergence time can be reduced by performing tap position replacement limited to the vicinity of the estimated waveform response section.

Furthermore, in the adaptive filter of the present invention, a stable position estimation is performed using a small step size in estimating the position of the waveform response section, and a large step is performed in the tap position replacement limited to the vicinity of the estimated waveform response section. High-speed convergence can be performed using the size, and the convergence time can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the functional blocks to which the same reference numerals as in FIG. 9 are assigned have the same functions as in FIG. The difference between FIG. 1 and FIG. 9 is that the tap circuits 90 ₁ , 90
_2, ..., 90 _N delay element array 10 _1, 10 _2, ..., 10
_N , matrix switch 12, and coefficient circuits 11 ₁ , 1
1 _2, ..., there is the point that has been replaced by a 11 _M. Along with this, the control circuit 14 controls the matrix switch 12 with its output.

In FIG. 1, the input signal supplied to the delay element 10 ₁ is supplied to the delay elements 10 ₂ ,.
0 _N are sequentially transmitted. The delay element arrays 10 ₁ , 10 ₂ ,
, 10 _N are connected to _M coefficient circuits 11 ₁ , 11 ₂ ,..., 11 _M via a matrix switch 12.
The matrix switch 12 includes the M delay element rows 10 _i selected by the output of the control circuit 14 and the M coefficient circuits 1
1 _j are sequentially and adaptively connected.

[0021] The configuration of the i-th coefficient circuits 11 _i shown in FIG. FIG. 2 is basically equivalent to the tap circuit of FIG. 7, with the only difference being that there is no delay element 70. The input signal 20 in FIG. 2 corresponds to the output signal of the delay element _10i in FIG. The other signals 55, 56, 57 are 75, 7 in FIG.
6, 77, which are the difference signal output from the subtracter 3, the signal supplied to the adder 61, and the step size, respectively. The coefficient generation circuit 51 and the multiplier 52 operate exactly the same as the coefficient generation circuit 71 and the multiplier 72 in FIG.

FIG. 3 shows a specific example of the control circuit 14. The input signal 300 in FIG. 3 is composed of M coefficient circuits 11 ₁ , 11 ₂ ,
.., 11 _M , and the output signal 302 are control signals for the matrix switch 12. Input signal 30
The coefficient value supplied as 0 is converted to an absolute value by the absolute value circuit 31 and transmitted to the maximum value detection circuit 32 and the minimum value detection circuit 33. The maximum value detection circuit 32 detects the maximum input signal and inputs the corresponding tap number to the delay element 34.
Is supplied to the coincidence detection circuit 36, the determination circuit 37 and the storage device 39. The delay element 34 transmits the input signal to the coincidence detection circuit 36 after delaying it by one sample period. The coincidence detection circuit 36 checks the coincidence between the signal supplied directly from the maximum value detection circuit 32 and the signal supplied via the delay element 34. This is the tap number corresponding to the current maximum coefficient and 1
This is equivalent to checking whether the tap numbers corresponding to the maximum coefficient before the sample period match. The match detection circuit 36 outputs 1 when the two inputs match, and outputs 0 when they do not match. The counter 38 uses the 1 or 0 as the match detection circuit 36
And count 1. When ones continue, the counter 38 continues counting up, and when the ones reaches a predetermined value, the output is changed from 0 to 1. When 0 is detected, the counter is reset.

This output signal is supplied to a delay element 45, a coincidence detection circuit 46, and a selector 47.
7 is the output of the delay element 48 when this output signal is 1 ,
When 0 , the output of the storage device 39 is selected and the output signal 302
Output as The output signal 302 is fed back to the selector 47 after being delayed by one sample period via the delay element 48. Therefore, when the output of the counter 38 is 0, the control signal 302 indicating which tap is to be assigned a coefficient is a value one sample period before, and the coefficient assigned tap is not changed. Coefficient allocation taps will change with the supplied values. The coincidence detection circuit 46
The coincidence between a signal obtained by delaying the output of the counter 38 by one sample period by the delay element 45 and the output of the counter 38 is checked. If they match, 1 is stored, otherwise 0 is stored.
9

The minimum value detection circuit 33 detects the minimum input signal, and assigns a corresponding tap number to the FIFO 35
Is supplied to the storage device 39. When the signal is supplied from the minimum value detection circuit 33, the FIFO 35 transmits the earliest input one sample among the sample values stored at that time to the determination circuit 37. In the judgment circuit 37, F
The difference between the signal supplied from the IFO 35 and the signal supplied from the maximum value detection circuit 32 is obtained, and its absolute value is compared with a predetermined threshold value. When the absolute value is larger than the threshold value, the signal supplied from the FIFO 35 is fed back to the FIFO 35 as it is. If it is smaller than the threshold value, it is transmitted to the storage device 39. The storage device 39 stores 0 or 1 corresponding to each of the N tap numbers to be subjected to the filtering operation. When a signal is transmitted from the determination circuit 37, the value corresponding to the tap number is set to 0.
From 1 to 1. On the other hand, the value corresponding to the tap number supplied from the minimum value detection circuit 33 to the storage device 39 is changed from 1 to 0. Therefore, the total number of 0s and 1s in the storage device 39 is constant. Further, when the signal supplied from the coincidence detection circuit 46 to the storage device 39 is 0 , the storage device 39 arranges M− 1 ones before and after the tap number supplied from the maximum value detection circuit 32. As an example of the arrangement method of 1, the tap numbers can be equally distributed before and after the tap number as a center, and can be arranged so that 1 is continuous. With this operation, the effective taps are concentratedly arranged near the estimated waveform response unit. 0 and 1 obtained by the above operation
Are transmitted from the storage device 39 to the selector 47. As described above, the selector 47 switches one of the signal supplied from the storage device 39 and the signal supplied from the delay element 47 by controlling the output from the counter 38.

As is clear from the above description, when the output of the counter 38 in FIG.
The assigned tap numbers of 1 ₁ , 1 _{1 2} ,..., 11 _M are unchanged and maintain the state of the initial assignment. By monitoring the growth of the amplitude of the tap coefficient value, a substantial waveform response part can be estimated. When the output of the counter 38 is 1
, It means that the substantial waveform response part has been estimated, and the tap numbers assigned to the _M coefficient circuits 11 ₁ , 11 ₂ ,..., 11 _M are concentrated near the estimated waveform response part. , The coefficient is more finely allocated.

FIG. 4 is a block diagram showing another embodiment of the present invention. 4 is a coefficient circuit 11 ₁ , 11 ₂ ,..., 11 _M
Step size mu ₁ supplied differs from that of Figure 1 in that it is replaced with step size mu ₁ and mu ₂ and a selector 41 in. Accordingly, the control circuit 14 controls the control circuit 1
5 has been replaced. In the embodiment shown in FIG. 4, the selector 41 selects the step sizes μ ₁ and μ ₂ according to the control signal from the control circuit 15 and
1 _1, 11 _2, ..., and supplies to 11 _M. FIG. 5 is a block diagram of the control circuit 15 shown in FIG. FIG. 5 and FIG.
The difference is that the output of the counter 38 is output as the control signal 501. The selector 47, a mu ₁ when the control signal 501 is 1, which is supplied from the control circuit 15, when the 0 mu ₂
Select When the control signal 501 is 1 , the coefficient is stably grown to estimate a correct waveform response portion, and the control signal 50
After 1 becomes 0 , the coefficient is usually set to μ ₁ ≦ μ ₂ in order to quickly converge the coefficient to the optimum value.

Although the LMS algorithm has been assumed so far, the only configuration unique to the LMS is the coefficient generation circuit shown in FIG. Therefore, the present invention can be applied to other algorithms including LIM. Further, the application of the present invention has been described by taking the echo canceller as an example, but the present invention can be applied to any system having an impulse response that can be expressed by a combination of flat delay and waveform response.

[0028]

As described in detail above, according to the present invention, the hardware scale can be reduced by sequentially switching a limited number of tap coefficients and assigning them to different taps. Further, the adaptive filter of the present invention, when allocating a limited number of taps to the substantial waveform response part of the impulse response, first estimates a rough position of the waveform response part, and sets the approximate position to the vicinity of the estimated position. After the taps are concentrated, the convergence time can be reduced by exchanging tap positions limited to the vicinity of the estimated waveform response section.

Further, the adaptive filter of the present invention performs stable position estimation using a small step size in estimating the position of the waveform response portion, and performs a large step in the tap position replacement limited to the vicinity of the estimated waveform response portion. High-speed convergence can be performed using the size, and the convergence time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing details of a tap circuit of FIG. 1;

FIG. 3 is a block diagram showing a specific example of a control circuit of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a specific example of the control circuit of FIG. 4;

FIG. 6 is a block diagram showing an example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 7 is a block diagram showing details of a tap circuit in FIG. 6;

FIG. 8 is a block diagram showing details of a coefficient generation circuit in FIG. 7;

FIG. 9 is a block diagram showing another example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 10 is a block diagram showing details of a tap circuit in FIG. 9;

FIG. 11 is a block diagram showing details of a control circuit in FIG. 10;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 input terminal 2 2-wire to 4-wire conversion circuit 3 subtractor 4 output terminal 10 _i (1 ≦ i ≦ N) delay element 11 _i (1 ≦ i ≦ M) tap circuit 12 matrix switch 14, 15 control circuit 41 selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-119930 (JP, A) JP-A-1-188037 (JP, A) JP-A-63-73724 (JP, A) 500075 (JP, A) Proceedings of the National Meeting of the Institute of Electronics, Communications and Communication Engineers, 1984 Volume 2 (Showa 59-10) p. 2-240 “A Method of Echo Canceller with Adaptive Control of Tap Position and Coefficient Value” Shinichi Kawamura, Mitsutoshi Hatori Proc. −10 “A construction method of howling canceller that adaptively controls tap position and value” Mitsutoshi Hatori, Motoaki Koyama (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 21/00 H03H 17/06 635 H03H 17/06 655 H04B 3/23 JICST file (JOIS) Practical file (PATOLIS) Patent file (PATOLIS)

Claims (3)

(57) [Claims] 1. A delay element array consisting of a cascade of a plurality of delay elements for delaying an input signal by one sample period, and a plurality of delay elements for multiplying the output of some of the delay elements constituting the delay element array by a coefficient. A coefficient circuit; a matrix switch that receives the outputs of the delay elements forming the delay element array and selectively transmits a part of the outputs to a specific coefficient circuit; and an addition that sums the outputs of the plurality of coefficient circuits. And a control circuit that receives outputs of the plurality of coefficient circuits and generates a control signal for the matrix switch , wherein the coefficient circuit is supplied from the matrix switch.
Delay element output, externally supplied error signal and external
Coefficient using the coefficient update step size supplied by
And a coefficient generating circuit for generating
Multiply with delay element output supplied from matrix switch
The control circuit receives the coefficient value of the output of the coefficient generation circuit.
An absolute value circuit for converting the absolute value
A minimum value detection circuit for detecting the minimum value,
Maximum value detection circuit that detects the largest value circuit output
And a first delay for delaying the output of the maximum value detection circuit
Element, output of the first delay element, and the maximum value detection circuit
A first match detection circuit for detecting a match with the output of
A counter for counting the output of the match detection circuit
A second delay element for delaying the output of the
A second method for determining whether the output of the element matches the output of the counter
A match detection circuit and a switch for receiving an output of the minimum value detection circuit.
Output at the same time as storing at the deepest part of the tack
A first-in first-out circuit and an output of the first-in first-out circuit
Receiving the output of the maximum value detection circuit,
Is different from the output of the maximum value detection circuit in advance.
Is determined to be below the threshold
If above, the output of the first-in first-out circuit is
A decision circuit that feeds back to the first-in first-out circuit;
The stored contents are sequentially received in response to the
Rewriting, in response to the output of the second match detection circuit,
Rewrite all stored contents using the output of the large value detection circuit
Storage device, output of the storage device and output of third delay element
Select according to the output of the counter and output
And the third delay element
An adaptive filter for outputting the control signal as well as supplying the control signal to the filter. " 2. A has a fourth selector for switching the step size and second step size, adaptive filter according to claim 1, wherein the controller controls the fourth selector at the counter output . 3. The adaptive filter according to claim 1 , wherein the counter counts the continuity of the output of the coincidence circuit, and resets when the continuity does not occur.