JP2569979B2 - Method and apparatus for estimating system characteristics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for estimating a system characteristic for identifying an unknown system using an adaptive filter. Such an adaptive filter has two
An echo canceller for removing echo generated in the line / 4-wire converter, an equalizer for removing intersymbol interference received on a transmission line, and a noise canceller for removing noise leaking into a microphone for acoustic input. It is applied to a canceller, a howling canceller for removing howling caused by acoustic coupling from a speaker to a microphone, and the like.

[0002]

2. Description of the Related Art Usually, identification of an unknown system using an adaptive filter is performed by inputting the same signal to the unknown system to be identified and the adaptive filter, and subtracting the output of the adaptive filter from the output of the unknown system. (Hereinafter, referred to as an error signal) by updating the coefficients of the adaptive filter.
Applications of identification of unknown systems using such adaptive filters include echo cancellers, equalizers, and noise filters.
Cancellers, howling cancellers, and the like are known. (Adaptive signal processing, (Ad
active Signal Processin
g), Prentice-Hall (Prentice-H)
all), 1985; hereinafter, "Document 1") Since the basic operation of the adaptive filter in these applications is almost the same, here, the prior art will be described using an echo canceller as an example. The echo canceller uses an adaptive (adaptive) filter having a transfer function that approximates the impulse response of the echo, and responds to the echo leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire / 4-wire conversion circuit. By generating a pseudo echo (echo replica), an operation is performed so as to suppress an echo that enters a receiving circuit and interferes with a received signal. That is, the path from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire / 4-wire conversion circuit is an adaptive canceller in the echo canceller.
This corresponds to an unknown system to be identified by a filter. At this time, each tap coefficient of the adaptive filter is sequentially corrected by correlating a difference signal obtained by subtracting an echo replica from a mixed signal in which an echo and a received signal are mixed, and a transmission signal. As a typical example of such adaptive filter coefficient correction, that is, a convergence algorithm of an echo canceller, an LMS algorithm (LMS algorithm) is used.
ALGORITHM) "Reference 2" and the Learning Identification Method (LEARNING)
IDENTIFICATIONMETHOD; LIM)
(IEEE Transactions on Automatic Control (IEEE TRANSA)
CTIONS ONAUTOMATIC CONTROL
L) Vol. 12, No. 3, 1967, pp. 282-287; hereinafter, "Document 3") is known.

FIG. 7 is a block diagram showing a configuration example of a conventional echo canceller. After being subtracted echo replica <br/> Rica e _k in the echo e _k subtractor 3 a transmission signal supplied to the input terminal 1 is generated leaks to the receiver side a 2-wire / 4-wire conversion circuit 2 , Output terminal 4. On the other hand, the transmission signal supplied to the input terminal 1 is an adaptive
Also supplied to the first tap circuit 70 ₁ of the filter. First
The first output of the tap circuits 70 ₁ is transmitted to the second tap circuit 70 ₂ adjacent. A second output of the first tap circuit 70 ₁ is supplied to the adder 12. Second tap circuit 70 ₂
The to the first output of the third tap circuit 70 ₃ generated from the signal received from the first tap circuit 70 _1, it transmits the second output to the adder 12. Here, i is an integer satisfying 2 ≦ i ≦ N−1, and N represents the number of taps of the adaptive filter. The first tap circuit 70 ₁ a first output generated from received from the input terminal 1 signal to the second tap circuit 70 _2, transmits a second output to the adder 12. Nth tap circuit 70
_N transmits the second output generated from the signal received from the (N−1) th tap circuit 70 _N−1 to the adder 12. The adder 12 adds all the second output which is supplied from the i tap circuit _{70 i (1 ≦ i ≦ N} ), supplied to the subtractor 3 as an echo replica e _k.

[0006] The difference signal and the constant μ ₁ output from the subtracter 3 are supplied to the i-th tap circuit 70 _i . Where μ
₁ is called the step size and is deeply involved in coefficient updating. FIG. 8 shows a block diagram of the i-th tap circuit 70 _i (1 ≦ i ≦ N). However, when i = 1, no delay element 81 is provided. When i = N, the output 804 is not used.
The input signal 800 is a signal transmitted from the input terminal 1 or the (i−1) th tap circuit 70 _i−1 , and the output signal 804 is a signal transmitted to the (i + 1) th tap circuit, the input signal 80
1 the difference signal output from subtractor 3, the signal output signal 803 is supplied to the adder 12, the input signal 802 is a step size mu _1. The input signal 800 is supplied to the delay element 81 and is delayed by one sample period.
4 and is supplied to the (i + 1) th tap circuit, and at the same time, is transmitted to the coefficient generation circuit 82 and the multiplier 83. Input signal 802 is also supplied as an input signal 801 and the step size mu ₁ is the difference signal to the coefficient generation circuit 82. The coefficient generation circuit 82 supplies a coefficient value generated using these input signals to the multiplier 83. Multiplier 83 multiplies the signal from coefficient generation circuit 82 by the signal from delay element 81, and outputs the result as output signal 803.

FIG. 9 shows a block diagram of the coefficient generating circuit 82 assuming the LMS algorithm. The input signal 95 is the output signal of the delay element 81 of FIG. 8, the input signal 95 is the difference signal,
The input signal 801 has a step size μ ₁ and the output signal 96
Is a coefficient value. The input signal 95 and the input signal 801 are multiplied by a multiplier 91, and the correlation between the transmission signal of the echo canceller and the difference signal is obtained. The output of the multiplier 91 is the multiplier 9
In step 2, the step size is multiplied by ₁ and supplied to the adder 93. The adder 93 adds the output of the multiplier 92 and the output of the feedback delay element 94 and supplies the result to the delay element 94. The output of the delay element 94, which is a coefficient value, is output as an output signal 96 every clock.

It is assumed that a transmission signal is x _k (k is an index indicating time), an echo is e _k , and an additional noise received by e _k is δ _k . _Considering that the echo canceller generally performs an adaptive operation only during single talk when there is no received signal and only the echo e _k exists, the signal u _k supplied to the subtractor 3 is composed of an echo and additional noise. It is represented by u _k = e _k + δ _k (1) The purpose of the echo canceller is to generate a replica e _k of the echo e _k in equation (1) and use it to cancel the echo. Difference signal d which is the output signal of subtracter 3
_k is generally [delta] _k is e _k - when compared to the e _k considering that sufficiently small, is expressed by the following equation. _{d k = e k - e k} ... (2) In the formula (2), - called (e _k e _k) is the residual echo. In the LMS algorithm, the m-th _{cm, k} of the adaptive filter is updated according to the following equation. _{c m, k = c m,} k-1 + μ 1 · d k · x km-1 ... (3) Expressed Equation (3) for all N coefficients in matrix _{form, c k = c k-1} + μ ₁ · d _k · x _k−1 (4) Here, the vector c _k and the vector x _k are respectively given by the following equations. _{c k = [c 0, k} c 1, k ...... c N-1, k] T ... (5) x k = [x k x k-1 ...... x k-N + 1] T ... (6) on the other hand. In the LIM, the coefficient is updated according to equation (7) instead of equation (4). _{c k = c k-1 +} (α / Nσ x 2) · d k · x k-1 ... (7) α is the step size for LIM, sigma _x ² is an average power input to the adaptive filter is there. σ _x
² is used to make the value of the step size α inversely proportional to the average power so as to perform stable convergence. σ _x ²
There are several methods for obtaining the value, but for example, the value can be obtained by Expression (8).

[0007]

(Equation 1)

The step size in equations (4) and (7) defines the speed of convergence of the adaptive filter and the residual echo level after convergence. In the case of LMS,
convergence as mu ₁ is large becomes faster, the residual echo level increases. Conversely, in order to achieve a sufficiently low residual echo level, it is necessary to employ a commensurately small μ ₁ , which causes a reduction in the convergence speed. The same applies to the step size α of the LIM.

In the identification of an unknown system, a case where a long flat delay is included at the head of the impulse response of the unknown system to be identified is frequently seen particularly in an echo canceller for a satellite link. Even for an impulse response including such a long flat delay, it is necessary for the conventional echo canceller to have a sufficient number of taps to have a tap number corresponding to the impulse response length. Actually, since the tap coefficients of the flat delay unit become zero, it is useless to use these coefficients for calculating the filter output. A method for solving this problem and efficiently performing system identification even for an impulse response including a long flat delay is described in “Transactions of the Institute of Electronics, Communication and Communication Engineers, 1984, No. 595” (hereinafter, “No. 595”). Reference 4 "). This method reduces the amount of calculation by using only coefficients at positions corresponding to the substantial response in the filter output calculation for an impulse response consisting of a flat delay and a substantial waveform response. Hereinafter, the method described in Reference 4 will be briefly described.

FIG. 10 is a block diagram showing an echo canceller described in Reference 4. The difference from the echo canceller shown in FIG. 7 is that FIG.
00 _1, 100 _2, ..., control circuit 10 out of the 100 _N
, Each tap circuit 100 ₁ , 100 ₂ ,.
00 points with a closed circuit back to _N and each tap circuit 7
_{0 1, 70 2, ...,} 70 N and the tap circuits 100 _1, 1
00 _2, ..., it is a configuration of 100 _N. Control circuit 101
Uses the coefficient values obtained from each of the tap circuits 100 ₁ , 100 ₂ ,..., 100 _N to determine which coefficient should be stopped for operation, and uses that information as a control signal to control each of the tap circuits 100 ₁ , 100 _2. , ..., 100 _N Each tap circuit 100 is controlled by a signal supplied from the control circuit 101.
₁ , 100 ₂ ,..., 100 _N stop the calculation for the unnecessary coefficient.

[0011] FIG. 11 shows a block diagram of a tap circuit 100 _i. The difference from the tap circuit 70 _i shown in FIG.
The input signal 801 is supplied to the coefficient generation circuit 82 via the selector 110 and the coefficient generated by the coefficient generation circuit 82 is supplied to the multiplier 83 via the selector 111. The selector 111 includes a coefficient generation circuit 82
Is selected and supplied to the multiplier 83. The selector 110 selects the input signal 801 or zero and supplies it to the coefficient generating circuit 82. The selectors 110 and 111 both control signals 11 supplied from the control circuit 101 to each tap coefficient.
5, zero is selected. Therefore, when the selector 110 selects zero, the signal supplied to the coefficient generation circuit 82 is determined.
The multiplicand at 3 becomes zero, and the coefficient update amount and the corresponding tap circuit output become zero. The selectors 110 and 111 select and output zero when the control signal 115 is zero. Next, the control circuit 101 will be described.

FIG. 12 is a block diagram of the control circuit 101. The control circuit 101 is supplied with values of tap coefficients and tap numbers from N taps of the adaptive filter. The control circuit 101 detects the minimum value of the tap coefficient value corresponding to the tap number corresponding to the tap number stored in the control circuit, and stores it in the control circuit instead of the tap number corresponding to the minimum value. A new set of tap numbers is formed by replacing the value at the head of the queue that has been set as a new tap number, and is supplied to the N taps of the adaptive filter. An input signal 125 to the control circuit 101 is output from each of the tap circuits 100 ₁ , 100 ₂ ,.
_The signal output from _N and supplied to the control circuit 101 and the output signal 126 are output from the control circuit 101 to the tap circuits 100 ₁ and 1
00 _2, ..., a control signal supplied to the 100 _N. Therefore, although indicated by one line in the figure, the input signal 125 and the output signal 126 are N-multiplexed signals. The input signal 125 is first supplied to the absolute value circuit 121, converted into an absolute value, and transmitted to the minimum value detecting circuit 122. The minimum value detection circuit 122 detects the minimum one of these absolute value signal components, and assigns the corresponding tap number to a first-in first-out circuit (F
IFO) 123 and the storage device 124. FIFO
When the signal is supplied from the minimum value detection circuit 122, the 123 transmits the earliest input sample among the stored sample values to the storage device 124. The storage device 124 stores 0 or 1 corresponding to each of the N tap numbers to be subjected to the filtering operation. When a signal is transmitted from the FIFO 123, the value corresponding to the tap number is changed from 0 to 1. change. on the other hand,
The value corresponding to the tap number supplied from the minimum value detection circuit 122 to the storage device 124 is changed from 1 to 0. Accordingly, the total number of 0s and 1s in the storage device 124 is constant, and the total number M of 1s is the number of effective taps to which a coefficient is assigned, and the number NM of 0s is the number of taps to which no coefficient is assigned. After being output as 0 and 1 of signal consists of a sequence output signal 126 from the storage device 124 obtained in the above operation, the tap circuits 100 _1, 100 _2, ..., an output signal supplied to the 100 _N 126 value of i-th (0 or 1) is a control signal of tap circuit 100 _i. Tap circuit 100 _i
Represents the i-th numerical value of the output signal 126 as the control signal 1 in FIG.
As 15, the selectors 110 and 111 are controlled.

[0013]

As described with reference to FIG. 11, in the method described in Reference 4, the control signal 11
When 0 is supplied as 5, zero is output as the output of the selector 111. Therefore, the coefficient generation circuit 82 is not substantially used and is wasted. Further, the number of 1s equal to the number of effective taps is arranged at equal intervals as the initial value of the storage device 124 in FIG. 12, and the tap numbers to which 0 is assigned in the FIFO device 123, that is, the storage device 124 as the initial value of the queue, from the smaller number. Arrange them in order. When such an initial value is used, when an impulse response having a long flat delay is approximated, the tap number corresponding to the waveform response unit is FIFO123.
It takes a long time to move to a position close to the output in, and to be supplied to the storage device 124 and assigned a tap. Therefore, there is a problem that the convergence time becomes long.

An object of the present invention is to provide a method and apparatus for estimating system characteristics using an adaptive filter having a small hardware scale and a short convergence time.

[0015]

A system characteristic estimating method according to the present invention performs multiplication by adaptively combining a plurality of input signal samples delayed by one sample period with a plurality of adaptively changing multiplicands, When an address of a multiplicand that is not used for the multiplication is stored in a queue and a system characteristic is estimated by an adaptive filter that outputs the sum of the multiplication results, the multiplication is updated using an estimation error and used for the multiplication. Using the value of the multiplicand obtained, the multiplicand and the replacement of the multiplicand corresponding to the value in the queue are repeatedly performed until a predetermined number of times is reached, and the number of repetitions is adaptively controlled. I do.

Further, the system characteristic estimating apparatus of the present invention
When estimating system characteristics using an adaptive filter, a delay element array including a cascade connection of a plurality of delay elements for delaying an input signal by one sample period, an output of each delay element constituting the delay element array, and A plurality of multiplication circuits for multiplying by a coefficient corresponding to the delay element; a matrix switch for determining a connection relationship between the plurality of delay elements and the plurality of multiplication circuits; and a summation of outputs of the plurality of multiplication circuits. An adder; and a control circuit that receives an estimation error that is a difference between outputs of the plurality of multiplication circuits, the adaptive filter output, and the system output, and generates a control signal for the matrix switch. A circuit for generating a coefficient by receiving the characteristic estimation error, the output of each of the delay elements, and a constant used for updating the coefficient; And a multiplier for multiplying the output of each of the delay elements by the output of the delay element and outputting the result. The control circuit comprises: an absolute value circuit that receives the output of the coefficient generation circuit and converts the output to an absolute value; A minimum value detection circuit that detects the smallest one of the outputs and feeds back the output to itself, and receives the output of the minimum value detection circuit and stores it in the deepest part of the stack, and at the same time outputs the value of the shallowest part on a first-in first-out basis Circuit, a selector for selecting and outputting the output of the first-in first-out circuit and the output of the delay element according to the output of the timing circuit controlled by the estimation error, and a storage device for sequentially rewriting the storage contents in response to the output of the selector. Wherein the matrix switch is controlled by the output of the storage device at the same time as the selector output is fed back to the delay element.

Further, the system characteristic estimating apparatus of the present invention
An absolute value circuit that receives the output of the coefficient generation circuit and converts it to an absolute value, a maximum value detection circuit that detects a maximum value among the absolute value circuit outputs, and a minimum value among the absolute value circuit outputs. A minimum value detection circuit that detects an object and feeds back an output to itself; a first-in first-out circuit that receives an output of the minimum-value detection circuit and stores it in the deepest part of the stack and outputs a value of the shallowest part at the same time; Receiving the output of the maximum value detection circuit and the output of the maximum value detection circuit, determine whether the difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is equal to or less than a predetermined threshold, and In the case of, a decision circuit that feeds back the output of the first-in first-out circuit to the first-in first-out circuit, and selects the output of the decision circuit and the output of the delay element according to the output of the timing circuit controlled by the estimation error And a storage device that receives the output of the selector and sequentially rewrites the stored contents. The output of the selector is fed back to the delay element, and at the same time, the matrix switch is controlled by the output of the storage device. It is characterized by the following.

Further, the system characteristic estimating apparatus of the present invention
When estimating system characteristics using an adaptive filter, a delay element array including a cascade connection of a plurality of delay elements for delaying an input signal by one sample period, an output of each delay element constituting the delay element array, and A plurality of multiplication circuits for multiplying by a coefficient corresponding to the delay element; a matrix switch for determining a connection relationship between the plurality of delay elements and the plurality of multiplication circuits; and a summation of outputs of the plurality of multiplication circuits. An adder; and a control circuit that receives outputs of the plurality of multiplication circuits and generates a control signal for the matrix switch. The multiplication circuit is configured to update the estimation error, the output of each of the delay elements, and a coefficient update. A coefficient generating circuit that generates a coefficient by receiving a constant to be used, and a multiplier that multiplies an output of the coefficient generating circuit by an output of each of the delay elements and outputs the result. The control circuit includes: an absolute value circuit that receives the output of the coefficient generation circuit and converts the output to an absolute value; a variance calculation circuit that receives the output of the absolute value circuit to calculate a variance; A maximum value detection circuit, a minimum value detection circuit that detects a minimum one of the absolute value circuit outputs and feeds back the output to itself, and a deepest portion of the stack receiving the output of the minimum value detection circuit. A first-in first-out circuit that outputs the value of the shallowest part at the same time as receiving the output of the first-in first-out circuit and the output of the maximum value detection circuit, and the difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is previously determined. A judgment circuit for judging whether or not the difference is equal to or less than a predetermined threshold value, and when the judgment result is equal to or more than the threshold value, a judgment circuit for feeding back the output of the first-in first-out circuit to the first-in first-out circuit; And a storage device that selects and outputs the output of the selector according to the output of the timing circuit controlled by the output of the dispersion calculation circuit, and a storage device that receives the output of the selector and sequentially rewrites the stored content. The matrix switch is controlled by the output of the storage device at the same time as the feedback to the delay element.

[0019]

The adaptive filter in the system characteristic estimating method and apparatus of the present invention can reduce the hardware scale by sequentially switching a limited number of tap coefficients and assigning them to different taps. Also, the adaptive filter adaptively controls the number of taps whose position is changed each time a coefficient is updated when a limited number of tap coefficients are assigned to a substantial waveform response part of an impulse response. As a result, the convergence time can be reduced.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In this figure, functional blocks to which the same reference numerals as in FIG. 10 are given have the same functions as in FIG. The difference between FIG. 1 and FIG.
₁ , 100 ₂ ,..., 100 _N are the delay element arrays 10 ₁ ,
10 ₂ ,..., 10 _N , matrix switch 14,
And the coefficient circuits 11 ₁ , 11 ₂ ,..., 11 _M. Accordingly, the control circuit 13
Controls the matrix switch 14 using the output of the coefficient circuit and the estimation error supplied from the subtractor 3.

In FIG. 1, the input signal supplied to the delay element 10 ₁ is supplied to the delay elements 10 ₂ ,.
…, Sequentially transmitted to 10 _N. Delay element rows 10 ₁ , 10
_2, ........., 10 _N is the M coefficient circuits via the matrix switch 14 11 _1, 11 _2, ........., it is connected to the 11 _M. However, N> M. The matrix switch 14 sequentially and adaptively connects the M delay element rows 10 _i selected by the output of the control circuit 13 and the M coefficient circuits 11 _j .

[0022] The configuration of the i-th coefficient circuits 11 _i shown in FIG. FIG. 2 is basically equivalent to the tap circuit of FIG. 8, with the only difference being that there is no delay element 81. The input signal 20 of FIG. 2 corresponds to the output signal of the delay element _10i of FIG. The other signals 21, 25, and 23 are 801 and 8 in FIG.
03, 802, a difference signal output from the subtractor 3, a signal supplied to the adder 12, and a step size, respectively. The coefficient generation circuit 22 and the multiplier 24 operate exactly the same as the coefficient generation circuit 82 and the multiplier 83 in FIG.

FIG. 3 shows a specific example of the control circuit 13. The input signal 300 in FIG. 3 is composed of M coefficient circuits 11 ₁ , 11 ₂ ,
........., the coefficient value C _m supplied from 11 _{M, k} and assigned tap number Z _m, the output signal 301 control signal of the matrix switch 14, the input signal 302 is the error signal supplied from the subtractor 3 . The coefficient value C _{m, k} supplied as the input signal 300 is converted into an absolute value by the absolute value circuit 31 and transmitted to the minimum value detecting circuit 33.

When the input to the minimum value detection circuit 33 is M samples, that is, when M coefficient values and tap numbers are used, these samples are _defined as [C _{m, k} , Zm]. In the minimum value detecting circuit 33 C _m, the minimum value min {C _m of _{k, k} | m
= 1, 2,..., M｝ = C _{j, k} and supplies the corresponding tap number Z _j to the FIFO 35. Z _j is fed back to the minimum value detecting circuit 33, by using the _{Z j {C m, k |} m = 1, 2, ........., M} the _{{C m, k | m =} 1
, 2,..., M, m {j}. Therefore,
Next, until a new {C _{m, k} } is supplied from the absolute value circuit 31 to the minimum value detection circuit 33, the smallest value of {C _{m, k} }, the second smallest value,. The corresponding tap numbers are supplied to the FIFO 35 in ascending order. At the same time F
The IFO 35 stores the signal Z _j supplied from the minimum value detection circuit 33 as a value at the end of the queue, sets the value at the head of the queue as a new Z _j , and transmits the new value to the selector 53. When a new Z _j is set, C _{j, k}
Is reset to zero. The selector 53 switches one of the new Z _j supplied from the FIFO 35 and the signal supplied from the delay element 54 by the output of the timing circuit 55, and transmits the signal to the storage device 39. A specific example of the above operation is given by M =
3, N = 7, Z _i = [136], FIFO initial value = [2
457] is shown in Table 1.

[0025]

[Table 1]

Using Table 1, the minimum value detection circuit 33 and the FI
The operation of the FO 35 will be described. However, for simplicity, it is assumed that the selector 53 always selects the output of the FIFO 35 and transmits it to the storage device 39. First, the result Z of the minimum value detection
₂ is obtained, and the value of Z ₂ = 3 is moved by the FIFO 35 to the end of the end of the queue, and 2 at the head of the queue is set as a new Z ₂ . Therefore, Z _i = [126], FIFO =
[4573] is obtained as the content of the storage device 39 when the number of times is 1. Next, the results Z ₁ of the minimum value detection is obtained, F
Go to after the last 3 queues value = 1 for Z ₁ in IFO35, the 4 the head of the queue as a new Z _1.
Therefore, Z _i = [426] and FIFO = [5731] are obtained as the contents of the storage device 39 when the number of times is 2.

The timing circuit 55 controls how many multiplicands are replaced for one multiplicand value update. The timing circuit 55 to which the error signal is supplied as the input signal 302 generates a signal that changes from 1 to 0 at a timing corresponding to the error signal 302. The output signal of the timing circuit 55 is determined so that when the error signal is large, a short 0 is obtained after a long series of 1s at first, and the opposite characteristic is obtained when the error signal is small. The output signal of the timing circuit 55 is supplied to the selector 53. The selector 53 selects the output of the delay element 54 when the output signal is 0, and selects the output of the selector 53 when the output signal is 1, and transmits the output to the storage device 39. . Further, the output of the selector 53 is fed back to the selector 53 after being delayed by one sample period via the delay element 54. Therefore, the storage device 39
When the output of the timing circuit 55 is 0, the coefficient assignment tap does not change with the value one sample period before. When the signal is 1, the coefficient assignment tap is the value newly supplied from the selector 53. Will change. That is,
When the value changes to 0 after 1 has been supplied from the timing circuit 55 for a long time, the contents of the storage device 39 change repeatedly, and tap replacement is performed. Conversely, if the value changes to 0 after a short sequence of ones, the contents of the storage device 39 hardly change. For example, in the case of Table 1, when the output of the timing circuit 55 changes from 1 to 0 at the end of the count 1, the content of the storage device 39 becomes 126, and at the end of the count 2, the output of the timing circuit 55 changes from 1 to 0. , The content of the storage device 39 becomes 426. The contents of the storage device 39 are output as an output signal 301. As is apparent from the above description, the output of the timing circuit 55 in FIG.
The number of coefficients replaced per one coefficient update is adaptively controlled based on the error signal. When the error signal is large, many coefficients are replaced, and when the error signal is small, small coefficients are replaced.

FIG. 4 is a block diagram showing another specific example of the control circuit 13. As shown in FIG. 4, the maximum value C _{1, k} is detected by the maximum value detection circuit 32 using the output of the absolute value circuit 31 and the corresponding tap number Z ₁ is transmitted to the determination circuit 37. The output is supplied to the selector 53 at the same time as the output Z _j of the FIFO 35 is supplied to the determination circuit 37. Judgment circuit 3
7 is a tap number Z ₁ supplied from the maximum value detection circuit 32.
If smaller than the threshold difference is given in advance of the supplied tap number Z _j from FIFO35 will transmit Z _j to the selector 53, the Zj otherwise FIFO35
Return to. The FIFO 35 places the returned Z _j at the end of the queue, and newly sets the head value of the queue as Z _j . The comparison with the threshold value and the resetting of Z _j are repeated until data is supplied from the determination circuit 37 to the selector 53. By the above operation, the value supplied to the storage device 39 from the determination circuit 37 and the value fed back to the selector 53 via the delay element 54, that is, the tap number and the tap of the maximum coefficient newly used for the multiplication The difference from the number can be limited to a certain value or less, and the taps are concentrated near the maximum coefficient tap.

FIG. 5 shows another embodiment of the present invention. In the embodiment shown in FIG. 5, instead of the control circuit 13 of FIG.
The control circuit 15 is used, and the error signal is no longer supplied to the control circuit 15. FIG. 6 is a block diagram of the control circuit 15 shown in FIG. 6 and 4 differ in the control method of the timing circuit 55. In FIG. 6, the timing circuit 55 is controlled not by the error signal but by the dispersion of the coefficient absolute value | C _{i, k} |, and for this purpose, a dispersion control circuit 56 is provided.

The output of the absolute value circuit 31 is
And the obtained variance of the coefficient absolute value is transmitted to the timing circuit 55. The timing circuit 55 is shown in FIG.
However, the output signal changes according to the variance of the coefficient absolute value output from the variance calculation circuit 56 instead of the error signal. The output signal of the timing circuit 55 is
The variance is determined so that when the variance is small, a short 0 is obtained after a long series of 1s, and when the variance is large, the opposite characteristic is obtained. This is because the update of the coefficient progresses,
When the error signal is reduced, the coefficients are arranged in a concentrated manner in the substantial waveform response part of the impulse response, compared to a case where all the coefficients are substantially zero distributed over a wide area other than the waveform response part. This is because the distribution of the coefficient absolute values becomes wider.

Although the LMS algorithm has been assumed so far, the only configuration unique to the LMS is the coefficient generation circuit shown in FIG. Therefore, the present invention can be applied to other algorithms including LIM. Although the application of the present invention has been described by taking the echo canceller as an example, the present invention can be applied to any system having an impulse response that can be expressed by a combination of a flat delay and a waveform response.

[0032]

As described in detail above, according to the present invention, the hardware scale can be reduced by sequentially switching a limited number of tap coefficients and assigning them to different taps. Further, the adaptive filter in the system characteristics estimation method and apparatus of the present invention, when allocating a limited number of taps to the substantial waveform response portion of the impulse response, by changing the number of replacement of the tap position, The convergence time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating details of a tap circuit in FIG. 1;

FIG. 3 is a block diagram illustrating a specific example of a control circuit of FIG. 1;

FIG. 4 is a block diagram showing another specific example of the control circuit of FIG. 1;

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a specific example of the control circuit of FIG. 5;

FIG. 7 is a block diagram showing an example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 8 is a block diagram showing details of a tap circuit in FIG. 7;

FIG. 9 is a block diagram showing details of a coefficient generation circuit in FIG. 8;

FIG. 10 is a block diagram showing another example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 11 is a block diagram showing details of a tap circuit in FIG. 10;

FIG. 12 is a block diagram illustrating details of a control circuit in FIG. 10;

[Description of Signs] 1 input terminal 2 2-wire to 4-wire conversion circuit 3 subtracter 4 output terminal 10 _i (1 ≦ i ≦ N) delay element 11 _i (1 ≦ i ≦ M) tap circuit 13 control circuit 14 matrix Switch 15 control circuit

Continuation of front page (56) References JP-A-4-230112 (JP, A) JP-A-4-234212 (JP, A) JP-A-3-266516 (JP, A) JP 8-31815 (JP) , B2) US Pat. No. 5,245,561 (US, A) US Pat. 1-177 “Tap position control algorithm of adaptive FIR filter and its application to echo canceller” IEICE Technical Report CS84-103P. 25-30 (1984/11/11) “Study on Tap Position Control Method for Tap Selective Echo Canceller” Annual Report of the Faculty of Engineering, The University of Tokyo, Vol. 44 (1985), p. 155-160 "Echo canceller with adaptive control of tap position"

Claims (10)

(57) [Claims] A multiplication is performed by adaptively combining a plurality of input signal samples delayed by one sample period with a plurality of adaptively changing multiplicands, and an address of a multiplicand not used in the multiplication is queued. When storing and estimating the system characteristics with an adaptive filter that outputs the sum of the multiplication results, updating the multiplicand using the estimation error and using the value of the multiplicand used for the multiplication, the multiplicand, A method for estimating system characteristics, comprising: repeatedly changing a multiplicand corresponding to a value in a queue until a predetermined number of times is reached; and adaptively controlling the number of times of the multiplication. 2. The system characteristic estimating method according to claim 1, wherein the adaptive control of the number of multiplicands to be exchanged is performed using an estimation error supplied from the outside. 3. The method according to claim 1, wherein the adaptive control of the number of the multiplicands to be replaced is performed using the values of the multiplicands. 4. The multiplicand replacement is set so that a multiplicand corresponding to an address which is a first value in a queue is used for multiplication, a minimum value of an absolute value of the multiplicand is detected, and a multiplicand corresponding to the minimum value is detected. 4. The system characteristic estimating method according to claim 1, wherein the address is stored at the end of the queue, and is further excluded from multiplication targets. 5. The multiplicand replacement is performed by examining whether or not the first value in the queue is within a predetermined range from the position of the maximum multiplicand value. Is stored at the end of the queue, the test is performed on the new queue head value, and the test is repeated until a new queue head value within the predetermined range is obtained. The multiplicand corresponding to the address that is the first value is set to be used for multiplication, the minimum value of the absolute value of the multiplicand is detected, and the address of the multiplicand corresponding to the minimum value is set at the end of the queue. 4. The method according to claim 1, wherein the data is stored and further removed from a multiplication target.
3. The method for estimating system characteristics according to item 1. 6. The multiplicand is updated by multiplying a plurality of delayed input signal samples by a characteristic estimation error, which is a difference between an adaptive filter output and a system output, to obtain a first multiplication result. The multiplication result is multiplied by a predetermined first constant to obtain a second multiplication result, and the second multiplication result and the delayed second multiplication result are added to obtain an addition result. 6. The system characteristic estimating method according to claim 1, wherein after delaying by one sample period, the sum is used for the addition, and the addition result is used as the updated multiplicand. 7. A delay element array formed by cascade connection of a plurality of delay elements for delaying an input signal by one sample period when estimating a system characteristic using an adaptive filter, and each delay constituting the delay element array. A plurality of multiplying circuits for multiplying an output of the element by a coefficient corresponding to each of the delay elements; a matrix switch for determining a connection relationship between the plurality of delay elements and the plurality of multiplying circuits; An adder for summing outputs; and a control circuit for receiving an estimation error that is a difference between the outputs of the plurality of multiplication circuits, the adaptive filter output, and the system output, and generating a control signal for the matrix switch. A coefficient generation circuit that generates a coefficient by receiving the characteristic estimation error, an output of each of the delay elements, and a constant used for updating a coefficient, An absolute value circuit configured to multiply an output of the coefficient generation circuit and an output of each of the delay elements and output the result, wherein the control circuit receives the output of the coefficient generation circuit and converts the output to an absolute value; A minimum value detection circuit that detects the minimum of the absolute value circuit outputs and feeds back the output to itself; and receives the output of the minimum value detection circuit and stores it in the deepest part of the stack, and at the same time the value of the shallowest part A first-in first-out circuit for outputting the output of the first-in first-out circuit, a selector for selecting and outputting the output of the first-in first-out circuit and the output of the delay element in accordance with the output of the timing circuit controlled by the estimation error, and sequentially rewriting the stored contents in response to the output of the selector. Wherein the matrix switch is controlled by the output of the storage device at the same time that the output of the selector is fed back to the delay element. Estimation device. 8. A control circuit, comprising: an absolute value circuit for receiving an output of a coefficient generation circuit and converting it to an absolute value; a maximum value detection circuit for detecting a maximum one of the absolute value circuit outputs; A minimum value detection circuit that detects the smallest one of the above and feeds back the output to itself, and a first-in first-out circuit that receives the output of the minimum value detection circuit, stores it in the deepest part of the stack, and outputs the value of the shallowest part Receiving the output of the first-in first-out circuit and the output of the maximum value detection circuit, and determines whether the difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is equal to or less than a predetermined threshold value. A determination circuit that feeds back the output of the first-in first-out circuit to the first-in first-out circuit when the output is greater than or equal to a threshold value; And a storage device that receives and outputs the output of the selector and sequentially rewrites the stored contents. The output of the selector is fed back to the delay element, and at the same time, the output of the storage device causes the matrix switch to operate. The system characteristic estimating device according to claim 7, wherein the system characteristic is controlled. 9. A delay element array comprising a cascade connection of a plurality of delay elements for delaying an input signal by one sample period when estimating a system characteristic using an adaptive filter, and each delay constituting the delay element array. A plurality of multiplying circuits for multiplying an output of the element by a coefficient corresponding to each of the delay elements; a matrix switch for determining a connection relationship between the plurality of delay elements and the plurality of multiplying circuits; An adder for calculating a sum of outputs; and a control circuit for receiving outputs of the plurality of multiplication circuits and generating a control signal for the matrix switch, wherein the multiplication circuit includes the estimation error and the delay element. A coefficient generation circuit for generating a coefficient in response to an output and a constant used for updating the coefficient,
An absolute value circuit configured to multiply an output of the coefficient generation circuit and an output of each of the delay elements and output the result, wherein the control circuit receives the output of the coefficient generation circuit and converts the output to an absolute value; A variance calculation circuit that receives the absolute value circuit output and calculates variance, a maximum value detection circuit that detects a maximum value among the absolute value circuit outputs, and detects a minimum value among the absolute value circuit outputs A minimum value detection circuit that feeds back an output to itself, a first-in first-out circuit that receives the output of the minimum value detection circuit, stores the output in the deepest portion of the stack, and outputs the value of the shallowest portion at the same time, an output of the first-in first-out circuit, Upon receiving the output of the maximum value detection circuit, determine whether the difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is equal to or less than a predetermined threshold value. Is the first-in first-out A judging circuit for feeding back the output of the circuit to the first-in first-out circuit, and a selector for selecting and outputting according to the output of the timing circuit which is controlled the output of the output and the delay element of the decision circuit at the output of the distributed computing circuit,
A storage device for sequentially rewriting storage contents in response to the output of the selector, wherein the matrix switch is controlled by the output of the storage device at the same time as the output of the selector is fed back to the delay element. Characteristic estimation device. 10. A coefficient generating circuit multiplies an output of each delay element by the characteristic estimation error, and multiplies an output of the first multiplier by a predetermined second constant. A second multiplier, an adder for adding an output of the second multiplier and an output of a fourth delay element to be described later, and delaying the output of the adder by one sample period and then feeding back to the adder 10. The system characteristic estimating apparatus according to claim 7, further comprising a fourth delay element, and outputting the delay element output as a coefficient value.