JP3167274B2 - Active matrix type liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device having a driving device built on a substrate.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device having a built-in signal line driving circuit is one in which a driving device is formed in the same step as a pixel transistor using polycrystalline polysilicon or the like. Conventionally, most of the active matrix type liquid crystal display devices are composed of small panels, and because of the limitations of the built-in transistor characteristics, only those for television applications having a relatively low frequency band of analog input are practically used. Not.

FIG. 7 shows a wiring example of image signal lines of a conventional active matrix type liquid crystal display device having a built-in signal line driving circuit. In FIG. 7, reference numeral 101 denotes a shift register for creating a timing for sampling an image signal, to which an image clock signal and a start data signal corresponding to a horizontal scanning period are input. 102a-102f
Denotes a plurality of image data signal wirings, which are arranged in parallel with each other. In this example, six image data signal lines are provided to transmit a 6-bit digital signal. 10
Reference numeral 3 denotes a latch, which is an image data signal wiring 102a to 102a.
The image signal of 2f is configured to be taken in based on the output of the shift register 101. Reference numeral 110 denotes an output wiring from the shift register 101;
f is a wiring for taking each image signal into the latch 103. A D / A converter 104 converts the digital signal of each latch 103 into a pulse amplitude modulated analog value waveform corresponding to an image signal. These constitute a signal conversion circuit. Output lines from each D / A converter 104 are connected to signal lines 105a to 105 of the liquid crystal display element.
x. These signal lines 105a to 105x are
They are arranged parallel to each other. Reference numeral 107 denotes a scanning line, which is arranged so as to be orthogonal to the signal lines 105a to 105x and parallel to each other.

The signal lines 105a to 105x
Each pixel portion is formed in the vicinity of the intersection between the pixel and the scanning line 107. Usually, each pixel portion has a liquid crystal 108a-1 of the pixel.
08x, and switching elements 106a to 106x composed of MOS transistors. This MOS
Switching elements 106a to 106 composed of transistors
6x, its source electrode is connected to the signal lines 105a to 105x, its gate electrode is connected to the scanning line 107,
Then, the drain electrodes are connected to the liquid crystals 108a to 108x of the pixels. 109 is a drive circuit for the scanning line 107,
It operates by a horizontal scanning clock signal and a vertical start data signal.

[0005]

[0006] Recent advances in technology have led to improvements in transistor characteristics and support for larger substrates. Accordingly, in the above-described conventional configuration of FIG. 7, the image data signal lines 102a to 102
Waveform distortion due to the difference in the number of cross portions at f became apparent.

For example, the signal wiring 102a shown in FIG.
Crosses only with the output wiring 110 of the shift register 101, and the number of cross portions is small. In contrast, signal line 1
02f also has five cross portions with the wirings 111a to 111e for taking in image signals to the latch 103. As a result, at the portion opposite to the input side of the image data signal wirings 102a to 102f (the right end in the drawing of FIG. 7),
The waveform is blunted by the wiring resistance and the large capacitance at the cross section. For this reason, there is a problem in that the image signal cannot be taken in at regular timing, and the image is disturbed.

Further, the image data signal lines 102a-102
An external digital drive circuit section for driving the driving circuit 102f must be designed with reference to the wiring 102f having the largest capacity, and requires a large driving current capability. Therefore, an increase in power consumption due to this is also a problem in liquid crystal display devices that are frequently used for portable applications.

Accordingly, an object of the present invention is to solve such a problem and average the difference between the capacitances of a plurality of image data signal lines to improve the driving frequency and reduce the power consumption. .

[0009]

In order to achieve this object, according to the present invention, a plurality of image data signal wirings parallel to each other are arranged in a bent state in the middle of the wiring, and symmetrically intersect each other at the bent parts. Is configured to
In the length direction of the plurality of image data signal wirings.
The number of cross sections is averaged . This allows
The capacitance of the cross portion is averaged, and the disturbance of the image due to the signal capture is eliminated.

Further, the present invention has time relationship changing means for changing the time relationship between the pixel cycle clock signal to the shift register and the image data signal within the horizontal scanning cycle.
The relationship changing means includes a plurality of delay gates connected in series.
It is a thing . This makes it possible to compensate for the delay of the image data signal and eliminate the disturbance of the image caused by the signal capture.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to a first aspect of the present invention is directed to a plurality of signal lines, a plurality of scanning lines intersecting with the signal lines, and a plurality of scanning lines arranged near intersections of the signal lines and the scanning lines. A provided pixel portion, a plurality of image data signal wirings parallel to each other,
A plurality of capture wirings arranged to intersect with the image data signal wiring and transmitting data of the image data signal wiring to each signal line; and the plurality of image data signal wirings parallel to each other, Bend in the middle of
Have symmetrical intersections at their bends
The length of the plurality of image data signal wiring
The number of cross sections in the vertical direction is averaged.
According to this, the image data signal transmitted through this wiring is averaged, the rounding of the waveform becomes the same, and the disturbance of the image due to the timing can be avoided.

According to a second aspect of the present invention, a signal line is driven.
A signal line driving circuit for inputting a horizontal scanning cycle start signal and a pixel cycle clock signal, and a shift register for inputting the horizontal scanning cycle start signal and the pixel cycle clock signal. A signal conversion circuit that drives the signal line by time-sampling an image data signal based on the output of the shift register, and further determines a time relationship between a pixel cycle clock signal to the shift register and the image data signal. There is a time relation changing means for changing the time relation within the horizontal scanning cycle, and the time relation changing means has a configuration in which a plurality of delay gates are connected in series. Thereby, the delay of the image data signal can be compensated, and the time over one cycle of the clock signal can be used for capturing the image data signal.

According to a third aspect of the present invention, there is provided a method for changing a time relationship.
The stage is configured to change the time phase difference between the pixel cycle clock signal to the shift register and the image data signal at the beginning and end of the horizontal scanning cycle. This makes it possible to compensate for a delay based on the time phase difference of the image data signal with respect to the pixel cycle clock signal.

According to a fourth aspect of the present invention , a plurality of signal lines are provided.
And a plurality of scanning lines arranged crossing the signal line,
A pixel portion provided near an intersection of the signal line and the scanning line;
And a signal line driving circuit for driving the signal line.
This signal line drive circuit starts the horizontal scanning cycle.
Shift register to which the clock signal and the pixel period clock signal are input.
And the start signal and pixel of these horizontal scanning periods.
Output of the shift register based on a periodic clock signal
Time sampling the image data signal
A signal conversion circuit for driving the signal line,
The pixel cycle clock signal to the shift register and the image
Change the time relationship with the image data signal within the horizontal scanning cycle.
Time relationship changing means.
At the beginning and end of the horizontal scanning period, the pixel
The time phase difference between the initial clock signal and the image data signal
At the beginning and end of the horizontal scanning cycle.
The clock cycle of the lock signal is configured to be different . This makes it possible to compensate for the delay based on the clock phase of the image data signal and the time phase difference with respect to the pixel cycle clock signal.

According to a fifth aspect of the present invention, there is provided a signal line driving circuit for driving a signal line, wherein the signal line driving circuit receives a shift signal to which a horizontal scanning cycle start signal and a pixel cycle clock signal are inputted. A register, and a signal conversion circuit that drives the signal line by time-sampling an image data signal based on an output of the shift register based on a start signal of the horizontal scanning cycle and a pixel cycle clock signal. And a time relationship changing means for changing the time relationship between the pixel cycle clock signal and the image data signal within a horizontal scanning cycle. According to this, by realizing the averaging of the delay of the wiring of the image data signal according to the invention of claim 1, there is an advantage that different time processing is not required for each image data signal.

Next, a first embodiment of the liquid crystal display device of the present invention will be described with reference to FIG. In FIG. 1, those having functions equivalent to those of the members shown in FIG.
The same reference numerals as those in FIG. 7 are assigned, and the detailed description is omitted.

In FIG. 1, image data signal wiring 102
a to 102f are wired in a bent state on the way, are arranged so as to intersect symmetrically with each other at the bent portion 112 as shown in the figure, and the number of cross portions in the length direction is equal to all image data signals. Wirings 102a-1
02f is the same. That is, in the example of FIG. 1, for example, before the bent portion 112, the wiring 102a is connected to the shift register 10 as described above.
Although it intersects only with the first output wiring 110, it intersects with wirings 111 a to 111 e for taking in image signals to the latch 103 after the bent portion 112. Conversely, for example, wiring 1
02f is the wiring 111a in front of the bent portion 112.
~ E, but only later intersects with the output wiring 110.

As described above, the image data signal wiring 102a
Bends 11 where 102f intersect symmetrically with each other
2 are formed at appropriate positions, so that each of the wirings 102a to 102a to 1
The number of cross portions at 02f can be averaged. For example, in the example of FIG. 1, the signal lines 105a to 105x
Assuming that the total number of stages of the driving circuit for driving the driving circuit is x, there are x times 5/2 cross sections for all the wirings 102a to 102f except for the output part of the common shift register 101. Therefore, the wirings 102a to 102a
The image data signal transmitted through 02f is averaged, and the rounding of the waveform becomes the same, so that image disturbance due to timing can be avoided.

In the example of FIG. 1, there is one intersection in the middle, but in the case of a large panel, a plurality of bent portions 112 are formed so as to intersect at a plurality of locations so that the waveform is more evenly rounded depending on the horizontal position. It is also possible.

A second embodiment of the liquid crystal display device according to the present invention will be described with reference to FIG. In FIG. 2, 2
Reference numeral 01 denotes a liquid crystal panel, the configuration of which is equivalent to that of FIG. Therefore, the same members as those of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Here, a clock modulator 202 modulates the phase of the image clock signal to the shift register 101. FIG. 3 shows a specific example of the clock modulator 202.
Here, reference numerals 301a to 301e denote delay gates whose numbers of stages are different based on a phase time described later. Reference numeral 302 denotes a high-speed multiplexer that switches the outputs of the delay gates 301a to 301e according to the phase difference modulation signal to make the entire delay amount variable.

FIG. 4A shows an example of the image clock signal and the image data signal at the power supply end at the left end of the screen in the drawing of FIG. Since it is the power supply end, there is no delay in wiring, and as shown in the figure, approximately one cycle of the image clock signal can be used for data capture. Normally, a hold time "thold" is required at the time of capturing, and in this case, the maximum time can be obtained.

FIG. 4B shows a waveform at the right end of the screen in the drawing of FIG. In this case, the wiring of the image clock signal has a small number of cross parts, so that the wiring delay due to the capacitance is small. However, the image data signal has a large wiring delay due to the large area of the cross part as described above. Therefore, in order to deal with this, inside the clock modulator 202, the delay gate 30
By selecting the output of 1e and shifting it by Δt, the hold time thold can be secured as in the case of the left end.

A liquid crystal display according to a third embodiment of the present invention will be described with reference to FIG. In FIG. 5, 5
Reference numeral 01 denotes a liquid crystal panel, which has the same configuration as that of FIG. 1, and therefore, the same members as those of FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The example of FIG. 5 is applied to a case where the delay of the image data signal is larger than that of FIG. Here, reference numeral 502 denotes a clock modulator similar to that of FIG. 2, and its internal configuration and operation are also the same. 503 is a memory for temporarily storing image data signals, and 504 is a memory 5
03 is an output latch. A pulse modulator 505 modulates the clock cycle of the image clock signal with a horizontal cycle.

Next, the operation based on the above configuration will be described with reference to FIG.
This will be described with reference to FIG. 6A and FIG. FIG. 6A shows an example of an image clock signal and an image data signal at the power supply end at the left end of the screen in the drawing of FIG. 5, and both have no waveform delay. FIG. 6B shows the waveform at the right end of the screen in the drawing of FIG. 5, and the delay of the image data signal is extremely large. However, here, in addition to shifting the clock signal by Δt as in the example of FIG. 2, the clock cycle is also shifted to the left end by the pulse modulator 505, that is, FIG.
It is longer than the case. Therefore, the hold time t
Hold can be secured for a necessary time.

The pulse modulator 505 can be realized by decoding a clock several times faster than the image clock signal. In order to make the horizontal cycle the same, the clock cycle is shorter than usual at the time of scanning at the left end on the drawing.
On the right side, it is necessary to slow down. Therefore, the image data signal causes a time difference in the memory 503 corresponding to the maximum delay.

The second embodiment (FIGS. 2 to 4) and the third embodiment (FIGS. 5 to 6) of the present invention are similar to the first embodiment (FIG. 1). By realizing the averaging of the delay of the wiring of the image data signal, there is an advantage that the practical value is high because different time processing is not required for each image data signal.

[0029]

According to the present invention as described above, according to the present invention, a plurality of parallel image data signal lines with each other, are arranged in a state bent along the wire, to so that is symmetrically crossed with each other at the bent portion These multiple image data
The number of cross sections along the length of the
Since the levels are equalized, the delays of the plurality of image data signal wirings are averaged, and it is possible to prevent screen disturbance. Further, since the capacity is equal between the image data signals, power consumption can be reduced by optimizing the current capability of the drive circuit.

According to the invention, there is provided a time relationship changing means for changing the time relationship between the pixel cycle clock signal to the shift register and the image data signal within the horizontal scanning cycle ,
The time relationship changing means includes a plurality of delay gates connected in series.
Because you like those being continued, the time relationship between the image data signals and the pixel period clock signal can be varied during the scanning of the one end and the other end of the screen, Therefore increasing the time allowance This makes it possible to prevent screen disturbance even with a low-speed device.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a clock modulator in FIG. 2;

FIG. 4 is a waveform diagram in the liquid crystal display device of FIG.

FIG. 5 is a configuration diagram of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 6 is a waveform chart in the liquid crystal display device of FIG.

FIG. 7 is a configuration diagram of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Shift register 102a-102f Image data signal wiring 103 Latch 104 D / A converter 105a-105x Signal line 110 Output wiring 111a-111f Intake wiring 112 Bent part 202 Clock modulator 502 Clock modulator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G09G 3/20 680 G09G 3/20 680F (56) References JP-A-6-105263 (JP, A) JP-A-9-92986 (JP, A) JP-A-8-227283 (JP, A) JP-A-8-146919 (JP, A) JP-A-2-309773 (JP, A) JP-A-7-56536 (JP, A) JP-A-8-262994 (JP, A) JP-A-5-99788 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505 -580 G09F 9/00-9/46

Claims (5)

(57) [Claims] A plurality of signal lines, a plurality of scanning lines arranged to intersect with the signal lines, a pixel portion provided near an intersection of the signal lines and the scanning lines, The image data signal wiring of the, and arranged to intersect with the image data signal wiring, having a plurality of capture wiring to transmit the data of the image data signal wiring to each signal line,
The plurality of image data signal wirings parallel to each other have a bent portion in the middle of the wiring, and are configured to intersect symmetrically with each other at the bent portion, over the length direction of the plurality of image data signal wirings. Wherein the number of cross portions is averaged. 2. A signal line driving circuit for driving a signal line.
Has, the signal line driver circuit includes a shift register the start signal and pixel period clock signal of the horizontal scanning period is input, the output of the shift register based on the start signal and the pixel periodic clock signal of the horizontal scanning period A signal conversion circuit that drives the signal line by time-sampling an image data signal, and further changes a time relationship between a pixel cycle clock signal to the shift register and the image data signal within a horizontal scanning cycle. 2. The active matrix type liquid crystal display device according to claim 1 , further comprising a time relation changing means, wherein the time relation changing means comprises a plurality of delay gates connected in series. 3. The time relationship changing means is configured to change a time phase difference between a pixel cycle clock signal to the shift register and an image data signal at the beginning and end of a horizontal scanning cycle. An active matrix liquid crystal display device according to claim 2. And a plurality of signal lines, a plurality of scanning lines arranged to intersect the signal lines, a pixel portion provided near an intersection of the signal lines and the scanning lines, A shift register to which a start signal of a horizontal scanning cycle and a pixel cycle clock signal are inputted, and a start signal of the horizontal scanning cycle and a pixel cycle clock. A signal conversion circuit for driving the signal line by time-sampling an image data signal based on an output of the shift register based on a signal, and further comprising a time period between the pixel cycle clock signal and the image data signal to the shift register And a time relationship changing means for changing the relationship within the horizontal scanning cycle, wherein the time relationship changing means sets the shift register at the beginning and end of the horizontal scanning cycle. Wherein the time period difference between the pixel cycle clock signal and the image data signal is changed, and the clock cycle of the pixel cycle clock signal is made different at the beginning and end of the horizontal scanning cycle. Matrix type liquid crystal display device. 5. A signal line driving circuit for driving a signal line, the signal line driving circuit comprising: a shift register to which a start signal of a horizontal scanning cycle and a pixel cycle clock signal are inputted; A signal conversion circuit that drives the signal line by time-sampling an image data signal based on an output of the shift register based on a start signal and a pixel cycle clock signal, and further includes a pixel cycle clock signal to the shift register. 2. An active matrix type liquid crystal display device according to claim 1, further comprising a time relation changing means for changing a time relation with the image data signal within a horizontal scanning cycle.