JP3165104B2 - Automatic wiring method and recording medium storing a program for executing automatic wiring processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an automatic wiring method, and more particularly to an automatic wiring method for an LSI in which a small-amplitude signal circuit and a large-amplitude signal circuit are mounted on the same chip.

[0002]

2. Description of the Related Art In recent years, LSIs that combine high-speed operation and low power consumption have been required in the field of communications and testers. In order to meet these demands, a high-speed operation small-amplitude signal circuit and a low-consumption large-amplitude signal are required. L on which both circuits are mounted on the same chip
SI is increasing.

Such an LSI is previously provided on a chip having a cell area in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged. LEF (Library Exchange Fo) including wiring prohibition information and wiring placement rule information for each function block and the entire chip.
rmat) information and circuit connection information of each circuit. Note that this automatic wiring processing is generally executed by a storage device and a data processing device that store an automatic wiring processing program recorded on a recording medium or the like.

At this time, for example, a CML circuit for a small amplitude signal of 0.25 V and a BiCMOS for a large amplitude signal of 3 V
When wiring an LSI which is on the same chip as a circuit by automatic wiring, it is necessary to separate the signals of each circuit so that noise due to the large amplitude signal wiring of the BiCMOS circuit does not get on the small amplitude signal wiring of the CML circuit. was there.

FIGS. 5 and 6 are partial flow charts respectively showing the first half and the second half of a flow example of the conventional automatic wiring method. FIG. 7 is a layout diagram showing a layout example of a chip wired by the conventional automatic wiring method.

Referring to FIG. 5, this conventional automatic wiring method uses steps 601 to 604 and 606 in order to separate the signal wiring as a measure to prevent the signal line of the CML circuit from entering the BiCMOS cell area shown in FIG. ~ 609
Then, based on the LEF information 61, the LEF information 62 and the circuit connection information 60 in which wiring is prohibited in the CML cell area and the BiCMOS cell area, the CML cell area and the Bi
In order to automatically wire the CML circuit and the BiCMOS circuit separately in the CMOS cell area to create automatic wiring information 63 and 64, and then to perform wiring for the entire chip,
At step 611, the automatic wiring information 63 and 64 are merged, and at steps 612 and 613, the merged information is
Based on the LEF information 65 that does not prohibit wiring on the CML cell area and the BiCMOS cell area, and the circuit connection information 60, automatic wiring is performed for the entire chip that connects each signal wiring via a level conversion circuit. That is, the automatic wiring is performed three times in total.

Here, first, steps 601 to 604
When performing automatic wiring of the CML cell area by using
All the S circuits are unwired because the LEF information 61 prohibits wiring on the BiCMOS cell area.
It is indistinguishable whether the entire non-wiring of the BiCMOS circuit and the signal non-wiring generated by the automatic wiring of the CML cell area are true non-wiring or false non-wiring due to wiring prohibition. When automatic wiring is performed in the entire chip in steps 612 and 613, the CML cell area, the BiCMO
Since the wiring on the S cell area is not prohibited, the non-wiring of the CML circuit passes over the BiCMOS cell area where the wiring channel has room. For this reason, in the second half flow shown in FIG.
The CML circuit wiring passing over the S cell area is checked and corrected.

Referring to FIG. 7, it is checked in step 607 whether or not there is any unwired wiring. If YES, the wiring is corrected in step 608. In step 607, N
In the case of O, in steps 609 to 610, the automatic wiring information 6
7. Merge the artwork information 68 into a BiCM
The CML circuit wiring that passes over the OS cell area is searched, the wiring is manually corrected in step 611, and the process returns to the automatic wiring process.
Perform I design.

[0009]

The prior art described above has the following problems.

The first problem is that in order to perform wiring separation,
On the CML cell area and the BiCMOS cell area, the wiring prohibition information is mutually defined, and the CML circuit and the BiCMOS circuit are separately and automatically wired, respectively. Then, the entire chip is automatically wired to connect the CML cell area and the BiCMOS cell area. However, automatic wiring must be performed three times in total.

The second problem is that, during automatic wiring of the entire chip, the line is not prohibited on the CML cell area and the BiCMOS cell area, so that the non-wiring of the CML circuit passes over the BiCMOS cell area where there is enough wiring channel. And CM
It is highly possible that the large amplitude signal wiring of the BiCMOS circuit is adjacent to the small amplitude signal wiring of the L circuit.
The large amplitude signal of the S circuit gets on the small amplitude signal of the CML circuit as noise and causes a malfunction of the CML circuit.

The third problem is that in order to prevent the above-mentioned malfunction, the signal wiring of the CML circuit passing over the BiCMOS cell area is searched, the wiring is corrected manually, the layout is verified again, and the LSI design is performed. In order to do so, the design time was long.

Accordingly, it is an object of the present invention to reduce the number of times of automatic wiring of an LSI in which circuits having different signal amplitudes are mounted on the same chip, to shorten the LSI design time, and to reduce the design cost.

[0014]

Therefore, the present invention is directed to a cell area in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged in advance. An automatic wiring method for automatically wiring the chip and each function block on the basis of the LEF information including the wiring prohibition information and the wiring arrangement rule information and the circuit connection information of each circuit. LEF from the real wiring layer or terminal layer of the block to the virtual wiring layer defined independently.
Information is converted into data, automatically wired in the virtual wiring layer, and converted into data in the actual wiring layer or the terminal layer.

Or a plurality of circuits having different signal amplitudes;
LEF including wiring inhibition information and wiring layout rule information of this chip and each function block is provided on a chip having each cell area in which respective base cells corresponding to a circuit for converting an amplitude level among these circuits are separately arranged in advance. In an automatic wiring method for automatically wiring based on information and circuit connection information of each of the circuits, a virtual method for data-converting the LEF information from a real wiring layer or a terminal layer of the chip and each of the function blocks to a virtual wiring layer independently defined. LE
An F conversion step, a virtual automatic wiring step for automatically wiring in the virtual wiring layer based on the information converted in the virtual LEF conversion step and the circuit connection information, and an automatic wiring information created in the virtual automatic wiring step. And an actual wiring conversion step of converting data to an actual wiring layer or a terminal layer.

The virtual LEF conversion step includes extracting information corresponding to each of the function blocks from the LEF information, converting the information into the virtual wiring layer for each of the function blocks, and merging the data. Extracting information corresponding to the chip from LEF information, converting the data to the virtual wiring layer for each of the cell areas, and merging the data.

Further, the virtual automatic wiring step includes a step of performing a non-wiring check and a wiring correction.

[0018]

Next, the present invention will be described with reference to the drawings.

The automatic wiring method of the present invention, as in the prior art,
Wiring of this chip and each function block on a chip having each cell area in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged. Automatic wiring is performed based on the LEF information including the prohibition information and the wiring arrangement rule information and the circuit connection information of each circuit. Also, this automatic wiring
This is executed by a storage device and a data processing device that store an automatic wiring processing program recorded on a recording medium or the like.

FIG. 1 is a flowchart showing an embodiment of the automatic wiring method of the present invention. Referring to FIG. 1, the automatic wiring method according to the present embodiment converts data of LEF information from a real wiring layer or a terminal layer of a chip and each function block to an independently defined virtual wiring layer, and performs automatic wiring in the virtual wiring layer. Steps 1, 2, 3 for converting data to an actual wiring layer or terminal layer are included. The operation will be described next in the order of these steps.

First, in step 1 of FIG. 1, the data of the LEF information is converted from the real wiring layer or terminal layer of the chip and each function block to an independently defined virtual wiring layer. At this time, information corresponding to each function block and chip is extracted from the LEF information, and from the real wiring layer or terminal layer to the virtual wiring layer for each function block or each cell area in the chip.
Data conversion is performed for each. FIG. 2 and FIG. 3 are partial detailed flow charts respectively showing a part of a detailed flow example of step 1, and FIG. 2 is a partial detailed flow example for performing data conversion for each function block.
Shows an example of a partial detailed flow for performing data conversion for each cell area in a chip.

Referring to FIG. 2, first, detailed step 1
In step 11, information 10 b corresponding to only each function block is extracted from the LEF information 10.
In steps 2 to 116, the type of each function block is determined using the function block name as a keyword, and the level conversion circuit (1) block, level conversion circuit (2) block, CML block, BiCMOS block, CMLI / O block, BiCMOSI / Classify into O block.

If it is classified into the level conversion circuit (1) block in the detailed step 112,
In a, the information of the real wiring layer in each block is transferred to the virtual wiring layer according to the type of information as follows: 6 layers (1AL) → 1 layer, 11 layers, 37 layers (1TH) → 2 layers, 12 layers , 36 layers (2AL) → 3 layers, 13 layers, 41 layers (2TH) → 4 layers, 14 layers, 40 layers (3AL) → 5 layers, 15 layers Data conversion is performed, and detailed step 112b
When the information of the terminal layer of each block is the input (Hxxx), the information is output to the virtual wiring layers 1, 3, and 5 (Nxxx).
In the case of (1), data is converted to the virtual wiring layers 11, 13, and 15, respectively.

If it is classified into the level conversion circuit (2) block in the detailed step 113,
In a, the information of the real wiring layer in each block is transferred to the virtual wiring layer according to the type of information as follows: 6 layers (1AL) → 1 layer, 11 layers, 37 layers (1TH) → 2 layers, 12 layers , 36 layers (2AL) → 3 layers, 13 layers, 41 layers (2TH) → 4 layers, 14 layers, 40 layers (3AL) → 5 layers, 15 layers
When the information of the terminal layer of each block is input (Hxxx), the output (Nx) is sent to the virtual wiring layers 11, 13, and 15.
In the case of xx), the data is converted into the virtual wiring layers 1, 3, and 5, respectively.

If the block is classified into the CML block in the detailed step 114, the information of the actual wiring layer in each block is transferred to the virtual wiring layer in the detailed step 114a according to the type of information. One layer, 37 layers (1TH) → 2 layers, 36 layers (2AL) → 3 layers, 41 layers (2TH) → 4 layers, 40 layers (3AL) → 5 layers Data conversion is performed for each layer, detailed step 114b
Thus, the information of the terminal layer of each block is converted into the virtual wiring layers 1, 3, and 5 for both input and output.

If the block is classified as a BiCMOS block in the detailed step 115, the information of the actual wiring layer in each block is transferred to the virtual wiring layer in the detailed step 115a according to the type of information. Data conversion is performed for 11 layers, 37 layers (1TH) → 12 layers, 36 layers (2AL) → 13 layers, 41 layers (2TH) → 14 layers, 40 layers (3AL) → 15 layers, and detailed steps 115b
Then, the information of the terminal layer of each block is converted into data of the virtual wiring layers 11, 13, and 15 for input and output.

If the block is classified into a CMLI / O block in the detailed step 116, each CM is
If the information of the terminal layer of the LI / O block is input and output, the data is converted into the virtual wiring layers 1, 3, and 5, respectively, and classified into the BiCMOS I / O block in the detailed step 116, and in the detailed step 117b, , Each BiCMOS
The information of the terminal layer of the I / O block is input and output, and the data is converted to the virtual wiring layers 11, 13, and 15, respectively.

In a detailed step 117, information converted into a virtual wiring layer for each function block is subjected to data merging, and LEF information 11b of the virtual wiring layer corresponding to only the function block is created.

Referring to FIG. 3, first, in a detailed step 121, information 10c corresponding to only the chip is extracted from the LEF information 10, and detailed steps 122 to 125 are performed.
Then, the type of each base cell is determined using the block name of the base cell of the chip as a keyword, and the CML cell, BiCMOS
Cell, level conversion circuit cell, BiCMOS I / O cell,
Classify into CMLI / O cells.

If the CML cell is classified in the detailed step 122, a CML cell area in which the CML cell is arranged is extracted in a detailed step 122a. Detailed Step 12
In step 2b, the wiring channel information on the CML cell area is extracted. In a detailed step 122c, the wiring channel information on the CML cell area is changed from a real wiring layer to a virtual wiring layer in the following 6 layers (1AL) → 1 layer , 37 layers (1TH) → 2 layers, 36 layers (2AL) → 3 layers, 41 layers (2TH) → 4 layers, 40 layers (3AL) → 5 layers Data conversion is performed for each layer, and detailed steps 122d
Then, the wiring prohibition information on the CML cell area is extracted, and in a detailed step 122e, the wiring prohibition information on the CML cell area is converted from the real wiring layer to the virtual wiring layer for each layer in the same manner as the wiring channel information. Is done.

If the cell is classified as a BiCMOS cell in the detailed step 123, the BiCMO
The BiCMOS cell area where the S cells are arranged is extracted. In a detailed step 123b, wiring channel information on the BiCMOS cell area is extracted, and a detailed step 123c
Then, the wiring channel information on the BiCMOS cell area is
From real wiring layer to virtual wiring layer, the following 6 layers (1AL) → 11 layers, 37 layers (1TH) → 12 layers, 36 layers (2AL) → 13 layers, 41 layers (2TH) → 14 layers, 40 layers (3AL) → Data is converted for each layer of 15 layers, detailed step 123d
Then, the wiring prohibition information on the BiCMOS cell area is extracted, and in a detailed step 123e, the wiring prohibition information on the BiCMOS cell area is data-converted from a real wiring layer to a virtual wiring layer for each layer in the same manner as the wiring channel information. You.

If the cell is classified as a level conversion circuit cell in the detailed step 124, a level conversion circuit cell area in which the level conversion circuit cell is arranged is extracted in a detailed step 124a. In a detailed step 124b, wiring channel information on the level conversion circuit cell area is extracted, and a detailed step 1
At 24c, the wiring channel information on the level conversion circuit cell area is transferred from the real wiring layer to the virtual wiring layer by the CML block,
According to the wiring connection from the BiCMOS block, the following 6 layers (1AL) → 1 layer, 11 layers, 37 layers (1TH) → 2 layers, 12 layers, 36 layers (2AL) → 3 layers, 13 layers, 41 layers (2TH) → 4 layers, 14 layers, 40 layers (3AL) → 5 layers, 15 layers Data conversion is performed for each layer, detailed step 124d
Then, the wiring prohibition information on the level conversion circuit cell area is extracted, and in a detailed step 124e, the wiring prohibition information on the level conversion circuit cell area is converted from the real wiring layer to the virtual wiring layer in the same manner as the wiring channel information. Is converted.

If the cell is classified as a CMLI / O cell in the detailed step 125, the CMLI / O cell is specified in a detailed step 125a.
Extract the CMLI / O cell area where the O cell is located,
In a detailed step 125b, the wiring prohibition information on the CMLI / O cell area is extracted. Also, detailed step 125c
Then, the wiring prohibition information on the CMLI / O cell area is changed from the real wiring layer to the virtual wiring layer according to the type of information as follows: 6 layers (1AL) → 1 layer, 11 layers, 37 layers (1TH) → 2 Data conversion is performed for each of the following layers: 12 layers, 36 layers (2AL) → 3 layers, 13 layers, 41 layers (2TH) → 4 layers, 14 layers, 40 layers (3AL) → 5 layers, 15 layers.

In the detailed step 125, BiCMOS I / O
If it is classified into a cell, Bi in step 126a
The BiCMOS I / O cell area in which the CMOS I / O cell is arranged is extracted, and in a detailed step 126b, the BiCM
The wiring prohibition information on the OSI / O cell area is extracted. Further, in the detailed step 126c, the wiring prohibition information on the BiCMOS I / O cell area is changed from the real wiring layer to the virtual wiring layer according to the type of information as follows: 6 layers (1AL) → 1 layer, 11 layers, 37 layers (1TH) → 2 layers, 12 layers, 36 layers (2AL) → 3 layers, 13 layers, 41 layers (2TH) → 4 layers, 14 layers, 40 layers (3AL) → Data for 5 layers, 15 layers Is converted.

In the detailed step 128, the information converted into the virtual wiring layer for each cell area in the chip is merged with the data, and the LEF of the virtual wiring layer corresponding to the entire chip is merged.
The information 11c is created.

Next, in steps 2 and 3 of FIG. 1, automatic wiring is performed in the virtual wiring layer based on the LEF information and circuit connection information of the virtual wiring layer created in step 1,
Data conversion from the virtual wiring layer to the real wiring layer or the terminal layer. FIG. 4 is a detailed flowchart showing an example of a detailed flow of these steps 2 and 3 and subsequent steps.

Referring to FIG. 4, in the detailed steps 201 to 203 of step 2, the LEF information 11b and 11c of the virtual wiring layer created in step 1 and the circuit connection information 2
0, block layout of all circuits is performed in the virtual wiring layer, and schematic wiring is performed on the entire surface of the chip. Then, detailed automatic wiring is performed on the entire surface of the chip, and automatic wiring information 21 is created. Then, the non-wiring check and the wiring correction are performed on the automatic wiring information 21.

Further, detailed step 301 of step 3
Then, the automatic wiring information 21 is transferred from the virtual wiring layer to the real wiring layer or the terminal layer in the following order: 1 layer, 11 layers → 6 layers (1AL), 2 layers, 12 layers → 37 layers (1TH), 3 layers, 13-layer → 36-layer (2AL), 4-layer, 14-layer → 41-layer (2TH), 5-layer, 15-layer → 40-layer (3AL), data conversion, automatic wiring of actual wiring layer or terminal layer Information 31 is created.

Subsequent to step 3, step 40
In step 1, the data of the automatic wiring information 31 and the artwork information 40 are merged, and the layout information 41 of the LSI is created.

[0040]

As described above, according to the automatic wiring method of the present invention, the L and L functions are changed from the actual wiring layer or the terminal layer of the chip and each function block to the independently defined virtual wiring layer.
Data conversion of EF information, automatic wiring in virtual wiring layer, and data conversion to real wiring layer or terminal layer, so that automatic wiring information of the entire chip is created at one time so that wiring channels of circuits with different signal amplitudes do not overlap each other. This eliminates the need for automatic wiring for each cell area.

Further, since automatic wiring is performed once in the virtual wiring layer, non-wiring information in the automatic wiring information is reduced, and checking of non-wiring and correction of wiring are facilitated.

Further, since the wiring channels of the circuits having different signal amplitudes do not overlap each other, manual wiring correction after the artwork processing is not required, so that the LSI design time can be shortened and the LSI design cost can be reduced. There are effects such as being done.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of an automatic wiring method according to the present invention.

FIG. 2 is a partial detailed flowchart showing an example of a detailed flow of a part of step 1 of FIG. 1;

FIG. 3 is a partial detailed flowchart showing an example of a detailed flow of a part of Step 1 of FIG. 1;

FIG. 4 is a detailed flowchart showing an example of a detailed flow of steps 2 and 3 in FIG. 1;

FIG. 5 is a partial flowchart showing the first half of a flow example of a conventional automatic wiring method.

FIG. 6 is a partial flowchart showing the latter half of a flow example of a conventional automatic wiring method.

FIG. 7 is a layout diagram showing a layout example of a chip according to a conventional automatic wiring method.

[Explanation of symbols]

1-3, 401, 601-611 Steps 10, 10b, 10c, 11b, 11c, 20, 60-
69 Information 111-301 Detailed Steps

Claims (6)

(57) [Claims] 1. A chip having respective cell areas in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged in advance. LEF (Libr containing the function block wiring prohibition information and wiring placement rule information )
In an automatic wiring method for performing automatic wiring based on information ( ary Exchange Format) and circuit connection information of each of the circuits, the LE and the real wiring layer or the terminal layer of the chip and each of the function blocks are converted to a virtual wiring layer independently defined.
F information is converted into data and automatically wired in the virtual wiring layer,
An automatic wiring method, wherein data is converted to the actual wiring layer or the terminal layer. 2. A chip having cell areas in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged in advance. LEF (Libr containing the function block wiring prohibition information and wiring placement rule information )
In an automatic wiring method for performing automatic wiring based on information ( ary Exchange Format) and circuit connection information of each of the circuits, the LE and the real wiring layer or the terminal layer of the chip and each of the function blocks are converted to a virtual wiring layer independently defined.
A virtual LEF conversion step of converting F information into data, a virtual automatic wiring step of automatically wiring in the virtual wiring layer based on the information converted in the virtual LEF conversion step and the circuit connection information, and a virtual automatic wiring step An actual wiring conversion step of converting the obtained automatic wiring information into the actual wiring layer or the terminal layer. 3. The virtual LEF conversion step comprises:
Extracting information corresponding to each of the function blocks from the EF information, converting the data to the virtual wiring layer for each function block, and merging them; and extracting information corresponding to the chip from the LEF information, 3. The automatic wiring method according to claim 2, further comprising the steps of: converting data into a virtual wiring layer for each of said cell areas; and merging the data. 4. The virtual automatic wiring step includes a step of performing a non-wiring check and a wiring correction.
Automatic wiring method as described. 5. A chip having each cell area in which base cells corresponding to a plurality of circuits having different signal amplitudes and a circuit for converting an amplitude level among these circuits are separately arranged in advance. LEF (Libr containing the function block wiring prohibition information and wiring placement rule information )
a recording medium for recording a program for executing an automatic wiring process for performing automatic wiring based on the information of the circuit ( ary Exchange Format) and the circuit connection information of each of the circuits; LE to independent defined virtual wiring layer
A virtual LEF conversion step of converting F information into data, a virtual automatic wiring step of automatically wiring in the virtual wiring layer based on the information converted in the virtual LEF conversion step and the circuit connection information, and a virtual automatic wiring step A real wiring conversion step of converting the obtained automatic wiring information into the real wiring layer or the terminal layer. The recording medium which stores a program for executing the automatic wiring processing. 6. The virtual LEF conversion step comprises:
Extracting information corresponding to each of the function blocks from the EF information, converting the data to the virtual wiring layer for each function block, and merging them; and extracting information corresponding to the chip from the LEF information, 6. A recording medium storing a program for executing an automatic wiring process according to claim 5, comprising a step of converting data into a virtual wiring layer for each of said cell areas and merging them.