JP3160279B2 - Resistance and its manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] <Industrial application field> The present invention relates to an integrated circuit structure, and more particularly to a technique for forming a resistor on a semiconductor substrate.

<Conventional Technology> The semiconductor industry has traditionally aimed at reducing the dimensions of structural elements in integrated circuit chips. In an electrostatic memory cell, for example, a resistor instead of a transistor is often used as a load element in order to eliminate the need to arrange more circuit elements on a semiconductor substrate. The resistor is located above the other active elements of the substrate, thereby reducing the overall space that the electrostatic memory cell can occupy. However, common resistors require a contact area to connect other elements to the resistor, and this contact area occupies space to be used for other elements, so that the resistance itself is larger than the desired area. Will be occupied. It is therefore advantageous to reduce the space occupied by the contact area.

Also, since the layers are successively patterned using separate masks in the integrated circuit structure, space must be allocated for misalignment of one mask with respect to the next. By reducing the space required to form mismatches or contacts, the total space that must be used for circuit elements is reduced. This further increases the speed at which the integrated circuit can operate and the number of elements that can be placed on an integrated circuit of a given size.

FIGS. 1.1a to 1.7b show the prior art and the resistor 13 respectively.
7A and 7B are a top view and a side cross-sectional view showing each manufacturing process of r and its final structure. Figures 1.1b to 1.7b each correspond to Figure 1.
FIG. 1B is a cross-sectional view taken along line AA of FIGS. 1A to 1.7A. In these drawings, the same elements are denoted by the same reference numerals. As shown in FIG. 1.1b, on the substrate 11, an oxide layer, a structure consisting of an oxide layer covered with a nitride layer, or a plurality of oxides, polycrystalline silicon or other materials. A more complex structure having layers, namely a layer 12, is formed. However, the top of layer 12 is an insulator. To form a resistor, on the layer 12, e.g. 1.
Generally 1000-5000 1 as shown in Fig.
A layer of high resistance material such as undoped or lightly doped polycrystalline silicon layer 13 having a thickness of

As shown in FIGS. 1.2a and 1.2b, the layer 13 is patterned to form a resistor 13p that serves as a resistor and its conductive contact area.
To form 1.3a and 1.3b, as shown in FIGS. 1.3a and 1.3b, a protective layer formed of an insulating material including oxide or oxide and nitride, or in another embodiment, a photoresist material
A 14 is formed on the surface of the resistive structure 13p and the exposed portion of the layer 12 on the structure. Layer 14 is shown in FIG.
Patterned as shown in FIG. 14b, forming a mask 14p, exposing the resistive structure 13p except for the position under the portion of the mask 14p that maintains a high resistance.

As shown in FIG.1.5b, doping or addition of impurities is performed, for example, by diffusion or ion implantation,
The doped regions 15a and 15b are formed, and the resistor 13r is left under the mask 14p. Since the added impurities diffuse in the next heating step, high-concentration doped regions 15a and 15b extending below the mask 14p are formed. In order to keep the resistance 13r high enough (Fig. 1.5b), two conductive regions
The final length of resistor 13r between 15a and 15b is generally about 1.0-1.
2μ. Doped region masks by lateral diffusion1
The length of the mask or protected area 14p should generally be between 3.0 and 3.5 microns, as it extends about 1.0-1.25 microns below each edge of 4p.

The space allocated to the protected area 14p is less if the material used does not require an implant that causes lateral diffusion. In such a case, the length of the protected area 14p is 1.
It is short at about 1.2μ.

As shown in FIGS. 1.6a and 1.6b, the oxide film layer 16
Is applied and patterned to open portions 16a, 16b to expose contacts in regions 15a, 15b. Finally, on the surface of this structure, as shown in Figures 1.7a and 1.7b, aluminum, often polycrystalline silicon or Tt Si, WSi2, TiSi, TaSi2, or MoSi
A conductive layer 17 that can also use a refractory silicide such as 2 is applied and patterned to leave conductive lines 17a and 17b.

1.0-1.2μ spacing for resistance mask plus resistance
An additional margin of about 0.5μ must be allowed at each end due to alignment errors of the contact openings 16a, 16b with respect to 13r.

1.2 μm for each contact opening 16a, 16b, 1.0-1.2μ necessary to secure the desired resistance of several hundred gigaΩ to several teraΩ for the resistor 13r, and 1.5 at both ends for matching error.
Allowing for a minimum dimension of μ, the overall length of the conventional structure of FIGS. 1.1a to 1.7b is approximately 4.4 to 4.6μ.

<Problem to be Solved by the Invention> It is an object of the present invention to significantly reduce the size of the entire structure of an integrated circuit resistor.

According to the present invention, a resistive layer preferably made of undoped polycrystalline silicon is formed on an insulating layer, and the final resistance width is reduced. The pattern is formed in the region having. An insulating layer, preferably silicon dioxide, is applied to this structure to cover the resistance region. A photoresist layer is formed and patterned on the insulating layer. The photoresist layer is then patterned to leave a protected area, which can be as short as the dispensing capability of the user's exposure device. The latest resolution is typically 1.2μ.

Insulating and resistive materials not protected by the photoresist layer are removed. Next, the protective photoresist layer is removed, the top and sides are covered with an insulating material, leaving a resistor with both ends exposed.
These exposed ends function as contacts. The conductive layer applied to the exposed structure contacts the exposed end of the resistive material. The patterning separates the portion of the conductive layer that contacts one end of the resistive material from the portion of the conductive layer that contacts the other end of the resistive material, forming a resistor that is significantly less than the conventional resistors described above. The length of the resistor is 1.2μ, and each side has a margin of 0.5μ due to a matching error, and compared with the conventional example which requires a linear distance of 4.4 to 4.6μ, according to the present invention. For example, the linear distance required to form one resistor is 2.
It becomes 0μ.

EXAMPLE The formation of a structure according to the present invention, as in the prior art structure, first forms a layer 12 of structural elements as described above with respect to FIGS. 1.1a and 1.1b. As shown in FIGS. 2.1a and 2.1b, undoped polycrystalline silicon preferably having a thickness of several hundred to several thousand Å and a resistance of several hundred megaΩ to several teraΩ per unit area. Layer 232 of high resistance material is layer 12
Formed on

As shown in FIGS. 2.2a and 2.2b, the layer 23 is patterned into a resistor structure 23p to define a width W of the target resistor and a length L larger than the target resistor. Formed on the exposed surface of this structure is an insulating layer 14 of silicon dioxide, preferably having a thickness of
Touch the exposed part of 2.

As shown in FIGS. 2.4a and 2.4b, a photoresist layer 25 is applied to the unpatterned insulating layer. A photoresist layer 25 is then patterned, as shown in FIGS.
p is left over the resistor region 23p to protect a final resistor length of preferably about 1.2μ. Photoresist protection area 25
p is patterned so as to have a width larger than the width of the resistance region 23p. Moderate alignment errors in the pattern of the photoresist protection region 25p do not adversely affect the final resistive structure dimensions determined by the intersection of the two patterns 23p, 25p.

As shown in FIGS. 2.6a and 2.6b, the photoresist protection region 25p functions as a mask for etching the insulating layer 14 and the resistance region 23p to form a structure including the resistor 23r and the insulating structure 14p. Although the surfaces 23a, 23b exposed by etching are shown vertically, in order to improve the coupling between the surfaces 23a, 23b and the contacts to be formed, both surfaces 23a, 23b
It is preferable that a and 23b have a gentler inclination than vertical. If the length occupied by the resistance increases because the slope of the slope is not too steep, it is preferable to make the slope considerably steep.

Next, as shown in FIGS. 2.7a and 2.7b, the photoresist protection region 25p is removed.

As shown in FIGS. 2.8a and 2.8b, a metallization layer is applied and patterned to form metallization regions 27a, 27b. The metallization layer 27a contacts the end 23a of the resistor 23r, and the metallization layer 27b contacts the end 23b of the resistor 23r.
The area of the contact regions 23a, 23b is on the order of 0.1-0.5 square μ, which is significantly smaller than the area of approximately 1.1 square μ of the conventional contact region described above with reference to FIGS. 1.1a-1.7b. Therefore, a resistance is added to the resistance by the contact itself. However, since the function of this element is resistance, resistance added to the contacts is acceptable.

The dimensions of the prior art and the present invention were compared using the same design criteria, especially the same optical resolution limit and the same alignment tolerance. Other dimensions are of course conceivable for other design criteria. It should be noted that the dimensions used in the description of the present specification are merely examples and do not limit the technical scope of the present invention.

The above-described resistor structure and its method of manufacture are advantageously used to form a resistor divider in which a plurality of adjacent resistors, in particular two adjacent resistors, have a contact therebetween. FIGS. 4 and 5 are plan views showing the conventional resistor divider and the resistor divider of the present invention, respectively, shown at the same scale as FIGS. 1.7a and 2.8a, respectively. The distance between the contact openings 46a and 46b or the distance between the contact openings 46b and 46c in FIG. 4 is determined by the contact openings 16a and 16a in FIG. 1.6a.
Same as the interval between 6b. Therefore, the distance between the contact lines 47a and 47b or between the contact lines 47b and 47c is the same as in FIG. 1.7a.

In contrast, according to the present invention, as shown in FIG. 5, there are no contact openings and the contacts are formed in a vertical or substantially vertical plane. The distance between the contact lines 57a and 57b or the distance between the contact lines 57b and 57c is the same as the distance between the contact lines 27a and 27b in FIG. 2.8a.

Using the same design criteria as described above, the total length of the conventional resistive divider of FIG. 4 is 8.6 microns, whereas the total length of the resistive divider of the present invention of FIG. 5 is 5.1 microns. Thus, the present invention is clearly advantageous. As will be apparent to those skilled in the art, the present invention can be implemented with various modifications and alterations to the above-described resistance structure within the technical scope thereof.

[Effects of the Invention] According to the present invention, since the contact points of the resistor are formed on both side surfaces of the resistor, there is almost no need to allocate the surface area to form the contact point on the resistor. Furthermore, the process of exposing the contact of the resistor is performed simultaneously with forming the resistor itself, thereby simplifying the manufacturing process. Also, according to the present invention, no doping of impurities is performed, so that there is no need to allocate space for lateral diffusion of the implanted region under the protective mask.

[Brief description of the drawings]

1.1a to 1.7a are plan views showing respective successive steps of forming a conventional resistor. Figures 1.1b to 1.7b correspond to Figures 1.1a to 1.7a, respectively.
It is sectional drawing which shows each process which forms the conventional resistance of the figure. FIGS. 2.1a to 2.8a are plan views showing respective successive steps for forming the resistor of the present invention. FIGS. 2.1b to 2.8b are cross-sectional views showing respective successive steps of forming the resistor of the present invention. FIG. 3 is a circuit diagram showing a typical memory cell having a resistor formed using the method and structure of the prior art or the method and structure of the present invention. FIG. 4 is a plan view showing a prior art resistor divider network. FIG. 5 is a plan view showing a resistor divider network formed according to the present invention. 11 ... substrate, 12 ... layer 13 ... polycrystalline silicon layer 13 p ... resistor structure, 13 r ... resistor 14 ... protective layer, 14 p ... mask 15 a, 15 b ... doped region 16 a, 16 b ... contact opening 17: conductive layer, 17a, 17b: conductive line 23: polycrystalline silicon layer 23a, 23b: plane, 23p: resistance structure 23r: resistance, 25: photoresist layer 25p: protection area 27a, 27b Metallized areas 46a, 46b, 46c Contact openings 47a, 47b, 47c Contact lines 57a to 57c Contact lines

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/822

Claims (4)

(57) [Claims] 1. A resistance element for use in an integrated circuit, comprising: a resistor formed on an insulating layer formed on a semiconductor substrate and having an upper surface, side surfaces, and an end surface extending upward. An insulating material formed on the resistance layer, covering the upper surface and the side surfaces of the resistance layer, and having a side surface extending upward in alignment with the end surface of the resistance layer; A conductive contact provided opposite to the end face of the layer. 2. The resistance element according to claim 1, wherein said conductive contact is separated from said upper surface and side surfaces of said resistance layer by said insulating material. 3. The resistance element according to claim 1, wherein said end surface of said resistance layer and said side surface of said insulating material are substantially vertical. 4. A method of forming a resistive element on a semiconductor horizontal plane, comprising forming a resistive material on an insulating horizontal structure layer above the semiconductor horizontal plane, and wherein the portion of the resistive material has a final resistance. Patterning the resistive material to have an element width; forming an insulating material on the resistive material; patterning the resistive material and the insulating material using a single mask; Forming a first and a second exposed surface of the resistive material extending upward thereby; and opposing the two exposed surfaces of the insulating material and the resistive material and the insulating horizontal structure layer. Forming a conductive layer; a first separated conductive region in contact with the first exposed surface;
Patterning said conductive layer to form at least two separate conductive regions, said second conductive region being in contact with said exposed surface.