JP3160180B2 - Data transfer device and data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transfer device and a data transfer method for transferring data with low power consumption.

[0002]

^2. Description of the Related Art Dynamic power consumption (P) in a data transfer line is generally represented by P = fCV ² . Here, f is the number of times of charging and discharging, C is the magnitude of the load capacity, and V is the voltage applied to the load capacity. In an integrated circuit that performs data processing, a bus structure is often employed as a data transfer line in order to simplify the internal structure. However, since the bus is long and many resources are connected to the bus, the load capacity of the bus is often large. This leads to an increase in power consumption.

Japanese Patent Laying-Open No. 4-128914 discloses a data transfer device for reducing the load capacity of an internal bus. In the data transfer device, the internal bus is separated into a main data bus and an input / output data bus, and the main data bus and the input / output data bus are used only when outputting data outside the integrated circuit. Connected via

[0004]

However, the load capacity of the external bus is much larger than that of the internal bus. The line width of the internal bus of the integrated circuit is of the order of μm and its length is of the order of mm, whereas the line width of the external bus connected to the terminals of the integrated circuit is of the order of mm and its length is in cm. Because it is an order. Therefore, in an integrated circuit of a type that requires data transfer to the outside of the integrated circuit, the power consumed at the terminal portion becomes extremely large. As described above, there is a problem that a significant reduction in power consumption cannot be expected only by reducing the load capacity of the internal bus.

In view of the above problems, an object of the present invention is to provide a data transfer device and a data transfer method for transferring data with low power consumption.

[0006]

A data transfer device according to the present invention is a data transfer device connected to a bus and a control signal line, and outputs the data to the bus without processing the data. A determination means for determining whether or not a change in the state of the bus that occurs when the processed data is output to the bus is smaller than a change in the state of the bus that occurs in the bus; , According to the determination result,
A first processing means for processing the data by changing the bit order; and one of the data and the data processed by the first processing means according to the determination result.
A first output means for selectively outputting one to the bus, and a second output means for outputting a control signal indicating the determination result to the control signal line, thereby achieving the above object.

[0007] The determining means includes a first holding means for holding a previous determination result, a second holding means for holding previous data when receiving current data, a result of the previous determination and the data of the previous data. Determining means for determining whether or not to process the current data according to the current data and the current data.

[0008]

The determining means outputs a number of patterns corresponding to a relationship between the current data and the previous data among a predetermined number of patterns prepared in advance according to the result of the previous determination. The image processing apparatus may further include a detection unit, and a unit that outputs a signal indicating whether or not to process the current data in accordance with an output of the pattern detection unit.

[0010] The determination means may include a determination means for determining whether or not to process the current data according to the current state of the bus and the current data.

[0011]

The determining means outputs a number of patterns corresponding to a relationship between a current state of the bus and the current data among a predetermined number of patterns prepared in advance; Means for outputting a signal indicating whether or not to process the current data according to the output of the means.

[0013] The data may be a part of data supplied to the data transfer device via an entire bus, and a bit width of the bus may be smaller than a bit width of the entire bus.

[0014]

The data transfer device receives the data output from the first output means via the bus, and receives a control signal indicating the determination result output from the second output means via the control signal line. And a second processing means for processing the data by changing the bit order according to the control signal.

[0016]

[0017] Another data transfer device of the present invention includes a transmitting unit that transmits data and a control signal, and is connected to the transmitting unit.
A bus for carrying the data, a control signal line connected to the transmitting unit for carrying the control signal, and a bus connected to the bus and the control signal line for receiving the data via the bus and receiving the control signal; A receiving unit for receiving the control signal via a line,
The transmitting unit, based on a change in the state of the bus that occurs when the data is output to the bus without processing the data,
Determining means for determining whether or not a change in the state of the bus that occurs when the processed data is output to the bus by processing the data; and determining a bit order according to the determination result. A first processing means for processing the data by replacing the data, and selectively outputting one of the data and the data processed by the first processing means to the bus according to the determination result. A first output unit for outputting a control signal indicating the determination result to the control signal line;
Output means for receiving the data output from the first output means via the bus, and controlling the control signal indicating the determination result output from the second output means to the control means. Received via a signal line, and according to the control signal,
A second processing means for processing the data by changing the bit order is provided, thereby achieving the above object.

[0018] The determination means of the transmission unit includes a first holding means for holding a previous determination result, a second holding means for holding the previous data when receiving current data, A determination unit may be provided for determining whether or not to process the current data according to the previous data and the current data.

[0019] The determination means of the transmission unit may include a determination means for determining whether or not to process the current data according to a current state of the bus and current data. The data transfer method of the present invention outputs the processed data to the bus by processing the data based on a change in the state of the bus that occurs when the data is output to the bus without processing the data. Then, it is determined whether or not the change in the state of the bus that occurs in the case is smaller, and the data is processed by changing the bit order according to the result of the determination. The processed data is transferred accordingly. Thereby, the above object is achieved.

[0020]

The data may be reproduced by performing a processing reverse to the processing of the data according to the determination result.

[0022]

[0023]

According to the data transfer apparatus and the data transfer method of the present invention, data processed by processing data is obtained from a change in the state of the bus that occurs when data is output to the bus without processing the data. It is determined whether or not the change in the state of the bus that occurs when is output to the bus is smaller.

The data is processed according to the result of the determination. Further, according to the determination result, either the unprocessed data or the processed data is selectively output to the bus. As a result, a change in the state of the bus due to data transfer can be reduced. As a result, the power consumed in the bus is reduced.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described with reference to FIG. The unit 801 and the unit 802 are connected to the wiring 8
Suppose that data consisting of a plurality of bits are transferred from the unit 801 to the unit 802 via the wiring 803. Since the wiring 803 has a load capacity, charge and discharge occur due to such data transfer. As a result, power is consumed. For example, b '
After transferring 10101010 (hereinafter, b ′ indicates a binary number) from the unit 801 to the unit 802 via the wiring 803, b′01010101 is transferred to the wiring 80
In the case where the data is transferred from the unit 801 to the unit 802 via the line 3, the power consumption by the wiring 803 becomes maximum.
This is because charging and discharging occur in all bits of the wiring 803 because all bits of the transfer data are inverted. The present invention provides b ′
Provided is a data transfer device and a data transfer method for transferring data obtained by processing this data instead of transferring data of “01010101” and information indicating that true data is obtained by processing this data. I do. For example, in the data transfer apparatus and the data transfer method according to the present invention, instead of transferring the data b'01010101, b'1
Data of 0101010 and 1-bit information indicating that true data is bit-inverted of this data are transferred. As a result, power consumption by the bus 803 is minimized. This is because the state of each bit of the wiring 803 does not change before and after data transfer.

Data processing is not limited to bit inversion. In this specification, “data processing” includes bit inversion, replacement of bit order or data compression / expansion, or a combination thereof, and any processing as long as the processing reduces the state change of the wiring 803. Including.

The wiring 803 may be an internal bus or an external bus. However, as described above, since the external bus has much larger load capacity than the internal bus, the present invention is particularly effective when the wiring 803 is an external bus. When the unit 801 and the unit 802 are included in one integrated circuit, the wiring 803 is called an internal bus. When the unit 801 is included in an integrated circuit and the unit 802 is included in an integrated circuit different from the integrated circuit, the wiring 803 is called an external bus. FIG.
4 shows a procedure of a data transfer method according to the present invention.

In step S1, the data processed and output to the bus is output from the bus state change (SC1) that occurs when the data is output to the bus without processing the data. It is determined whether the state change (SC2) that occurs in this case is smaller.

If it is determined in step S1 that the bus state change (SC2) is smaller than the bus state change (SC1), the data is processed (step S1).
2) The processed data is output to the bus (Step S)
3) Information (for example, b′1) indicating the result of the determination in step S1 is output to the control signal line (step S4).

If it is determined in step S1 that the bus state change (SC2) is equal to or greater than the bus state change (SC1), the data is output to the bus without processing (step S3). Information (for example, b'0) indicating the result of the determination in S1 is output to the control signal line (step S4).

The order of steps S3 and S4 may be reversed.

(First Embodiment) FIG. 3 shows the configuration of a first embodiment of the data transfer device according to the present invention. The data transfer device includes an integrated circuit 101 and an integrated circuit 113. The integrated circuit 101 is connected to the external bus 1 via a terminal 111.
19 and to a signal line 120 via a terminal 112. The integrated circuit 113 is connected to the external bus 119 via a terminal 114, and the signal line 12 is connected via a terminal 115.
Connected to 0. The external bus 119 is, for example, an 8-bit bus. The signal line 120 is, for example, a 1-bit signal line.

The integrated circuit 101 includes an internal bus 102, an output latch 103, a determination unit 10, and a logic inversion circuit 108.
, A terminal driving circuit 109, a terminal driving circuit 110, and a data processing circuit 201.

The internal bus 102 is a bus provided inside the integrated circuit 101 for transferring data.

The output latch 103 is connected to the internal bus 102 and temporarily holds data to be output to the outside of the integrated circuit 101. The output latch 103 is, for example, an 8-bit latch. The output latch 103 has an internal bus 102
, Data is provided from the data processing circuit 201, for example.

The judging section 10 outputs the data whose logical level has been inverted to an external signal based on a state change of the external bus 119 which occurs when the data is output to the external bus 119 without inverting the logical level of the data. It is determined whether or not the change in state of the external bus 119 that occurs when the signal is output to the bus 119 is smaller, and a determination signal 107 indicating the determination result is output. The determination unit 10 is configured to store the temporary latch 1
04, an unmatched number detection circuit 105, and a determination circuit 106.

The temporary latch 104 is the output latch 1
Each time new data is written to the data latch circuit 03, the data latched in the output latch 103 is latched.
The temporary latch 104 is, for example, an 8-bit latch.

The mismatched number detection circuit 105 compares the output of the output latch 103 and the output of the temporary latch 104 bit by bit, and determines whether the output of the output latch 103 and the output of the temporary latch 104 do not match. Output the number.

The determination circuit 106 is provided with the mismatched number detection circuit 1
05 and the previous self output, the judgment signal 10
7 is output. The operation of the determination circuit 106 will be described later.

The logic inversion circuit 108 outputs the output latch 10 according to the judgment signal 107 output from the judgment circuit 106.
Process the output of 3. When the determination signal 107 is logic 1, the logic inversion circuit 108 inverts the logic level of the output of the output latch 103. When the determination signal 107 is logic 0, the logic inversion circuit 108
The output of No. 3 is passed as it is.

The terminal drive circuit 109 includes the logic inversion circuit 10
The terminal 111 is driven in order to output the output 8 to the outside of the integrated circuit 101. The terminal drive circuit 110 outputs the determination signal 107 output from the determination circuit 106 to the integrated circuit 101
The terminal 112 is driven to output to the outside of the terminal.

The integrated circuit 113 includes a logical inversion circuit 116
, An internal bus 117, and a data processing circuit 202.

The logic inversion circuit 116 receives the 8-bit signal via the terminal 114, and processes the 8-bit signal according to the logic level of the terminal 115. Terminal 115
Is at 1, the logical inversion circuit 116
Inverts the logical level of the 8-bit signal. When the logic level of the terminal 115 is 0, the logic inversion circuit 116 passes the 8-bit signal as it is.

The internal bus 117 is a bus provided inside the integrated circuit 113 for transferring data. The output of the logic inversion circuit 116 is sent via the internal bus 117
For example, it is provided to the data processing circuit 202.

FIG. 4 shows logic defining the operation of the decision circuit 106. As shown in FIG. 4, the operation of the determination circuit 106 is defined according to cases A, B, C, and D, respectively. For example, case A is a case where the determination circuit 106 outputs a determination signal 107 that is 0 in the previous determination, and the mismatched number detection circuit 105 determines 0, 1,
Judgment circuit 106 when any one of 2 and 3 is output
The operation of FIG. In this case, the determination circuit 106 outputs the same determination signal 107 as the previous determination signal 107 as the current determination signal 107. In case B, the judgment circuit 10
6 is a case where the judgment signal 107 which is 0 in the previous judgment is outputted, and the judgment circuit 106 in the case where the mismatched number detection circuit 105 outputs any of 4, 5, 6, 7 and 8 in the present judgment. The operation is shown. In this case, the determination circuit 106 outputs a determination signal that is 1 different from the previous determination signal 107 as the current determination signal 107. Case C
Case D indicates the relationship between the output of the mismatched number detection circuit 105 and the current determination signal 107 when the determination circuit 106 outputs the determination signal 107 of 1 in the previous determination.

FIG. 5 shows an example of the operation of the data transfer device of the first embodiment in a time series. Hereinafter, how the data transfer device operates at each of the times 1, 2, 3, 4, and 5 shown in FIG. 5 will be described.

Time 1) At time 1, the output latch 10
It is assumed that b′10101010 is stored in 3 and the determination signal 107 is 0. The output of the output latch 103 passes through the logic inversion circuit 108. As a result, the terminal drive circuit 109 drives the external bus 119 with a value of b'10101010.

The determination signal 107 of 0 is output from the terminal driving circuit 1
10, the integrated circuit 11 via the terminal 112 and the terminal 115
It is conveyed inside 3. Since the logic inversion circuit 116 does not cause an inversion operation, the signal on the external bus 119 is
14 through the logic inversion circuit 116 and the internal bus 1
It is conveyed to 17. Thus, the output latch 103
Is output to the internal bus 117.

Time 2) At time 2, the output latch 10
3 is written with b′10101000 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
03 is stored. The mismatched number detection circuit 105 compares the output b'10101000 of the output latch 103 and the output b'10101010 of the temporary latch 104 bit by bit, and
Is output. The value 1 is the output b′10 of the output latch 103.
101000 and the output b′10 of the temporary latch 104
Indicates the number of bits that do not match with 101010. The determination circuit 106 determines that the current state corresponds to case A in FIG. 4 and outputs a determination signal 107 of 0.

The output of the output latch 103 passes through the logic inverting circuit 108, and the terminal driving circuit 109 outputs b'1010
The external bus 119 is driven with a value of 1000. Since the state of the external bus 119 at time 1 is b'10101010, the state of the external bus 119 changes by one bit by the output of b'10101000 at this time. as a result,
Power corresponding to a one-bit state change is consumed.

The determination signal 107 of 0 is output from the terminal drive circuit 1
10, the integrated circuit 11 via the terminal 112 and the terminal 115
It is conveyed inside 3. Since the logic inversion circuit 116 does not cause an inversion operation, the signal on the external bus 119 is
14 through the logic inversion circuit 116 and the internal bus 1
It is conveyed to 17. Thus, the output latch 103
Is output to the internal bus 117.

Time 3) At time 3, the output latch 10
3 is written with b′00110011 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
03 'stored in b'10101000. The mismatched number detection circuit 105 compares the output b′00110011 of the output latch 103 with the output b′10101000 of the temporary latch 104 for each bit, and obtains the value 5
Is output. The value 5 is the output b'00 of the output latch 103.
110011 and the output b′10 of the temporary latch 104
Indicates the number of bits that do not match between 101000. The determination circuit 106 determines that the current state corresponds to case B in FIG. 4 and outputs a determination signal 107 of 1.

The output of the output latch 103 is inverted by the logic inversion circuit 108. As a result, the terminal drive circuit 1
09 drives the external bus 119 with a value of b'11001100. The state of the external bus 119 at time 2 is b'10
B'1100110
The output of 0 changes the state of the external bus 119 by 3 bits. As a result, power corresponding to the 3-bit state change is consumed.

The determination signal 107 of 1 is output from the terminal drive circuit 1
10, the integrated circuit 11 via the terminal 112 and the terminal 115
It is conveyed inside 3. Since the logic inversion circuit 116 performs an inversion operation, the signal on the external bus 119 is inverted by the logic inversion circuit 116 via the terminal 114, and the inverted signal is transmitted to the internal bus 117. Thus, b'0011001 stored in output latch 103
1 is output to the internal bus 117.

The content of output latch 103 at time 3 changes by 5 bits compared to the content of output latch 103 at time 2. However, the state change of the external bus 119 is 3 bits, and even if the state change of the signal line 120 from 0 to 1 is applied, only a 4-bit state change occurs.

Time 4) At time 4, the output latch 10
3 is written with b′10101011 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
03 is stored. The mismatched number detection circuit 105 compares the output b′10101111 of the output latch 103 with the output b′00110011 of the temporary latch 104 for each bit, and obtains the value 3
Is output. The value 3 is the output b′10 of the output latch 103.
101011 and output b′00 of temporary latch 104
This indicates the number of bits that do not match with 110011. The determination circuit 106 determines that the current state corresponds to case C in FIG. 4 and outputs a determination signal 107 of 1.

The output of the output latch 103 is inverted by the logic inversion circuit 108. As a result, the terminal drive circuit 1
09 drives the external bus 119 with a value of b'01010100. The state of the external bus 119 at time 3 is b'11
001100, so this b'0101010
The output of 0 changes the state of the external bus 119 by 3 bits. As a result, power corresponding to the 3-bit state change is consumed.

The determination signal 107 of 1 is output from the terminal drive circuit 1
10, the integrated circuit 11 via the terminal 112 and the terminal 115
It is conveyed inside 3. Since the logic inversion circuit 116 performs an inversion operation, the signal on the external bus 119 is inverted by the logic inversion circuit 116 via the terminal 114, and the inverted signal is transmitted to the internal bus 117. Thus, b′1010101 stored in output latch 103
1 is output to the internal bus 117.

Time 5) At time 5, the output latch 10
3 is written with b′01010000 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104 stores b'10101011 previously stored in the output latch. The mismatched number detection circuit 105 compares the output b'01010000 of the output latch 103 with the output b'10101111 of the temporary latch 104 for each bit, and outputs the value 7. The value 7 is the output b'0101 of the output latch 103.
0000 and the output b′1010 of the temporary latch 104
Indicates the number of bits that do not match with 1011. The determination circuit 106 determines that the current state corresponds to case D in FIG. 4, and outputs a determination signal 107 of 0.

The output of the output latch 103 passes through the logical inversion circuit 108, and the terminal drive circuit 109 outputs b'0101
The external bus 119 is driven with a value of 0000. Since the state of the external bus 119 at time 4 is b'01010100, the state of the external bus 119 changes by one bit by the output of b'01010000 at this time. as a result,
Power corresponding to a one-bit state change is consumed.

The determination signal 107 of 0 is output from the terminal drive circuit 1
10, the integrated circuit 11 via the terminal 112 and the terminal 115
It is conveyed inside 3. Since the logic inversion circuit 116 does not cause an inversion operation, the signal on the external bus 119 is
14 through the logic inversion circuit 116 and the internal bus 1
It is conveyed to 17. Thus, the output latch 103
Is output to the internal bus 117.

The content of output latch 103 at time 5 changes by 7 bits compared to the content of output latch 103 at time 4. However, the state change of the external bus 119 is one bit, and even if a state change of the signal line 120 from 1 to 0 is applied, only a 2-bit state change occurs.

FIG. 6 shows an example of the circuit configuration of the mismatched number detection circuit 105 and the determination circuit 106. The mismatched number detection circuit 105 includes, for example, the exclusive OR circuits 401 to
408. The exclusive OR circuits 401 to 408 detect a bit-by-bit mismatch between the output of the output latch 103 and the output of the temporary latch 104. The determination circuit 106 is realized by, for example, a programmable logic array 409 and a flip-flop 410. The programmable logic array 409 and the flip-flop 410 implement the logic shown in FIG. The flip-flop 410 outputs the previous judgment signal 1
07 is held.

As described above, in the data transfer device of the first embodiment, the determination circuit 106 determines which of the cases A to D in FIG. 4 corresponds to the current state, and indicates the determination result. The determination signal 107 is output. Logic inversion circuit 10
8 processes the output of the output latch 103 according to the logic level of the determination signal 107. When the logic level of the determination signal 107 is 1, the output of the output latch 103 is inverted by the logic inversion circuit 108 and the inverted signal is output to the external bus 119. When the logic level of the determination signal 107 is 0, the output of the output latch 103 is output to the external bus 119 without being inverted. Thus, the change in the state of the external bus 119 can be reduced. As a result, the power consumed by the external bus 119 can be reduced.

In this embodiment, only the logical inversion processing is performed on the output of the output latch 103 in order to reduce the change in the state of the external bus 119.
The output of No. 3 may be subjected to a bit order change process. Alternatively, the bit order changing process and the logical inversion process may be used together. Combination with other processing is also possible.

In order to realize these processes, the mismatched number detection circuit 105, the judgment circuit 106, the logical inversion circuit 1
08 and the like are newly required. However, the increase in power consumption due to these additional circuits is small. This is because the additional circuit is provided in the integrated circuit, and the processing is only a logical operation such as bit inversion and permutation of the bit order. In addition, comparing the increase in power consumption due to the additional circuit with the reduction in power consumption due to the reduction in the state change of the external bus 119, the latter is much larger. In particular, the external bus 11
This tendency becomes remarkable when the bit width of 9 is large.

Next, the effect of the data transfer device of the first embodiment will be described more specifically.

FIG. 7 shows the number of bits whose state has changed on external bus 119 when data is transferred by the conventional data transfer device. Here, the conventional data transfer device refers to a data transfer device that transfers 8-bit data without performing a bit inversion operation. From time n to time n + 5, 2, 4, -1,-in decimal notation
It is assumed that data 2, 3, and -2 are sequentially transferred from the integrated circuit 101 to the integrated circuit 113 via the external bus 119. Here, the negative data is expressed in a two's complement system. In the case where the negative data is expressed in the two's complement system as described above, when the data changes from a positive number to a negative number or when the data changes from a negative number to a positive number, the external bus 11 is used.
The number of bits whose state has changed on 9 becomes large. This is because the upper bits of the data change significantly. As a result, a large amount of power is consumed in the external bus 119.

FIG. 8 shows the number of bits whose state has changed on the terminals 111 and 112 when data is transferred by the data transfer device of the first embodiment. From time n to time n + 5, 2, 4 in decimal notation,
It is assumed that the data -1, -2, 3, and -2 are sequentially transferred from the integrated circuit 101 to the integrated circuit 113 via the external bus 119. Here, the negative data is expressed in a two's complement system. According to the data transfer device of the first embodiment, the data is bit-inverted so that the state change of the terminals 111 and 112 is reduced. Thus, the number of bits whose states have changed on the terminals 111 and 112 can be significantly reduced. As a result, power consumed at the terminals 111 and 112 can be reduced.

In this example, the bit width of the data is 8 bits. As the bit width increases, the effect of reducing the power consumption by the data transfer device of the first embodiment increases. This is because the larger the bit width is, the larger the number of changes of the upper bits of the data when the data changes from a positive number to a negative number or when the data changes from a negative number to a positive number.

FIG. 9 is a circuit diagram showing the configuration of the integrated circuit 101 to the integrated circuit 11.
3 shows the effect of reducing the power consumption by the data transfer device of the first embodiment when the data transferred via the external bus 119 is random 8-bit data. For example, when the transfer data is an instruction code of a computer, the 8-bit bit pattern may be considered to occur statistically at random.

In FIG. 9, case 1 shows a case where the number of matching bits between two consecutive transfer data is 1 (ie, the number of mismatching bits is 7). The number of cases in which case 1 occurs is eight. This is because the number of combinations to select one from _eight is ₈ C ₁ = 8. Therefore, the probability that case 1 will occur is 8/256 =
0.031.

Therefore, in case 1, the average number of changed bits by the conventional data transfer device is 7
X Probability 0.031 = 0.219. Here, the conventional data transfer device refers to a data transfer device that transfers 8-bit data without performing a bit inversion operation regardless of case 0 to case 8. On the other hand, the average number of changed bits by the data transfer device of the first embodiment is 1 in the number of mismatch bits × the probability of occurrence 0.031 = 0.031 because the data is inverted and transferred in this case. As described above, according to the data transfer device of the first embodiment, in case 1, the average number of change bits can be reduced by 86%.

When the average number of changed bits is summed up for Cases 0 to 8, the average number of changed bits by the conventional data transfer device is four. On the other hand, the average number of changed bits by the data transfer device of the first embodiment is 2.906. That is, the terminal 111 has changed by an average of 2.906 bits per transfer. Further, when the state change of the terminal 112 is considered, the average number of changed bits as a whole is 2.906 + 0.363 = 3.269. In cases 0 to 3, the state of the terminal 112 changes.
When the average number of change bits of the terminal 112 is (1 + 8 + 28 + 5)
6) /256=0.363. That is, the terminals 111 and 112 change on average 3.269 bits per transfer. Thus, according to the data transfer device of the first embodiment, the average number of changed bits as a whole can be reduced by 18%. By reducing the average number of change bits as a whole, the terminal 111 and the terminal 11
2 can reduce the power consumed.

(Second Embodiment) FIG. 10 shows the configuration of a data transfer device according to a second embodiment of the present invention. 10, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

The configuration of the data transfer device of the second embodiment is as follows.
This is effective when the state of the external bus 119 is maintained until the next data is written to the output latch 103.

In the second embodiment, the mismatched number detection circuit 5
05 and the determination circuit 506 function as the determination unit 50.
The judging unit 50 outputs the data whose logical level has been inverted to the external bus 119 based on a change in the state of the external bus 119 that occurs when the data is output to the external bus 119 without inverting the logical level of the data. It is determined whether or not the change in the state of the external bus 119 that occurs when the signal is output is smaller, and a determination signal 107 indicating the determination result is output.

The mismatched number detection circuit 505 compares the output of the output latch 103 and the state of the external bus 119 bit by bit, and determines whether the output of the output latch 103 and the state of the external bus 119 do not match. Output the number. The determination circuit 506 outputs a determination signal 107 according to the output of the mismatched number detection circuit 505.

FIG. 11 shows logic defining the operation of the decision circuit 506. As shown in FIG.
The operation of No. 6 is defined according to cases A and B, respectively. In case A, the number of mismatch detection circuit 505 is 0,
Judgment circuit 5 when one of 1, 2, and 3 is output
06 is shown. In this case, the judgment circuit 506
Outputs a determination signal of 0 as the current determination signal 107. In case B, the number-of-mismatches detection circuit 505 is 4,
The operation of the determination circuit 506 when any one of 5, 6, 7, and 8 is output is shown. In this case, the judgment circuit 50
6 outputs the determination signal of 1 as the current determination signal 107.

Next, the operation of the data transfer device according to the second embodiment will be described.

When data to be output to the external bus 119 is written to the output latch 103, the mismatched number detection circuit 505
Compares the output of the output latch 103 with the state of the external bus 119 bit by bit, and outputs the number of bits that do not match between the output of the output latch 103 and the state of the external bus 119. The determination circuit 506 includes the mismatched number detection circuit 50.
5 and outputs a decision signal 107 according to the logic shown in FIG. For example, the output of the output latch 103 is b′10101010 and the external bus 1
Assume that state 19 is b'10101000.
In this case, the mismatched number detection circuit 505 outputs the output latch 1
03 is compared with the state b'10101000 of the external bus 119 bit by bit, and the value 1 is output. The value 1 is the output b'101 of the output latch 103.
01010 and state b′1010100 of the external bus 119
Indicates the number of bits that do not match with zero. Judgment circuit 50
No. 6 determines that the current state corresponds to case A in FIG. 11 and outputs a determination signal 107 of 0. Output latch 10
Assume that the output of No. 3 is b'10101010 and the state of the external bus 119 is b'00000000. In this case, the mismatched number detection circuit 505 outputs the output b′10101010 of the output latch 103 and the external bus 119.
Is compared bit by bit with the state b′00000000, and the value 4 is output. The value 4 is the output b′1 of the output latch 103.
0101010 and state b'0000 of external bus 119
000 indicates the number of bits that do not match. The determination circuit 506 determines that the current state corresponds to case B in FIG. 11 and outputs a determination signal 107 of 1. Subsequent operations of the data transfer device are the same as in the first embodiment, and a description thereof will be omitted.

FIG. 12 shows an example of the operation of the data transfer device of the second embodiment in a time series. FIG. 12 shows time points 1, 2,
The relationship between the data output from the output latch 103 and the state change of the external bus 119 in each of 3, 4, and 5 is shown.

FIG. 13 shows an example of the circuit configuration of the mismatched number detection circuit 505 and the determination circuit 506. The mismatched number detection circuit 505 is, for example, an exclusive OR circuit 401.
To 408. The exclusive OR circuits 401 to 408 detect a bit-by-bit mismatch between the output of the output latch 103 and the state of the external bus 119. The determination circuit 506 is realized by, for example, the programmable logic array 709. The programmable logic array 709 implements the logic shown in FIG.

As described above, in the data transfer device of the second embodiment, the determination circuit 506 determines whether the current state corresponds to case A or B in FIG. 11 and indicates the determination result. The determination signal 107 is output. The logic inversion circuit 108 processes the output of the output latch 103 according to the logic level of the determination signal 107. When the logic level of the determination signal 107 is 1, the output of the output latch 103 is inverted by the logic inversion circuit 108 and the inverted signal is output to the external bus 119. When the logic level of the determination signal 107 is 0, the output of the output latch 103 is output to the external bus 119 without being inverted. Thus, the change in the state of the external bus 119 can be reduced. As a result, the power consumed by the external bus 119 can be reduced.

Further, in this embodiment, in order to reduce the change in the state of the external bus 119, only the logical inversion processing is performed on the output of the output latch 103. Output latch 103
May be subjected to a bit order change process. Alternatively, the bit order changing process and the logical inversion process may be used together. Combination with other processing is also possible.

In order to realize these processes, the mismatched number detection circuit 105, the judgment circuit 106, the logical inversion circuit 1
08 and the like are newly required. However, the increase in power consumption due to these additional circuits is small. This is because the additional circuit is provided in the integrated circuit, and the processing is only a logical operation such as bit inversion and permutation of the bit order. In addition, comparing the increase in power consumption due to the additional circuit with the reduction in power consumption due to the reduction in the state change of the external bus 119, the latter is much larger. In particular, the external bus 11
This tendency becomes remarkable when the bit width of 9 is large.

Further, the circuit shown in FIG. 10 may be provided in each of the integrated circuits other than the integrated circuit 101 so that the integrated circuits other than the integrated circuit 101 output data to the external bus 119. With such a configuration, the power consumed by the external bus 119 as a whole system can be reduced. When such a configuration is adopted, a three-state bus is usually used as the external bus 119. When the external bus 119 is a three-state bus, the contents of the bus are held for a while by being in a high impedance state. Therefore, the mismatched number detection circuit 505 can easily monitor the state of the external bus 119.

The same effect as that already described with reference to FIGS. 7 to 9 can also be obtained by the data transfer device of the second embodiment.

(Third Embodiment) FIG. 14 shows the configuration of a third embodiment of the data transfer device according to the present invention. The data transfer device includes an integrated circuit 1201 and an integrated circuit 1205.

The integrated circuit 1201 has a 16-bit overall bus 1202, an integrated circuit 1203 and an integrated circuit 1204. The configuration of the integrated circuit 1203 is the internal bus 1
The configuration is the same as the configuration of the integrated circuit 101 shown in FIGS. 3 and 10 except that 02 is connected to the upper 8 bits of the entire bus 1202. The configuration of the integrated circuit 1204 is the same as that of the integrated circuit 10 shown in FIGS. 3 and 10 except that the internal bus 102 is connected to the lower 8 bits of the overall bus 1202.
1 is the same as that of FIG.

The integrated circuit 1205 has a 16-bit overall bus 1206, an integrated circuit 1207 and an integrated circuit 1208. The configuration of the integrated circuit 1207 is the internal bus 1
The configuration is the same as that of the integrated circuit 113 shown in FIG. 3 and FIG. 10 except that 17 is connected to the upper 8 bits of the entire bus 1206. The configuration of the integrated circuit 1208 is the same as that of the integrated circuit 11 shown in FIGS. 3 and 10 except that the internal bus 117 is connected to the lower 8 bits of the entire bus 1206.
3 is the same as that of FIG.

Next, the operation of the data transfer device having the above configuration will be described. The upper 8 bits of the 16-bit data transferred via the entire bus 1202 are transferred from the integrated circuit 1203 to the integrated circuit 1207. The lower 8 bits of the 16-bit data transferred via the entire bus 1202 are transmitted from the integrated circuit 1204 to the integrated circuit 1208.
Is forwarded to From the integrated circuit 1203 to the integrated circuit 1207
Transfer operation from the integrated circuit 1204 to the integrated circuit 120
8 is the same as the transfer operation already described with reference to FIGS. 3 and 10, and the description thereof is omitted here. 8-bit data output from the internal bus 117 of the integrated circuit 1207 and the internal bus 11 of the integrated circuit 1208
The 8-bit data output from 7 is output from the entire bus 1206 as one 16-bit data.

FIG. 15 shows the effect of reducing power consumption by the data transfer device of the third embodiment. As shown in FIG. 15, when the average number of change bits is summed up for case 0 to case 16, the average number of change bits becomes 8 when 16-bit data is transferred by the conventional data transfer device. Here, the conventional data transfer device is defined as cases 0 to 0.
This refers to a data transfer device that transfers 16-bit data without performing a bit inversion operation regardless of case 16.

On the other hand, when 16-bit data is transferred by the data transfer device of the first embodiment or the second embodiment, the average is calculated by the same calculation as that already described with reference to FIG. The number of bit changes is 6.429. Further, when the state change of the signal line 120 is considered, the average number of bit changes as a whole is 6.429 + 0.402 = 6.
831.

When 16-bit data is divided into two 8-bit data and transferred by the data transfer device of the third embodiment, the average number of bit changes is equal to the data of the first or second embodiment. It is obtained by doubling the average bit change number 3.269 when 8-bit data is transferred by the transfer device. That is, the average bit change number is 6.538.

As described above, according to the data transfer apparatus of the third embodiment, the average number of changed bits can be reduced by 18% as compared with the case where 16-bit data is transferred by the conventional data transfer apparatus. The average number of changed bits can be reduced by 4% as compared with the case where 16-bit data is transferred by the data transfer device of the first embodiment or the second embodiment. By reducing the average number of bit changes, the power consumed on the bus connecting the integrated circuits 1201 and 1205 is reduced.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the data transfer device according to the present invention will be described. The data transfer device according to the fourth embodiment is an example of a data transfer device that reduces power consumption by changing the bit order.

FIG. 16 shows the principle of reducing the power consumption by changing the bit order when two data are successively transferred. It is assumed that 2-bit data (d0, d1) is transferred. When the bit order of the data (d0, d1) is not changed, the data (d0, d1) is transferred, and when the bit order of the data (d0, d1) is changed, the data (d1, d0) is transferred. You.

For example, in case g, the previous transfer data is (0,1) and the current transfer data is (1,1).
0). In case g, the number of bit state changes when the bit order is changed is smaller than the number of bit state changes when the bit order is not changed. Therefore, the effect of power consumption reduction can be obtained by changing the bit order. Case j is a case where the previous transfer data is (1, 0) and the current transfer data is (0, 1). In case j, the number of bit state changes when the bit order is changed is smaller than the number of bit state changes when the bit order is not changed. Therefore, the effect of power consumption reduction can be obtained by changing the bit order.

FIG. 17 shows the configuration of a fourth embodiment of the data transfer device according to the present invention. The data transfer device of the fourth embodiment is based on the above-described principle of reducing power consumption by changing the bit order. 17, components that are the same as the components shown in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted.

The determination unit 1500 can determine the 8-bit data (d7, d6, d5, d4, d4) without changing the bit order.
From the state change of the external bus 119 that occurs when d3, d2, d1, d0) are output to the external bus 119, the 8-bit data (d6, d7, d4, d5, with the bit order changed every two adjacent bits). d2, d3, d0, d1)
External bus 1 generated when the external bus 119 is output to the external bus 119
It is determined whether or not the state change of 19 is smaller, and a determination signal 1507 indicating the determination result is output. Judgment unit 150
0 is the temporary latch 104 and the pattern detection circuit 15
05 and a determination circuit 1506.

The pattern detection circuit 1505 generates four bit pairs (d) based on the previous judgment signal 1507, the output of the output latch 103, and the output of the temporary latch 104.
7, d6), (d5, d4), (d3, d2), (d
1, d0), the number of bit pairs corresponding to case g or case j shown in FIG. 16 is output.

The determination circuit 1506 includes the pattern detection circuit 1
A determination signal 1507 is output in response to the output of 505.
The operation of the determination circuit 1506 will be described later.

The bit order changing circuit 1508 processes the output of the output latch 103 according to the judgment signal 1507 output from the judgment circuit 1506. Judgment signal 15
When 07 is logic 1, the bit order change circuit 1508 changes the bit order of the output of the output latch 103. As a result, the data (d6, d7, d4, d
5, d2, d3, d0, d1) are output. When the judgment signal 1507 is logic 0, the bit order changing circuit 1508 passes the output of the output latch 103 as it is. As a result, the data (d7, d6, d5, d
4, d3, d2, d1, d0) are output.

The terminal driving circuit 109 drives the terminal 111 to output the output of the bit order changing circuit 1508 to the outside of the integrated circuit 101. Terminal drive circuit 110
Is a determination signal 1507 output from the determination circuit 1506
Terminal 112 to output to the outside of the integrated circuit 101.
Drive.

The terminal 111 is connected to the terminal 114 via the external bus 119. Terminal 112 is connected to terminal 115 via signal line 120.

The bit order changing circuit 1516 receives the 8-bit data via the terminal 114 and
The 8-bit data is processed in accordance with the logical level of. When the logic level of the terminal 115 is 1, the bit order changing circuit 1516 changes the bit order of the 8-bit data. The logic level of the terminal 115 is 0
If, the bit order permutation circuit 1516
The 8-bit data is passed as it is.

FIG. 18 shows logic defining the operation of the decision circuit 1506. As specified in FIG. 18, the operation of the determination circuit 1506 is specified according to case A and case B, respectively. Case A is the pattern detection circuit 1
The operation of the determination circuit 1506 when 505 outputs one of 0 and 1 is shown. In this case, the judgment circuit 1
506 outputs a determination signal 1507 of 0. Case B shows the operation of the determination circuit 1506 when the pattern detection circuit 1505 outputs one of 2 and 3. In this case, the determination circuit 1506 outputs 1 determination signal 1
507 is output.

FIG. 19 shows an example of a circuit configuration of the pattern detection circuit 1505 and the determination circuit 1506. The pattern detection circuit 1505 includes, for example, a flip-flop 1701
Logic gates 1702 to 1709 and logic gate 1710
To 1713. Judgment circuit 1506
Is realized by, for example, a programmable logic array 1714.

The flip-flop 1701 outputs the judgment signal 1 output from the programmable logic array 1714.
507 is delayed.

The logic gates 1702 to 1709 perform processing for changing the bit order of the output of the temporary latch 104 according to the output of the flip-flop 1701. When the output of flip-flop 1701 is logic 1, logic gates 1702 to 1709 exchange the bit order of the output of temporary latch 104. as a result,
Data (d6, d7, d4, d5, d2, d3, d0,
d1) is output from the logic gates 1702 to 1709. When the output of the flip-flop 1701 is logic 0, the logic gates 1702 to 1709 pass the output of the temporary latch 104 as it is. as a result,
Data (d7, d6, d5, d4, d3, d2, d1,
d0) are output from the logic gates 1702 to 1709.

The logic gates 1710 to 1713 compare the outputs of the logic gates 1702 to 1709 with the output of the output latch 103, and determine four bit pairs (d7, d6), (d
5, d4), (d3, d2), and (d1, d0), the number of bit pairs corresponding to case g or case j shown in FIG. 16 are output. For example, the number of bit pairs corresponding to case g or case j is determined by logic gates 1710 to 1713.
Is represented by the number of output signal lines whose logical level is 1 out of the four output signal lines from.

Programmable logic array 1714
Outputs a determination signal 1507 in accordance with the outputs of the logic gates 1710 to 1713. The logic shown in FIG.
This is realized by the programmable logic array 1714.

FIG. 20 is a block diagram showing a bit order changing circuit 150.
8 shows an example of the circuit configuration of FIG. Bit order change circuit 15
08 is realized by, for example, logic gates 1801 to 1808. The logic gates 1801 to 1808 output the input data (d7, d6, d
5, d4, d3, d2, d1, d0). When the determination signal 1507 is logic 1, the logic gates 1801 to 1808 exchange the bit order of the input data. As a result, the data (d
6, d7, d4, d5, d2, d3, d0, d1) are output from logic gates 1801-1808. If the judgment signal 1507 is logic 0, the logic gate 1801
1808 pass the input data as it is. As a result, the data (d7, d6, d5, d4, d3, d2,
d1, d0) are output from the logic gates 1801-1808.

The circuit configuration of bit order changing circuit 1516 is the same as the circuit configuration shown in FIG.

FIG. 21 shows an example of the operation of the data transfer device of the fourth embodiment in a time series. Hereinafter, how the data transfer device operates at each of the times 1, 2, 3, 4, and 5 shown in FIG. 21 will be described.

Time 1) At time 1, the output latch 10
It is assumed that b′10101010 is stored in 3 and the determination signal 1507 is 0. Output latch 103
Are passed through the bit order permutation circuit 1508. As a result, the terminal drive circuit 109 obtains b′10101
The external bus 119 is driven with a value of 010.

The determination signal 1507 of 0 is output to the integrated circuit 1 via the terminal driving circuit 110, the terminal 112 and the terminal 115.
13 is transmitted to the inside. Bit order change circuit 15
The signal on the external bus 119 is transmitted to the internal bus 117 via the terminal 114 via the bit order switching circuit 1516 because the bit 16 does not perform the bit order switching operation. Thus, b′10101010 stored in the output latch 103 is output to the internal bus 117. Further, the determination signal 1507 of “0” is held in the flip-flop 1701.

Time 2) At time 2, the output latch 10
3 is written with b′01010100 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
03 is stored. Since the output of the flip-flop 1701 is 0, the logic gates 1702 to 1709
04 as it is. Logic gate 1702
Output b'10101010 and output latch 1
03 and the output of the logic gate 171
It is input to 0-1713. As a result, the logic gate 17
Of the four output signal lines from 10 to 1713, the logic level of three output signal lines becomes 1. Judgment circuit 1506
Determines that the current state corresponds to case B in FIG. 18, and outputs a determination signal 1507 of 1.

The bit order of the output of output latch 103 is changed by bit order changing circuit 1508. As a result, the terminal drive circuit 109 has b'101010
The external bus 119 is driven with a value of 00. Since the state of the external bus 119 at time 1 is b'10101010, the state of the external bus 119 changes by one bit by the output of b'10101000 at this time. As a result, power corresponding to a one-bit state change is consumed.

The determination signal 1507 becomes 1 through the terminal drive circuit 110, the terminal 112 and the terminal 115.
13 is transmitted to the inside. Bit order change circuit 15
16 performs the bit order change operation, so that the external bus 1
The signals on 19 are permuted by a bit permutation circuit 1516 via a terminal 114 and transmitted to the internal bus 117. Thus, b′01010100 stored in the output latch 103 is output to the internal bus 117. Also, the determination signal 1507 becomes 1
Are stored in the flip-flop 1701.

Time 3) At time 3, output latch 10
3 is written with b′010101111 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
B′01010100 stored in “03” is stored. Since the output of the flip-flop 1701 is 1, the logic gates 1702 to 1709 output the temporary latch 1
The bit order of the output of No. 04 is exchanged. As a result, b '
10101000 is output from the logic gates 1702 to 1709. Here, b′10101000 corresponds to time 2
Is the same data as the data output to the external bus. Output b'101 of logic gates 1702-1709
01000 and the output b′010101 of the output latch 103
11 are input to logic gates 1710-1713.
As a result, the logic level of three of the four output signal lines from the logic gates 1710 to 1713 becomes 1. The determination circuit 1506 determines that the current state corresponds to case B in FIG. 18 and outputs a determination signal 1507 of 1.

The output of the output latch 103 is permuted in bit order by the bit permutation circuit 1508, and the terminal drive circuit 109 drives the external bus 119 with a value of b'10101011. External bus 11 at time 2
Since the state of No. 9 is b'10101000, the state of the external bus 119 changes by 2 bits by the output of b'10101011 this time. As a result, power corresponding to a 2-bit state change is consumed.

The determination signal 1507 becomes 1 through the terminal drive circuit 110, the terminal 112 and the terminal 115.
13 is transmitted to the inside. Bit order change circuit 15
16 performs the bit order change operation, so that the external bus 1
The signals on 19 are permuted by a bit permutation circuit 1516 via a terminal 114 and transmitted to the internal bus 117. Thus, b′010110111 stored in the output latch 103 is output to the internal bus 117. Also, the determination signal 1507 becomes 1
Are stored in the flip-flop 1701.

Time 4) At time 4, the output latch 10
3 is written with b′10101001 via the internal bus 102. At the same time as writing to the output latch 103, the temporary latch 104
B'010101111 stored in the storage unit 03 is stored. Since the output of the flip-flop 1701 is 1, the logic gates 1702 to 1709 output the temporary latch 1
The bit order of the output of No. 04 is exchanged. As a result, b '
10101011 is output from the logic gates 1702 to 1709. Here, b′10101011 is at time 3
Is the same data as the data output to the external bus. Output b'101 of logic gates 1702-1709
01011 and output b ′ 101010 of output latch 103
01 is input to logic gates 1710-1713.
As a result, the logic levels of the four output signal lines from the logic gates 1710 to 1713 all become 0. Judgment circuit 1
506 determines that the current state corresponds to case A in FIG. 18 and outputs a determination signal 1507 of 0.

The output of output latch 103 passes through bit order permutation circuit 1508. As a result, the terminal drive circuit 109 sets the external bus 1 to a value of b'10101001.
19 is driven. Since the state of the external bus 119 at time 3 was b′10101011, this time b′101
The output of 01001 changes the state of the external bus 119 by one bit. As a result, power corresponding to a one-bit state change is consumed.

The determination signal 1507 of 0 is output to the integrated circuit 1 via the terminal driving circuit 110, the terminal 112 and the terminal 115.
13 is transmitted to the inside. Bit order change circuit 15
16 does not cause the bit order change operation, the signal on the external bus 119 passes through the bit order change circuit 1516 via the terminal 114 and is transmitted to the internal bus 117. Thus, b′10101001 stored in the output latch 103 is output to the internal bus 117.

Note that the order of the bit order is not limited to that between adjacent bits. Arbitrary bits can be exchanged.

As described above, in the data transfer device of the fourth embodiment, the judgment circuit 1506 determines that the current state is as shown in FIG.
Is determined, and a determination signal 1507 indicating the determination result is output. The bit order changing circuit 1508 performs a process of changing the bit order of the output of the output latch 103 according to the logic level of the determination signal 1507. When the logical level of the determination signal 1507 is 1, the bit order of the output of the output latch 103 is changed by the bit order changing circuit 1508, and the signal whose bit order is changed is output to the external bus 1.
19 is output. When the logical level of the determination signal 107 is 0, the determination signal 107 is output to the external bus 119 without changing the bit order of the output of the output latch 103. Thus, the change in the state of the external bus 119 can be reduced. As a result, the power consumed by the external bus 119 can be reduced.

(Fifth Embodiment) FIG. 22 shows the configuration of a data transfer apparatus according to a fifth embodiment of the present invention. 22, the same components as those shown in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted.

The structure of the data transfer device of the fifth embodiment is as follows.
This is effective when the state of the external bus 119 is maintained until the next data is written to the output latch 103.

In the fifth embodiment, the pattern detection circuit 20
05 and the determination circuit 1506 function as the determination unit 2000. Based on a change in the state of the external bus 119 that occurs when the data is output to the external bus 119 without changing the bit order of the data, the determination unit 2000 outputs the data whose bit order has been changed to the external bus 119.
It is determined whether or not the change in the state of the external bus 119 that occurs when the state is output is smaller, and a determination signal 1507 indicating the determination result is output.

The pattern detection circuit 2005 uses the external bus 11 instead of inputting the output of the temporary latch 104.
1 in that the state of FIG. 9 is directly fed back and input.
7 is different from the pattern detection circuit 1505 shown in FIG. However, the operation of the pattern detection circuit 2005 is the same as the operation of the pattern detection circuit 1505 shown in FIG. 17, and a description thereof will not be repeated.

FIG. 23 shows an example of the circuit configuration of the pattern detection circuit 2005. The pattern detection circuit 2005 is realized by, for example, the logic gates 2101 to 2104. Logic gates 2101 to 2104 are connected to external bus 119.
Is compared with the output of the output latch 103, and four bit pairs (d7, d6), (d5, d4), (d3, d
2), the case g shown in FIG. 16 among (d1, d0)
Alternatively, the number of bit pairs corresponding to case j is output. For example, the number of bit pairs corresponding to case g or case j is:
It is represented by the number of output signal lines whose logic level is 1 among the four output signal lines from the logic gates 2101 to 2104.

When cyclic data is continuously transferred as in key scan, it is preferable to use the data transfer devices of the fourth and fifth embodiments. By changing the bit order of the transfer data, the external bus 1
This is because the change in the state of No. 19 can be reduced.
For example, as cyclic data, b'1000100
0, b'01000100, b'00100010,
A series of data such as b'00010001 is given.

Further, some data transfer devices in which the data transfer device of the first or second embodiment is combined with the data transfer device of the fourth or fifth embodiment are also conceivable. The bit inversion operation and the bit order permutation operation may be performed in parallel, and data may be transferred with a smaller change in the state of the external bus 119.
In this case, the signal line 120 is not 1 bit wide but 2 bits.
It is required to be bit wide. This is because it is necessary to specify the bit inversion operation and the bit order permutation operation separately. Alternatively, after the bit inversion operation is performed, the bit order is further switched, or after the bit order is switched, the bit inversion operation is further performed, and the data is changed in a state where the state change of the external bus 119 is smaller. You may make it transfer. Also in this case, the signal line 120 needs to have a 2-bit width instead of a 1-bit width. This is because it is necessary to specify the bit inversion operation and the bit order permutation operation separately.

When the integrated circuit 101 prepares a predetermined data compression method and the integrated circuit 113 prepares a predetermined data decompression method corresponding to the predetermined data compression method, the data is compressed. Of the missing data and the compressed data, data that causes a small state change to the external bus 119 is transferred via the external bus 119, and indicates whether the data has been compressed using the predetermined data compression method. One bit may be transferred via the signal line 120. The integrated circuit 113 recovers the original data by using a predetermined data decompression method as necessary.

Further, when the integrated circuit 101 prepares a plurality of types of data compression methods and the integrated circuit 113 prepares a plurality of types of data decompression methods, the compressed data is transmitted via the external bus 119. And the type of data compression method used to compress the data.
20 may be transferred. Integrated circuit 11
3 recovers the original data by receiving the compressed data and decompressing the data using a decompression method corresponding to the compression method. The integrated circuit 101 has 2 ⁿ
When various types of data compression methods are prepared, the signal line 120 needs to have at least an n-bit width.

[0139]

According to the data transfer apparatus and the data transfer method of the present invention, the data is processed by processing the data from the change in the bus state that occurs when data is output to the bus without processing the data. It is determined whether the change in the state of the bus that occurs when the output data is output to the bus is smaller.

Data is processed according to the result of the determination. Further, according to the determination result, either the unprocessed data or the processed data is selectively output to the bus. As a result, a change in the state of the bus due to data transfer can be reduced. As a result, the power consumed in the bus is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention.

FIG. 2 is a flowchart showing a procedure of a data transfer method according to the present invention.

FIG. 3 is a diagram showing a configuration of a first embodiment of a data transfer device according to the present invention.

FIG. 4 is a diagram illustrating logic that defines the operation of the determination circuit in the data transfer device according to the first embodiment;

FIG. 5 is a diagram illustrating an example of an operation of the data transfer device according to the first embodiment in a time series.

FIG. 6 is a diagram illustrating a configuration of a mismatched number detection circuit 105 and a determination circuit 106 in the data transfer device of the first embodiment.

FIG. 7 is a diagram showing the number of bits whose status has changed on an external bus 119 when data is transferred by a conventional data transfer device.

FIG. 8 is a diagram illustrating the number of bits whose states have changed on the terminals 111 and 112 when data is transferred by the data transfer device of the first embodiment.

FIG. 9 is a diagram illustrating an effect of reducing power consumption by the data transfer device according to the first embodiment.

FIG. 10 is a diagram showing a configuration of a second embodiment of the data transfer device according to the present invention.

FIG. 11 is a diagram illustrating logic defining the operation of a determination circuit in a data transfer device according to a second embodiment.

FIG. 12 is a diagram illustrating an example of an operation of the data transfer device according to the second embodiment in a time series.

FIG. 13 is a diagram illustrating a configuration of a mismatched number detection circuit 505 and a determination circuit 506 in the data transfer device of the second embodiment.

FIG. 14 is a diagram showing a configuration of a third embodiment of the data transfer device according to the present invention.

FIG. 15 is a diagram illustrating an effect of reducing power consumption by the data transfer device of the third embodiment.

FIG. 16 is a diagram illustrating the principle of reducing power consumption by changing the bit order of data.

FIG. 17 is a diagram showing a configuration of a fourth embodiment of the data transfer device according to the present invention.

FIG. 18 is a diagram illustrating logic that defines the operation of the decision circuit 1506 in the data transfer device of the fourth embodiment.

FIG. 19 is a diagram illustrating a configuration of a pattern detection circuit 1505 and a determination circuit 1506 in the data transfer device of the fourth embodiment.

FIG. 20 is a diagram showing a configuration of a bit order changing circuit 1508 in the data transfer device of the fourth embodiment.

FIG. 21 is a diagram illustrating an example of an operation of the data transfer device according to the fourth embodiment in a time series.

FIG. 22 is a diagram showing a configuration of a data transfer device according to a fifth embodiment of the present invention.

FIG. 23 is a diagram illustrating a configuration of a pattern detection circuit 2005 in the data transfer device of the fifth embodiment.

[Explanation of symbols]

 10, 50, 1500, 2000 Judgment unit 101, 113 Integrated circuit 103 Output latch 104 Temporary latch 105, 505 Mismatch number detection circuit 106, 506, 1506 Judgment circuit 107 Judgment signal 108 Logical inversion circuit 109, 110 Terminal drive circuit 116 Logical inversion Circuits 1505, 2005 Pattern detection circuit 1508 Bit permutation circuit 1516 Bit permutation circuit

Claims (12)

(57) [Claims] 1. A data transfer device connected to a bus and a control signal line, wherein the data transfer device outputs the data to the bus without processing the data. Determining means for determining whether a change in the state of the bus which occurs when the processed data is output to the bus is smaller than the above, and changing the bit order according to the determination result To do
A first processing means for processing the data by, in accordance with the determination result, selectively a first output for outputting to the bus of one of the processed data by the data and the first processing means And a second output unit for outputting a control signal indicating the determination result to the control signal line. 2. The method according to claim 1, wherein the determination unit includes a first storage unit configured to store a previous determination result, a second storage unit configured to store the previous data when the current data is received, 2. The data transfer device according to claim 1, further comprising: a determination unit that determines whether or not to process the current data in accordance with the current data and the current data. 3. The determination means outputs a number of patterns that match a relationship between the current data and the previous data among a predetermined number of patterns prepared in advance according to a result of the previous determination. 3. The data transfer device according to claim 2, further comprising: a pattern detection unit that performs processing; and a unit that outputs a signal indicating whether or not to process the current data in accordance with an output of the pattern detection unit. 4. The apparatus according to claim 1, wherein said determination means includes a determination means for determining whether or not to process the current data according to a current state of the bus and current data. A data transfer device according to claim 1. 5. A pattern detecting means for outputting a number of patterns corresponding to a relationship between a current state of the bus and the current data among a predetermined number of patterns prepared in advance, 5. The data transfer device according to claim 4 , further comprising: a unit that outputs a signal indicating whether or not to process the current data according to an output of the pattern detection unit. 6. The data bus according to claim 1, wherein the data is a part of data supplied to the data transfer device via an entire bus, and a bit width of the bus is smaller than a bit width of the entire bus. Data transfer device. 7. The data transfer device receives the data output from the first output means via the bus, and outputs a control signal indicating the determination result output from the second output means to the control signal line. And performs bit order permutation according to the control signal.
And a second processing means for processing the data by the data transfer apparatus according to claim 1. 8. A transmitting unit for transmitting data and a control signal, a bus connected to the transmitting unit and carrying the data, a control signal line connected to the transmitting unit and carrying the control signal, and the bus And a receiving unit connected to the control signal line for receiving the data via the bus and receiving the control signal via the control signal line. Is generated when the processed data is output to the bus by processing the data, based on a change in the state of the bus that occurs when the data is output to the bus without processing the data. Determining means for determining whether or not the change in the state of the bus is smaller; and changing the bit order according to the determination result.
A first processing means for processing the data by, in accordance with the determination result, selectively a first output for outputting to the bus of one of the processed data by the data and the first processing means Means, and a second output means for outputting a control signal indicating the determination result to the control signal line, wherein the receiving section receives the data output from the first output means via the bus Receiving the control signal indicating the determination result output from the second output means via the control signal line, and changing the bit order according to the control signal to process the data. A data transfer device comprising a second processing means for performing the processing. 9. The determination unit of the transmission unit includes: a first holding unit that holds a previous determination result; a second holding unit that holds previous data when receiving current data; 9. The data transfer device according to claim 8 , further comprising: a determination unit that determines whether to process the current data according to a result, the previous data, and the current data. 10. The determination unit of the transmission unit includes: a determination unit that determines whether to process the current data according to a current state of the bus and current data. The data transfer device according to claim 8 . 11. When the processed data is output to the bus based on a change in the state of the bus that occurs when the data is output to the bus without processing the data. determines whether towards the state change of the bus is less generated, bits in accordance with the determination result
A data transfer method for processing the data by changing the order, and transferring the processed data according to the determination result. 12. The data transfer method according to claim 11 , wherein the data is reproduced by performing processing opposite to the processing of the data according to the determination result.