JPS58161575A - Parallel-serial converting circuit - Google Patents

Abstract

PURPOSE:To insert simply a specific data to a converted serial data, by generating successively the selection information by means of a counter and selecting and delivering successively the parallel data based on said selection information to convert a serial data into a variable length parallel data. CONSTITUTION:A parallel data PD having a data length and a fixed data CD are fed to input terminals 0-9 and 10-15 of a data selector 1. The count output of a counter 2 is fed to selection terminals A-D of the selector 1. In addition, a digital comparator 3 is provided between the output of the counter 2 and the input terminal of data length information PDL of the data PD to compare the information PDL with the output of the counter 2. Then a coincidence derecting signal DT is supplied to a control processing part 4. The part 4 controls the counter 2, and the selection information given from the counter 2 is applied to the selector 1. Then the data PD is converted into the data SD and then delivered. At the same time, the data CD is inserted to the data SD.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel-to-serial conversion circuit, and more particularly to a circuit for converting variable length parallel data into serial data.

Generally, when transmitting a facsimile signal or the like digitally, the facsimile signal is encoded in a predetermined manner to obtain variable length parallel data, and then the parallel data is converted into serial data and transmitted! ! I will do i+J#.

Conventionally, as a circuit for converting such variable-length parallel data into serial data, a circuit has been used that is composed of a shift register that can load parallel data and a clock circuit that controls the timing of the operation of the shift register. The clock output timing of this clock circuit is appropriately controlled to obtain serial data corresponding to the data length of the parallel data input to the shift register.

However, such conventional parallel-to-serial conversion circuits do not control the output of the clock when inserting specific data (for example, rOJ data to ensure transparency of identification flags, etc.) into converted serial data. This has the disadvantage that control becomes extremely complicated.

This invention has been made in view of the above circumstances, and provides a parallel-to-serial conversion circuit that can not only convert variable-length parallel data to serial data but also easily insert specific data into the converted serial data. The purpose is to provide.

That is, the present invention includes selection information generation means that sequentially generates selection information using a counter or the like, inputting parallel data,
The parallel-to-serial converter circuit includes a data selector that sequentially selects and outputs the input parallel data based on the selection information.Using the function of this data selector, for example, the data selector can be activated at a desired time. , or make it inactive (this causes the data selector output to be unconditionally "
0'' data is inserted>, or fixed data other than parallel data may be added in advance to other input addresses of the data selector, and this fixed data may be selected at a desired time using the above selection information. Inserts specific data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A parallel-to-serial conversion circuit according to the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a parallel-to-serial conversion circuit according to the present invention.

This embodiment circuit includes a data selector 1, a counter 2, a digital converter 3, and a control processing section 4, and is configured as shown in the figure. That is, variable-length parallel data PD for which serial conversion is desired (in this example, data with a maximum length of 10 bits), and specific fixed data CD for which insertion is desired (in this example, up to 6 types of data can be inserted). ) are respectively applied to the input terminals at addresses 0 to 15 of the data selector 1, and these applied data are applied to the selection terminals A, B, C, and D of the data selector 1.
They are selectively outputted in accordance with the contents of the 4-bit count output of counter 2 added to the output.

For example, the count output of counter 2 is a binary signal "0.0.
0.0'', the data added to the input terminal at address 0 of data selector 1, that is, the data of the first bit of the parallel data PD in the example shown in FIG. 1, is used as data SD. Similarly, if the count output of counter 2 is "0.0.0.1J", then the data added to the input terminal at address 1 of data selector 1, exactly the back of parallel data PD. If the second bit data is selected and output as data SD, and the count output of counter 2 is "1, Oll, 0", the data added to the input terminal at address 10 of data selector 1, i.e. One of the fixed data CDs is selectively output as data SD. In this embodiment circuit, the digital comparator 3 receives and compares the data length information PDL indicating the data length of the variable length parallel data PD and the count output of the counter 2, and when these contents match, The control processing section 4 has a function of outputting a coincidence detection signal DT to the control processing section 4. The control processing section 4 also sets the data selector 1 to an active state or an inactive state using a signal EN, and outputs a predetermined clock signal CK using a signal INO.
The count content of the counter 2 is incremented at a timing synchronized with , and the count content of the counter 2 is initialized by a signal CL. The digital comparator has the function of loading the preset data of By applying the coincidence detection signal DT from step 3, it is recognized that the serial conversion of one variable-length parallel data has been completed, and predetermined processing to be described later is performed.

FIG. 2 is a flowchart showing an example of the operation of the control processing section 4. Hereinafter, the specific operation of the embodiment circuit shown in FIG. 1 will be explained with reference to this flowchart.

First, a normal parallel-to-serial conversion operation that does not require insertion of specific data will be described.

Now, for example, parallel data P having a data length of 8 bits
If D (this data length information PDL is "Oll, 1.1") is applied to the input terminals from address 0 to address 7 of data selector 1, control processing unit 4 inputs data by signal EN as an initial operation. Set the selector 1 to the active state (see step 10 in Figure 2), and then initialize the count contents of the counter 2 by sending the signal @CL (step 2 in Figure 2).
0>). As a result, the count output of counter 2 becomes “0”.
．． 0.0.0", and the above parallel data PD
Of these, the bit data applied to the input terminal at address 0 of data length information RI1 is selectively output as data SD. This output data SD is transferred in synchronization with the timing of the clock signal GK output from the control processing section 4 (see step 30 in FIG. 2). Next, the control processing section 4
Increments the count content of counter 2 to "0.0.0.1" by signal INc, and sets the data of the bit applied to the input terminal at address 1 of data selector 1 of the parallel PD as data SD. Select and transfer in the same way (
See Step 40 in Figure 2. Below, the control processing unit 4:
This count content increment operation and data transfer operation are repeatedly executed until the count content of the counter 2 reaches "0.1.1.1", which is the content of the data length information PDL of the parallel data PD ( Figure 2 Step 90
), and when this content matches 10.1.1.1, it receives the coincidence detection signal DT output from the digital comparator 3 and recognizes that the serial conversion of the parallel data PD has been completed, For example, the next parallel data is applied with the data selector 1 inactive. Of course,
This means that the data SD has been transferred as serial data corresponding to the parallel data PD.

Next, the rOJ data is used as specific data and serial SD
We will explain the operation when inserting into.

For any parallel data PD, during the process of step 40 and step 90 shown in the 7th day chart in Figure 2, "0" data is inserted for the purpose of ensuring transparency of the identification flag. (Step 50 in Figure 2)
), the data selector 1 is controlled to be inactive upon completion of the process in step 40 for the bit of the parallel data PD (the bit before the bit for which "O" data is desired to be inserted). Program the processing unit 4. Thereafter, the control processing unit 4 stops the signal ING, interrupts the counting content increment operation, and operates in this state to transfer the data SD for an arbitrary clock period (see step 70 in FIG. 2). As a result, "0" data is transferred by the number of bits corresponding to the clock cycle, and this "0" data is inserted into the serial data length information. When this "0" data insertion operation is completed, the control processing unit 4 again activates the data selector 1 and outputs the data length information P of the parallel data PD with which the count contents of the counter 2 are compared by the digital comparator 3.
The above-described processes of step 40> and step 90> are repeated until the content matches the content of the DL. When inserting "0" data again for one parallel data PD, as soon as the processing in step 40 for that bit is completed, the same steps as described above are carried out in steps 60 to 80. good.

The subsequent operations are similar to normal parallel-to-serial conversion operations.

In addition to inserting the above-mentioned "0" data, when inserting specific fixed data CDs (not shown in the flowchart of FIG. 2), if the data desired to be inserted among these fixed data CDs is of counter 2 so that it is selectively output from selector 1! Set i1 number output. 11i, that is, the control processing unit 4 forms preset data necessary to select the data desired to be inserted using the signals P1, P2, P3, and P4, and loads the formed preset data into the counter 2 using the signals. . If the selected fixed data is then transferred at the timing of the clock signal CK, this fixed data will also be inserted in series into the data SD.

Note that the form of the fixed data CD is arbitrary, and may be different types of serial data, or multiple bits of parallel data (in this case, in the example shown in FIG. 1, the maximum data length is 6 bits). possible), or even the previously mentioned "0" data. Therefore, if the fixed data CD is serial data, the contents of counter 2 are held until the serial data is completely transferred, and if it is parallel data, the contents of counter 2 are held as in the parallel-to-serial conversion operation described above. You can increment them sequentially. In general, the insertion of such a fixed data CD is flexible as described above. However, if this fixed data CD is the above-mentioned "o" data and it is necessary to insert the "0" data during the parallel-to-serial conversion operation, the embodiment circuit shown in FIG. An appropriate memory is provided to temporarily hold the count contents when the counter 2 is incremented, and after the insertion of "0" data by loading the preset data into the counter is completed, the increment operation is restarted from the count contents held above. Alternatively, the incrementing operation of the rOJ data insertion request-H counter 2 is stopped, and the preset data necessary to select the "0" data is directly added to the data selector 1 without going through the counter 2. The incrementing operation of the counter 2 may be restarted after the insertion of "0" data based on the preset data is completed.

Furthermore, in the embodiment shown in FIG.
Although the first bit of is added to the input terminal at address 0 of the data selector 1, the present invention is not particularly limited to this. That is, the function of loading the count contents corresponding to the address of the input terminal to which the first bit of the variable length parallel data PD is added into the counter 2 as preset data, and the data length information P of the variable length parallel data PD.
As long as we add a function to convert the contents of DL, that is, convert the number of bits corresponding to the address from address O to the address of the input terminal to which the first bit of this parallel data PD is added to the contents of this data length information PDL, The above variable length parallel data P
No matter where D is applied to the input terminal of the data selector 1 at any address, it can be effectively serialized.

Note that the maximum data length that can be serially converted from the variable length parallel data PD is determined by the input permission of the data selector 1, and is, of course, not limited to the data length described above.

As explained above, the parallel single-column conversion circuit according to the present invention has the advantage of effectively serializing any variable-length parallel data and easily realizing the insertion of other specific data. It has a great effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the parallel-to-serial conversion circuit according to the present invention, and FIG. 2 is a flowchart showing an example of the operation of the control processing section in the embodiment circuit shown in FIG.

Claims (3)

[Claims] (1) selection information generating means that receives data length information indicating the data length of input variable length parallel data and sequentially generates data selection information corresponding to the data length information; a data selector that sequentially selects each bit signal of the received variable-length parallel data in accordance with data selection information, and a parallel-serial conversion that outputs serial data corresponding to the variable-length parallel data from the master data selector. circuit. (2) The selection information means includes a counter that sequentially counts, and a comparator that compares the count output contents of the counter with the contents of the data length information and outputs a coincidence detection signal when the contents match. 2. The parallel-to-serial conversion circuit according to claim 1, further comprising control means for initializing the counter based on the coincidence detection signal, and a count output of the counter is used as the data selection information. (3) selection information generating means for receiving data length information indicating the data length of input variable length parallel data and sequentially generating data selection information corresponding to the data length information; a data selector that sequentially selects each bit signal of the received variable-length parallel data in accordance with the data selection information; and a data selector that temporarily holds the data selection information and temporarily deactivates the data at any time. and means for actively inserting "0" data into said serial data.