JPH04303234A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data with a high reliability without reducing the effective transfer rate of multibit parallel data where simultaneous switching noise occurs. CONSTITUTION:A bit change detecting circuit 1 compares data outputted at present and data to be next outputted with each other with one bit as the unit to detect whether the bit variation is larger than a set value or not, and a bit pattern conversion signal which is significant in the case of the bit variation larger than the set value is outputted. If the bit pattern conversion signal is significant, a bit pattern converting circuit 2 inverts all bits of data to be next outputted to output the bit pattern of less bit variation; but otherwise, the circuit 2 outputs this data as it is. The one-bit of bit pattern conversion signal is added to this output, and it is transferred. The transfer destination fetches transfer data including the one-bit of bit pattern conversion signal; and if the bit pattern conversion signal is significant, all bits are internally inverted to restore the original data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system that outputs multiple bits of transfer data in parallel.

0002

[Prior Art] When transferring multiple bits of data in parallel between IC packages, etc., "transistor technology SP
ECIAL No. 22” (CQ Publishing Co., Ltd., 19
As described in detail in pp. 34-49 of the publication (July 1, 1990), a problem called simultaneous switching noise occurs in the output stage of the package, causing errors in transferred data. This simultaneous switching noise is
With advances in data processing and semiconductor technology, data bit widths and transfer speeds have increased, as typified by microprocessors, and this has become a major problem. However, no technology has yet been found that fundamentally solves this problem using hardware technology.

0003

[Problems to be Solved by the Invention] As described above, in this type of conventional data transfer method, when transferring multi-bit parallel data, simultaneous switching noise occurs and errors are likely to occur in the transferred data, resulting in reliability problems. There was a problem. Therefore, in order to improve reliability, countermeasures have been taken such as keeping the transfer rate low enough to prevent errors or adding an error correction code. In addition, the error correction code is
In order to improve the correction ability, the number of check bits added must be increased, which considerably reduces the effective transfer rate.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transfer method that can realize highly reliable data transfer without reducing the effective transfer rate of multi-bit parallel data.

[0005]

[Means for Solving the Problems] A data transfer method according to the present invention compares currently output data and next output data bit by bit to detect whether the amount of bit change is greater than or equal to a set value. Based on the bit change detection means and this detection output, when the bit change amount is greater than the set value, the next data to be output is converted to a bit pattern with a smaller bit change amount by bit inversion and output, and the bit change amount is set. A bit pattern converting means outputs the data as is when it is less than the value, and the detection output of the bit change detecting means is added to the output data of the bit pattern converting means and transferred.

[0006]

[Operation] In this invention, when the amount of bit change is large and accounts for more than half of the total number of bits, prior to output, for example, all bits are inverted to convert to a bit pattern with a small amount of bit change, and a notification to that effect is made. 1 bit of change detection output shown is added and output. At the transfer destination, the transfer data including the change detection output 1 bit is taken in, and the change detection output 1 is
If the bit indicates bit inversion, all bits are internally inverted to return to the original data, allowing subsequent processing to be performed normally. As a result, highly reliable data transfer can be achieved without reducing the effective transfer rate of multi-bit parallel data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of an output stage of a microprocessor or the like to which the present invention is applied. In the figure, 1 is a bit change detection circuit that compares the currently output data and the next data to be output bit by bit and detects whether the amount of bit change is greater than or equal to the set value. In the above case, the 1-bit bit pattern conversion signal which is the detection output is considered significant. 2: When the above bit pattern conversion signal is significant, all bits of the data to be output are inverted to convert it into a bit pattern with a small amount of bit change and output, and when the bit pattern conversion signal is not significant, it is output as is. This is a bit pattern conversion circuit. The bit pattern conversion signal output from the bit change detection circuit 1 is input to the bit pattern conversion circuit 2, and is added to the output data of the bit pattern conversion circuit 2 and transferred to the outside. Note that the setting value for determining whether the amount of bit change is large or small is valid if it is more than half of the total number of bits.・It should be determined by taking into consideration whether an error will occur.

FIG. 2 is a circuit diagram showing a specific example of the configuration shown in FIG. 1, and here shows the case of 64-bit width. In the figure, 11 and 12 are 64-bit wide latches that latch input and output data, respectively, and 13 is the output of latch 12, that is, the data that is currently being output, and the output of latch 11, that is, the data that will be output next, in bits. is a comparator that compares each corresponding bit with 64 E
It can be configured with an XOR (exclusive OR) gate. Tr1 to Tr64 are 64 PMOS transistors connected in parallel and controlled by each bit output of the comparator 13, with one end connected to the power supply and the other end connected to the pull-down resistor 14. Reference numeral 15 denotes an inverter which receives as input the potential at the connection point of the PMOS transistors Tr1 to Tr64 and the pull-down resistor 14, and these constitute the bit change detection circuit 1 of FIG. Furthermore, a bit pattern conversion circuit 2 is provided between the latches 11 and 12 provided at the input/output. The output of the inverter 15 is input to the bit pattern conversion circuit 2 as a bit pattern conversion signal which is the detection output of the bit change detection circuit 1, and is added to the output data of the latch 12 and output to the outside. That is, the transfer data is 64 bits+1 bit=65 bits. Note that the bit pattern conversion circuit 2 has a path in which an inverter is inserted for each bit and a path in which an inverter is not inserted in parallel via a selector, and when the bit pattern conversion signal is significant, an inverter is inserted. This can be easily realized by selecting a route and, if it is not significant, selecting a route without an inverter inserted. Further, the setting value of the number of bits for determining the amount of bit change can be set by adjusting the value of the pull-down resistor 14 according to the application.

Next, the operation of the above embodiment will be explained. First, if the amount of bit change between the currently output data and the next output data is less than the set value, in FIG. The transistor T turns on.
Since r increases, the potential at the connection point with the pull-down resistor 14 is in a high state, and the bit pattern conversion signal that is the output of the inverter 15 remains "0" and is not significant. Therefore, the bit pattern conversion circuit 2 does not perform any conversion and passes through the data to be output next. As a result, 64 bits of original data without bit pattern conversion and 1 bit of a bit pattern conversion signal with a value of "0" indicating this are transferred to the transfer destination. At the transfer destination, transfer data including one bit of the bit pattern conversion signal is taken in, and since the bit pattern conversion signal does not indicate bit inversion, no bit inversion processing is performed.

On the other hand, when the amount of bit change is greater than the set value, as shown in FIG. The potential at the connection point becomes low, and the bit pattern conversion signal that is the output of the inverter 15 becomes "1" and becomes significant. Therefore, the bit pattern conversion circuit 2 performs bit pattern conversion to invert all bits on the data to be output next, and outputs the data. As a result, the data 64 that has undergone bit pattern conversion is transferred to the transfer destination.
The bit and one bit of a bit pattern conversion signal with a value of "1" indicating this are transferred. At the transfer destination, transfer data including one bit of the bit pattern conversion signal is taken in, and since the bit pattern conversion signal indicates bit inversion, bit inversion processing is performed to restore the original data. in this way,
If there are many bits that change simultaneously and exceed a certain number of bits,
By transferring data after converting it into a bit pattern with fewer simultaneous changes, highly reliable transfer can be achieved without reducing the effective transfer rate.

FIG. 3 is a circuit diagram showing another specific example of the configuration of FIG. 1, which differs from that of FIG. 2 in the configuration after the comparator 13. That is, in FIG. 2, an analog circuit is used, and in FIG. 3, adders of 2 bits to 7 bits are connected hierarchically as shown in the figure, and the entire circuit is constructed of digital circuits. This causes one of the two inputs to have “−32
” is input, the most significant bit of the adder output at the final stage is “
0'' indicates that 32 bits or more, that is, more than half of the bits are inverted, and this most significant bit is converted into a bit pattern conversion signal via the inverter 15 and sent to the bit pattern conversion circuit 2 and the transfer destination. This is what I did. In addition, by determining the most significant bit in combination with other bits, the setting value that determines whether the amount of bit change is large or small can be arbitrarily set according to the application target, similar to the embodiment shown in FIG. Effects can be obtained.

[0012] In the above embodiment, bit pattern conversion is performed by inverting all bits; however, if there is a margin for bit change without causing a data transfer error, only odd or even numbered bits may be converted. It may also be reversed.

FIG. 2 shows a specific example of the configuration of the present invention.
The circuits shown in FIGS. 3A and 3B show examples of a case where the circuit is constructed using an analog circuit and a case where the circuit is constructed entirely using a digital circuit, and it goes without saying that the present invention is not limited thereto.

Further, in the above embodiment, an example was shown in which the present invention is applied to all output bits at once, but if the output bits are divided into, for example, a plurality of physically adjacent blocks,
It may be performed independently for each block. By dividing into a plurality of blocks, the number of bits targeted by one bit change detection circuit is reduced, and processing speed can be improved. Furthermore, by combining physically adjacent output buffers into one block, it is possible to precisely deal with "simultaneous switching of physically adjacent output buffers," which is the most problematic issue in terms of electrical characteristics. The effects of the present invention can be further ensured.

[0015]

As described above, according to the present invention, the bit change method detects whether the bit change amount is greater than or equal to a set value by comparing the currently output data and the next output data bit by bit. Based on the detection means and this detection output, when the bit change amount is greater than the set value, the next data to be output is converted to a bit pattern with a smaller bit change amount by bit inversion and output, and the bit change amount is less than the set value. A bit pattern converting means is provided which outputs the data as is when the number of bits is low, and the detection output of the bit change detecting means is added to the output data of the bit pattern converting means and transferred.
Highly reliable data transfer can be achieved without reducing the effective transfer rate of multi-bit parallel data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration example of FIG. 1;

FIG. 3 is a circuit diagram showing another specific configuration example of FIG. 1;

[Explanation of symbols]

1 Bit change detection circuit (bit change detection means) 2
Bit pattern conversion circuit (bit pattern conversion means) 11, 12 Latch 13 Comparator

Claims (1)

[Claims] [Claim 1] In a data transfer method that outputs multiple bits of transfer data in parallel, the currently output data and the next output data are compared bit by bit to determine whether the amount of bit change is greater than or equal to a set value. Based on the bit change detection means and this detection output, when the amount of bit change is greater than the set value, the next data to be output is converted to a bit pattern with a smaller amount of bit change by bit inversion and output, and the amount of bit change is detected. bit pattern converting means that outputs the data as is when the bit pattern converting means is less than a set value, and the detection output of the bit change detecting means is added to the output data of the bit pattern converting means and transferred. Transfer method.