JP3159783B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a video signal processing apparatus suitable for a camera-integrated VTR or an electronic still video camera.

[0002]

2. Description of the Related Art There is an image pickup apparatus such as a camera-integrated VTR or an electronic still video camera for recording an NTSC video signal. Recently, digitalization of video signal processing circuits has progressed, and some imaging devices have a memory for video signals.

When a video signal of the NTSC system is stored in the video signal memory in a component system, the
In the SC system, since the frequency band of the chrominance signal is narrower than the frequency band of the luminance signal, the memory capacity for the chrominance signal is generally set smaller than the memory capacity for the luminance signal. That is, the sampling frequency of the color signal is lowered to reduce the amount of data.

FIG. 5 shows an example of an image pickup apparatus provided with a conventional video signal processing device when a video signal of the NTSC system is stored in a video signal memory in a component system.

In the configuration shown in FIG. 5, an image of a subject is formed on a solid-state image sensor (hereinafter, referred to as a CCD) 102 by a lens 101. A video signal formed by photoelectric conversion by the CCD 102 is supplied to the imaging circuit 103 under the control of the imaging circuit 103.

In the synchronization signal generating circuit 104, a synchronization signal is formed. The synchronization signal is supplied to the imaging circuit 103, write sampling pulse generation circuits (hereinafter, referred to as write pulse generation circuits) 131 and 132, and read sampling pulse generation circuits (hereinafter, read pulse generation circuits).
116, 117, etc.

In the imaging circuit 103, a control signal from the system control circuit 170 and the synchronizing signal generation circuit 1
04 based on the synchronization signal supplied from the CCD
Drive control and video signal read control.
In the imaging circuit 103, the video signal supplied from the CCD 102 is separated into a luminance signal and a chrominance signal. The luminance signal is supplied to an A / D conversion circuit 109 after being subjected to predetermined signal processing in a luminance signal processing circuit 105. The color signals are converted into color difference signals (RY, BY), and the color difference signals (RY, BY) are alternately determined by the color signal processing circuit 106 in units of 1H (horizontal scanning period). , And then supplied to the A / D conversion circuit 111.

In the write pulse generating circuit 132, based on a control signal from the system control circuit 170 and a synchronizing signal supplied from the synchronizing signal generating circuit 104,
A clock signal that defines the timing of the AD conversion of the luminance signal and the generation of the write address is formed. This clock signal is supplied to the A / D conversion circuit 109 and the write address generation circuit 134.

In the write pulse generating circuit 131, based on a control signal from the system control circuit 170 and a synchronizing signal supplied from the synchronizing signal generating circuit 104,
A clock signal that defines the timing of the AD conversion of the color signal and the generation of the write address is formed. This clock signal is supplied to the A / D conversion circuit 111 and the write address generation circuit 133.

In the A / D conversion circuit 109, AD conversion is performed at the timing of the clock signal supplied from the write pulse generation circuit 132. That is, the luminance signal processing circuit 1
The analog luminance signal supplied from 05 is digitized and converted into pixel data. This pixel data is supplied to the luminance signal memory 110.

In the A / D conversion circuit 111, AD conversion is performed at the timing of the clock signal supplied from the write pulse generation circuit 131. That is, the color signal processing circuit 10
The analog color signal supplied from 6 is digitized and converted into pixel data. This pixel data is supplied to the color signal memory 112.

In the write address generating circuit 134, a write address is formed based on a clock signal supplied from the write pulse generating circuit 132. The write address and the write clock signal are stored in the luminance signal memory 1.
10 is supplied. In the write address generation circuit 133, a write address is formed based on a clock signal supplied from the write pulse generation circuit 131. The write address and the write clock signal are supplied to the color signal memory 112.

In the luminance signal memory 110, pixel data is written based on a write address and a clock signal supplied from the write address generating circuit 134. In the color signal memory 112, pixel data is written based on a write address and a clock signal supplied from the write address generating circuit 133.

In the read pulse generation circuit 117, based on a control signal from the system control circuit 170 and a synchronization signal supplied from the synchronization signal generation circuit 104,
A clock signal defining the timing of the DA conversion of the luminance signal and the read address is formed. The clock signal generated by read pulse generation circuit 117 is supplied to D / A conversion circuit 118 and read address generation circuit 115.

In the read pulse generation circuit 116, based on a control signal from the system control circuit 170 and a synchronization signal supplied from the synchronization signal generation circuit 104,
A clock signal that defines the timing of the DA conversion of the color signal and the read address is formed. The clock signal formed by the read pulse generation circuit 116 is supplied to the D / A conversion circuit 121 and the read address generation circuit 114.

In read address generating circuit 115, a read address for a luminance signal is generated based on a clock signal supplied from read pulse generating circuit 117.
This read address is supplied to the luminance signal memory 110. The read address generation circuit 114 generates a read address for a color signal based on the clock signal supplied from the read pulse generation circuit 116.
This read address is supplied to the color signal memory 112.

The pixel data of the luminance signal read from the luminance signal memory 110 is converted into an analog luminance signal by the D / A conversion circuit 118 based on the timing of the clock signal supplied from the read pulse generation circuit 117. You. This analog luminance signal is subjected to FM modulation by an FM modulation circuit 119. The luminance signal subjected to the FM modulation is supplied to the adder 120.

The pixel data of the color signal read from the color signal memory 112 is converted into an analog color signal by the D / A conversion circuit 121 based on the timing of the clock signal supplied from the read pulse generation circuit 116. You. This analog color signal is subjected to FM modulation by an FM modulation circuit 122. The color signal subjected to the FM modulation is added to an adder 120.
Supplied to

The adder 120 adds the FM-modulated luminance signal and color signal to form a video signal. This video signal passes through the recording amplifier 123,
Supplied to

The system control circuit 170 is a conventionally known microcomputer for controlling the entire system,
U, ROM and RAM. The system control circuit 170 includes an operation unit 171 having various operation switches, and a display unit 17 for displaying a setting state of the camera.
2 are respectively connected.

The magnetic disk 152 is driven to rotate by a spindle motor 153 controlled by a spindle servo circuit 154. This spindle servo circuit 154
Is based on the control of the system control circuit 170,
When the spindle motor 153 is rotated at a certain rotational speed (for example, 360
(0 rpm).

The spindle motor 153 is provided with an FG pulse generator 155.
2 is detected, and this detection signal is supplied to the spindle servo circuit 154. Also, the PG coil 156
Detects the rotation timing of the magnetic disk 152 and supplies this detection signal to the spindle servo circuit 154.

The magnetic head 151 is displaced in the radial direction of the magnetic disk 152 by a tracking motor 160, and the tracking motor 160 is controlled by a system control circuit 170 via a tracking motor drive circuit 161. That is, the magnetic disk 1
While the 52 is rotating, the magnetic head 151 is positioned on a predetermined track of the magnetic disk 152, and records a video signal and an ID code on this track.

[0024]

As described above, when the video signal of the NTSC system is stored in the video signal memory in the component system, the sampling frequency of the chrominance signal is set lower than that of the luminance signal. Since the amount of data is reduced, there is a problem that the address control of the memory and the timing of writing and reading must be performed for each of the luminance signal and the chrominance signal.

For this reason, there has been a problem that the circuit configuration becomes complicated and the circuit scale becomes large. That is, according to the configuration of FIG. 5, two write pulse generation circuits 131 and 132 having different frequencies, write address generation circuits 133 and 134, and read pulse generation circuits 116 and 11 are provided.
7. The read address generation circuits 114 and 115 are required.

The sampling frequency of the luminance signal is
Since the sampling frequency of the chrominance signal is set higher than, for example, twice, the writing and reading pulse generation circuit for the luminance signal, the writing and reading address generation circuit, and the like are faster than those for the chrominance signal. There is a problem that the IC must be operated, and an IC that can operate at high speed is required.

An address bus is used to supply address data.
There has been a problem that it is difficult to make it.

An object of the present invention is to provide a video signal processing apparatus which can control the address of a memory and write and read timings of pixel data between a memory section for a luminance signal and a memory section for a chrominance signal. And

[0029]

According to the present invention, there is provided a video signal processing apparatus which samples a video signal from a first signal and a first signal.
A second signal having a lower frequency and a first signal .
First and second memory unit for storing pre-the second signal respectively, first stored in the first and second memory unit
Means for controlling reading of first and second signals, wherein the first and second memory units are provided.
And the sampling frequency of the first and second signals.
And the first memory unit has a plurality of
The memory section is provided with one or more memory systems, respectively.
Each of these memory systems has its own memory for storing pixel data.
And input / output of pixel data to / from memory
Timing adjustment means for controlling all the timings in the same way
The first memory unit includes a plurality of memory systems and a plurality of these memory systems.
Sampling the first signal to one of the number of memory systems
Switching based on the clock signal corresponding to the switching frequency
Switching means .

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the sampling frequency of the luminance signal is twice the sampling frequency of the chrominance signal. As a result, the amount of data formed from the luminance signal is:
This is twice the data amount formed from the color signals.

In the configuration shown in FIG. 1, an image of a subject is imaged by a lens 11 through a solid-state imaging device (hereinafter referred to as a CCD).
12 is imaged. The video signal formed by photoelectric conversion by the CCD 12 is supplied to the imaging circuit 13 under the control of the imaging circuit 13.

In the synchronizing signal generation circuit 14, a synchronizing signal is formed. The synchronization signal is supplied to an imaging circuit 13, a write sampling pulse generation circuit (hereinafter referred to as a write pulse generation circuit) 17, and a read sampling pulse generation circuit (hereinafter referred to as a read pulse generation circuit) 26.

The imaging circuit 13 controls the driving of the CCD 12 and the reading of the video signal based on the control signal from the system control circuit 80 and the synchronization signal supplied from the synchronization signal generation circuit 14. In the imaging circuit 13, the video signal supplied from the CCD 12 is separated into a luminance signal and a chrominance signal. The luminance signal is supplied to an A / D conversion circuit 19 after being subjected to predetermined signal processing in a luminance signal processing circuit 15. The color signal is a color difference signal (RY,
BY) and the color difference signals (RY, BY)
Represents the color signal processing circuit 1 alternately in units of 1H (horizontal scanning period).
6, after the predetermined signal processing, the A / D conversion circuit 2
1 is supplied.

The write pulse generation circuit 17 determines the timing of AD conversion of a luminance signal and a chrominance signal and generation of a write address based on a control signal from the system control circuit 80 and a synchronization signal supplied from the synchronization signal generation circuit 14. A clock signal for defining is formed. This clock signal is supplied to the A / D conversion circuits 19 and 21 and the write address generation circuit 18.

In the A / D conversion circuit 19, AD conversion is performed at the timing of the clock signal supplied from the write pulse generation circuit 17. That is, the analog luminance signal supplied from the luminance signal processing circuit 15 is digitized and converted into pixel data. This pixel data is supplied to the luminance signal memory unit 20.

In the A / D conversion circuit 21, AD conversion is performed at the timing of the clock signal supplied from the write pulse generation circuit 17. That is, the analog color signal supplied from the color signal processing circuit 16 is digitized and converted into pixel data. This pixel data is supplied to the color signal memory unit 22.

In the write address generation circuit 18, a write address is formed based on a clock signal supplied from the write pulse generation circuit 17. The write address and the write clock signal are stored in the luminance signal memory unit 20.
And the color signal memory unit 22.

FIG. 2 shows the configuration of the luminance signal memory section 20 and the chrominance signal memory section 22. In FIG.
The luminance signal memory unit 20 includes a first memory system 55 and a second memory system 56. Since the sampling frequency of the luminance signal Y is twice the frequency of the color signal C as described above, the clock signal for writing and reading the pixel data is originally twice the frequency of the color signal clock signal. It is necessary to

However, in one embodiment, the luminance signal memory section 20 and the chrominance signal memory section 2 are provided by providing the two memory systems described above in the luminance signal memory section 20.
2 can be written and read with a clock signal of the same frequency.

As will be described later, the first memory system 55
It is provided to hold pixel data having an odd pixel number. The first memory system 55 includes a memory 43
And a latch 42 arranged at the preceding stage of the memory 43 and connected to the switch 41, and a latch 44 arranged at the succeeding stage of the memory 43 and connected to the switch 45. The connection state of the switches 41 and 45 is switched at the timing when each pixel data is supplied. For example,
In the switch 41, the connection between the terminal 41a and the terminal 41b or the terminal 41c is switched for each pixel.

As will be described later, the second memory system 56
It is provided for holding pixel data having an even pixel number. The second memory system 56 includes a memory 47
And a latch 46 arranged at the preceding stage of the memory 47 and connected to the switch 41, and a latch 48 arranged at the succeeding stage of the memory 47 and connected to the switch 45.

As will be described later, the delay amount of the latch 42 is set to be larger than that of the latch 46 by one clock of the system clock CKS in order to make writing timings to the memories 43 and 47 the same. As a result, the latch 4
The output timings of 2, 46 are the same. In addition, since the pixel data simultaneously read from the memories 43 and 47 are output in time series in the order of the pixel numbers, the delay amount of the latch 48 is larger than that of the latch 44 by one clock of the system clock CKS. . As a result, the latch 4
The output timing from 4, 48 is controlled.

Therefore, the pixel data of the luminance signal is stored in the memory 4 of the luminance signal memory unit 20 at the same timing.
The pixel data written to the memory cells 3 and 47 and read out from the memories 43 and 47 at the same timing are output from the luminance signal memory unit 20 in time series in the order of the pixel numbers.

In FIG. 2, the color signal memory section 22 comprises:
A memory 52, a latch 51 provided in a stage preceding the memory 52, and a latch 5 provided in a stage subsequent to the memory 52;
3 mainly. Since the sampling frequency and data amount of the color signal are (1/2) compared to the luminance signal, the memory capacity is also (1/2). The latches 51 and 5 provided in the color signal memory 22 are provided.
Reference numeral 3 is provided for synchronizing and synchronizing the timing with the luminance signal passing through the luminance signal memory unit 20.

The read pulse generation circuit 26 performs D / A conversion of the luminance signal and the chrominance signal and the timing of the read address based on the control signal from the system control circuit 80 and the synchronization signal supplied from the synchronization signal generation circuit 14. Are formed. The clock signal generated by the read pulse generation circuit 26 is
D / A conversion circuits 28 and 31, read address generation circuit 2
4 is supplied.

The read address generation circuit 24 generates a read address for a luminance signal and a color signal based on the clock signal supplied from the read pulse generation circuit 26. This read address is supplied to the memories 43, 47, and 52 via the terminal.

The pixel data of the luminance signal Y read from the luminance signal memory section 20 is supplied to a D / A conversion circuit 28 via a terminal 39, and the color signal read from the color signal memory section 22 is supplied. The pixel data of C is supplied to D through terminal 40.
/ A conversion circuit 31.

In the D / A conversion circuit 28, the pixel data of the luminance signal Y is converted into an analog luminance signal based on the timing of the clock signal supplied from the read pulse generation circuit 26. This analog luminance signal is subjected to FM modulation by an FM modulation circuit 29. The luminance signal subjected to the FM modulation is supplied to the adder 30.

In the D / A conversion circuit 31, the pixel data of the color signal C is converted into an analog color signal C based on the timing of the clock signal supplied from the read pulse generation circuit 26. The analog color signal C is subjected to FM modulation by the FM modulation circuit 32. The color signal C that has been subjected to the FM modulation is supplied to the adder 30.

The adder 30 adds the FM-modulated luminance signal and color signal C to form a video signal. This video signal is supplied to the magnetic head 61 via the recording amplifier 33.

The system control circuit 80 is a conventionally known microcomputer for controlling the entire system.
U, ROM and RAM. The system control circuit 80 is connected to an operation unit 81 having various operation switches and a display unit 82 for displaying a camera setting state and the like.

The magnetic disk 62 is driven to rotate by a spindle motor 63 controlled by a spindle servo circuit 64. The spindle servo circuit 64 rotates the spindle motor 63 at a constant rotation speed (for example, 3600 rpm) based on the control of the system control circuit 80.

The spindle motor 63 is provided with an FG pulse generator 65, which detects the rotation period of the magnetic disk 62 and supplies this detection signal to the spindle servo circuit 64. The PG coil 66 detects the rotation timing of the magnetic disk 62 and supplies the detection signal to the spindle servo circuit 64.

The magnetic head 61 includes a tracking motor 7
The magnetic disk 62 is displaced in the radial direction by 0, and the tracking motor 70 is controlled by the system control circuit 80 via the tracking motor drive circuit 71. That is, while the magnetic disk 62 is rotating, the magnetic head 61 is positioned on a predetermined track of the magnetic disk 62, and records a video signal and an ID code on this track.

Next, the writing and reading operations of pixel data in the luminance signal memory section 20 and the chrominance signal memory section 22 will be described with reference to FIGS. In addition,
In this specification, Y, YA, YB, and YC represent luminance signals, and C and CA represent chrominance signals. ADW represents a write address of a luminance signal and a write address of a chrominance signal, respectively.
R represents a read address of a luminance signal and a color signal. Further, T1 to T12 shown in the drawing indicate delay amounts depending on the characteristics of the elements. The delay amounts T1 to T1
T12 is assumed to be the same delay amount for convenience of explanation.

First, the timing and operation of writing pixel data in the luminance signal memory section 20 and the chrominance signal memory section 22 will be described with reference to FIGS. FIG. 3A shows the system clock CKS.
C, FIG. 3D shows a clock signal CKS2 formed by dividing the system clock CKS to a frequency of (１ ／).
CKS3 is shown. FIG. 3J shows the write address ADW.

The above-mentioned system clock CKS is used for setting the timing when inputting / outputting the pixel data of the luminance signal to / from the luminance signal memory unit 20, and setting the timing for switching the switches 41 and 45. In addition, in the timing setting inside the luminance signal memory unit 20, or the input / output of the pixel data of the color signal to / from the color signal memory unit 22 and the timing setting inside the color signal memory unit 22, (1/1 / the system clock CKS) Clock signals CKS2 and CKS3 having the frequency of 2) are used. Therefore, the first and second memory systems 55,
56 systems are provided.

As shown in FIG. 3B, at the timing of the system clock CKS from time t1, the terminal 3 in FIG.
5, a luminance signal Y is supplied. For example, the pixel data of the luminance signal Y of the pixel number 1 is supplied between the time points t1 and t3, and the pixel data of the luminance signal Y of the pixel number 2 is supplied between the time points t3 and t5. Hereinafter, similarly, pixel data is supplied serially for each pixel.

This luminance signal Y is output from the system clock CK.
A switch 41 whose connection state is controlled at the timing of S distributes and supplies the data to the latches 42 and 46 for each pixel. Between the time points t1 and t3, the terminals 41a and 41b
Is connected, the pixel data of the above-described pixel number 1 is taken into the latch 42 and supplied to the memory 43. The state captured by the latch 42 is shown in FIG. 3E.

As described above, the latch 42 has a delay amount larger than that of the latch 46 by one clock of the system clock CKS, in other words, by (（) clock of the clock signals CKS2 and CKS3. Therefore,
The timing at which the pixel data captured by the latch 42 can be output is set to coincide with the output timing of the pixel data having an even pixel number as shown in FIG. 3G.

The connection state of the switch 41 is controlled at the timing of the system clock CKS. Since the terminals 41a and 41c are connected between the time points t3 and t5, the pixel data of the pixel number 2 is taken into the latch 46 and the memory 47. The state captured by the latch 46 is shown in FIG. 3F.

From time t5 to time t9, the odd-numbered pixel data shown as the luminance signal YC in FIG. 3G is at the same timing as the even-numbered pixel data shown as the luminance signal YB in FIG. 3F. Latch 42, 4
6 is output. The pixel data output from the latch 42 is stored in the memory 43 and the pixel data output from the latch 46 is stored in the memory 47 between the time points t5 and t9.
At the same time, the clock signal CKS3 is fetched during the high level period.

On the other hand, as shown in FIG.
, The color signal C is supplied to the latch 51 via the terminal 36 in FIG. 2 in synchronization with the rise of the clock signal CKS2. For example, the pixel data of the color signal C of the pixel number 1 is
It is supplied at the timing of time t1. Between the time points t1 and t5, the data is taken into the latch 51 in synchronization with the rise of the clock signal CKS2, and is supplied to and taken into the memory 52 between the time points t5 and t9. FIG. 3I shows a state where the pixel data of the color signal C of the pixel number 1 is output from the latch 51 and taken into the memory 52.

As shown in FIGS. 3F, 3G, and 3I, the luminance signal memories 43 and 47 and the chrominance signal memory 52 store the luminance signal YB and YC pixel data and the chrominance signal CA pixel data at the same timing. Respectively.

Next, the operation of reading pixel data in the luminance signal memory section 20 and the chrominance signal memory section 22 will be described with reference to FIGS. FIGS. 4A and 4B show clock signals CKS2 and CKS3 formed by dividing the system clock CKS to a frequency of (１ ／). FIG. 4C shows the read address ADR.
It is shown. This read operation is performed in the memory 4
This is performed after writing to 3, 47 and 52 is completed.

The pixel data of the luminance signal is read from the memories 43 and 47 based on the read address ADR supplied from the time point t1 in FIG. 4C and supplied via the terminal 38 in FIG. Reads pixel data of a color signal.

Pixel data having an odd-numbered pixel number, for example, 1 is read from the memory 43 in synchronization with the rise of the clock signal CKS2. This pixel data is
This is shown in FIG. 4D as a luminance signal YA. This FIG. 4D
Is input to the latch 44.
The pixel data of the luminance signal YA having the pixel number 1 is supplied to the terminal 45b of the switch 45 between the time points t1 and t5.

Pixel data having an even-numbered pixel number, for example, 2, is read from the memory 47 in synchronization with the rising edge of the clock signal CKS2. This pixel data is
This is shown as a luminance signal YB in FIG. 4E. This FIG. 4E
The luminance signal YB shown in FIG.

As is apparent from FIGS. 4D and 4E, the luminance signals YA and YA read from the luminance signal memories 43 and 47, respectively.
YB is synchronized with the latches 44 and 4 at the same timing.
8. By the way, as described above, the delay amount of the latch 48 is longer than that of the latch 44 by the system clock CK.
It is increased by one S clock.

Accordingly, as shown in FIG. 4G, the timing at which the pixel data captured by the latch 48 can be output is (1) of the clock signals CKS2 and CKS3.
/ 2) Times t3 to t7 later by the clock. That is, as can be seen by comparing FIGS. 4D and 4G, the pixel data of the even-numbered pixel number is (）) of the clock signals CKS2 and CKS3 more than the pixel data of the odd-numbered pixel number.
The output is delayed by the clock. Thus, the latch 48
Thereafter, the pixel data of the luminance signal YC having the pixel number of 2 is output between the time points t3 and t7 and supplied to the terminal 45c of the switch 45.

FIG. 4F shows the pixel data of the color signal C read from the memory 52. The color signal C shown in FIG. 4F
Is supplied to the latch 53 and is taken in. The latch 53 is delayed by (１ ／) clock of the clock signals CKS2 and CKS3, and as shown in FIG.
Between time points t3 and t7, the pixel data of the color signal C having the pixel number 1 is extracted from the output terminal 40 of the color signal memory unit 22.

The connection state of the switch 45 is controlled at the timing of the system clock CKS. For example, the terminals 45a and 45b are connected between time points t2 and t4 in FIG.
The terminals 45a and 45c are connected between the time points t4 and t6. Therefore, from the output terminal 39 of the luminance signal memory unit 20, as shown in FIG.
Between 4, the luminance signal Y having the pixel number (1) and the time points t4 to t
The luminance signal Y having the pixel number (2) is extracted between the pixels 6. Thereafter, similarly, as shown in FIG. 4H, the pixel data is serially extracted at the timing of the system clock CKS so that the pixel numbers are in the order of odd numbers and even numbers.

In this embodiment, the luminance signal memory 2
0 is the first pixel data storing the odd-numbered pixel data.
And a second memory system 56 for storing pixel data of even-numbered pixel numbers.
Clock signals CKS2 and CKS3 obtained by dividing the system clock CKS by (1/2) can be used as clock signals for setting the timing of writing and reading, and as a result, the luminance signal memory unit 20 and the color signal In both of the signal memory units 22, the clock signals CKS2, CKS
3 can be used in common.

By increasing the amount of delay of the latch 42 by one system clock CKS as compared with that of the latch 46, pixel data can be written to the corresponding same addresses of the memories 43 and 47 at the same timing. By increasing the delay amount of the latch 48 by one clock of the system clock CKS as compared with that of the latch 44, and outputting the pixel data by the switch 45 whose connection state is controlled at the timing of the system clock CKS, the luminance signal memory unit It is not necessary to separately perform address control and address generation timing control in both the color signal memory unit 20 and the color signal memory unit 22.

[0075]

As described above, according to the present invention, it is possible to obtain the effect that the timing for writing and reading can be shared between the memory section for the luminance signal and the memory section for the chrominance signal. Further, there is an effect that an IC having a relatively slow processing speed can be used. In addition, the circuit configuration can be simplified and the circuit scale can be reduced. Further, since the number of address buses can be reduced, an effect that IC integration becomes easy can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a memory unit for a luminance signal and a memory unit for a chrominance signal;

FIG. 3 is a timing chart showing writing of pixel data in a luminance signal memory and a color signal memory.

FIG. 4 is a timing chart showing reading of pixel data in a luminance signal memory and a chrominance signal memory;

FIG. 5 is a block diagram showing a conventional video signal processing device.

[Explanation of symbols]

 13, 103 imaging circuit 20 luminance signal memory unit 22 color signal memory unit 24, 114, 115 read address generation circuit 26, 116, 117 read pulse generation circuit 41, 45 switch 42, 44, 46, 48 latch 43, 47 , Memory 51, 53 latch 52 memory 55 first memory system 56 second memory system Y, YA, YB, YC luminance signal C, CA color signal CKS system clock

Claims (2)

(57) [Claims] 1. A video signal is generated from a first signal and the first signal.
A circuit for separating the signal into a second signal having a low sampling frequency, and a first and a second signal for storing the first and second signals , respectively .
Preliminary a second memory portion, the first and it to the second memory unit
A video signal processing device and means for controlling the reading of the respectively stored first and second signals, wherein the first and second memory portions, said first and second signals
Number according to the ratio of the sampling frequency of the signal, and
The first memory unit has a plurality of the second memory units.
One or more memory systems are provided, and each of these memory systems stores a memory for storing pixel data.
And the pixel data for the memory
Timing control that controls all input / output timings identically
Has an integer unit, the first memory unit includes a plurality of said memory system, these multiple
Of the first signal to one of the memory systems
Based on the clock signal corresponding to the sampling frequency
A video signal processing device , comprising: switching means for switching . 2. The method according to claim 1, wherein the first signal is a luminance signal,
2. The signal according to claim 1, wherein the two signals are color signals.
Video signal processing device.