JP3159286B2 - VRAM drive system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Industrial application] It relates to an image processing apparatus and the like.
The present invention relates to a VRAM driving method for increasing a transfer speed from a DRAM in a RAM to a SAM.

[0002]

Conventionally, as shown in FIG. 5, A / D converter unit
Digital signal converted from video signal (Sa) by 1
(Sd) is synchronized with the synchronization signal of the video signal (Sa).
To temporarily store the video signal (Sa).
Or stored in synchronization with an asynchronous synchronization signal.
One DRAM 2a and one DRAM for reading the total signal (Sd)
VRAM drive to drive VRAM2 consisting of SAM2b
Input method in synchronization with the video signal (Sa).
A / D conversion in synchronization with an external HD signal (HDw)
A / D clock signal (CK1) used for the conversion unit 1
Clock signal generating means for A / D generated, the external H
D signal (HDw) and an internal HD signal (H
Digital signal transferred to SAM2b in synchronization with Dr)
Read clock signal (CK) for sequentially reading (Sd)
3) and a read clock signal generating means for generating, said outer
Section HD signal (HDw) and A / D clock signal (CK)
1) and the read clock signal (CK3), RAS,
And a memory drive unit for generating a signal such as CAS to drive the VRAM 2 . Then, as shown in FIG. 3, the external HD signal (HDw) and the A / D clock signal
(CK1) synchronized with the RAS and CAS signals
The digital signal (Sd) is written to the DRAM 2a pixel by pixel.
DRA in synchronization with the internal HD signal (HDr)
Refresh M2a and DRAM2a to SAM2b
Of one line of digital signal (Sd)
Section HD signal (HDr) and read clock signal (CK3)
Is read sequentially from SAM2b in synchronization with
Was. However, in this method, it is not possible to refresh the DRAM 2a in the VRAM 2 or transfer one line of data from the DRAM 2a to the SAM 2b between the end of writing one pixel data to the DRAM 2a and the start of writing the next one pixel data. As shown in FIG. 3, it is impossible to read correct data after inputting an internal HD signal (HDr) for reading, as shown in FIG.
It takes a time from the end of the transfer to the AM2b to the next transfer, that is, a write time for several pixels, during which time invalid data is read out, and the left portion of the screen is disturbed as shown in FIG. The problem arises. So, this
In order to avoid these problems , a plurality of VRAMs are used, and refresh or transfer from DRAM to SAM is performed during writing to another VRAM .

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a VRAM driving system in which invalid data of read data is reduced.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an A / D converter for converting a video signal into a video signal.
Digital signal in synchronization with the synchronization signal of the video signal
Once stored, synchronized or asynchronous with the sync signal of the same video signal
The stored digital signal is synchronized with the synchronization signal of
VRA consisting of one DRAM and one SAM to be read
A VRAM driving method for driving the M, the video signal
In synchronization with the external HD signal input in synchronization with
Clock signal generating means for A / D which generates a clock signal for A / D used for D converter, riffs said DRAM
Digital signal from RES or DRAM to SAM
And the rolling <br/> clock signal generating means for feeding for generating a transfer clock signal as a transfer timing, the other is an external HD signal
Is transferred to the SAM in synchronization with the internal HD signal input to the
Clock signal for sequentially reading the read digital signals
A read clock signal generating means for generating said external H
D signal, A / D clock signal, and transfer clock signal
Signal, the internal HD signal, and the read clock signal
S, and generates a signal CAS, etc. will be provided and a memory drive unit for driving the VRAM, the transfer clock signal
Is higher than that of the clock signal for the A / D converter.
The VRAM driving method is used as a wave number. In addition,
The frequency of the transmission clock signal is changed by the A / D clock signal.
One pixel of the digital signal as at least 16 times
After writing the data for the next pixel to the DRAM,
Time from the DRAM to the start of writing the data
VRAM drive system that can complete transfer to AM
And Further, the transfer clock signal is
/ D asynchronous with the clock signal for / D
VRAM drive system that synchronizes with signals
You.

[0005]

The VRAM according to the present invention is constructed as described above.
According to the driving method, the writing to the DRAM converts the video signal into a digital signal at the timing of A / D clock signal, until the next data write clock A / D
Refresh or transfer data from DRAM to SAM at timing of transfer clock signal higher in frequency than signal, and synchronous or asynchronous with A / D clock signal
Read out sequentially at the timing of the readout clock signal .
To shorten the time from refresh to data transfer
Reduce the number of writes during that time and include it in the read data
To reduce the amount of invalid data.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The driving method will be described in detail. FIG. 1 shows a VRA according to the invention.
FIG. 2 is a main block diagram showing an embodiment of an M drive system. In the figure, reference numeral 1 denotes an A / D converter, which receives an input video signal (S
a) is converted to a digital signal (Sd). 2 is VR
In the AM, the converted digital signal (Sd) is stored in the DRAM 2a one pixel at a time, transferred to the SAM 2b line by line, and read out one pixel at a time from the SAM 2b. Reference numeral 3 denotes a memory driving unit which is an external HD signal for writing (HD
w), an internal HD signal (HDr) for reading, and three clock signals (CK1, CK2, CK3) described later, etc., to generate signals such as RAS, CAS, and WE for driving the VRAM2. Reference numeral 4 denotes an A / D clock signal generating means for generating an A / D converter clock signal. The A / D conversion A / D clock signal (HDw) is used in synchronization with an external HD signal (HDw). CK1) has occurred. 5
Is a transfer clock signal generating means for generating a transfer clock signal (CK2) for refreshing the DRAM 2a and transferring data to the SAM 2b. This transfer channel
The clock signal (CK2) is the A / D clock signal (CK).
1) Asynchronous with A / D clock signal
(CK1) at least 16 times the frequency of the digital
Write data for one pixel of the total signal to the DRAM 2a
After the end, until writing of data for the next one pixel starts
Transfer from DRAM 2a to SAM 2b can be completed in time
I am trying to. Reference numeral 6 denotes a read clock generating means, which synchronizes with the internal HD signal (HDr) to read digital data from the SAM 2b.
A read clock signal (CK3) for reading the ground signal is generated. The transfer clock signal (CK2) is
Is synchronized with the internal HD signal (HDr).

In the above configuration, the operation will be described next.
The operation will be described with reference to a timing chart for explaining the operation of the VRAM driving method according to the present invention shown in FIG. The input video signal (Sa) is synchronized with the external HD signal (HDw) by an A / D clock signal
A / D operating in synchronization with D clock signal (CK1)
The signal is converted into a digital signal (Sd) by the
They are entered in the AM2. On the other hand, in the memory driving section 3, in addition to the external HD signal (HDw) and the A / D clock signal (CK1) synchronized therewith, the internal HD signal (HDr)
And the transfer clock in synchronization with the internal HD signal (HDr).
Clock signal (CK) generated by the clock signal generating means 5
2), RAS, CAS,
WE, TRG and other timing signals are generated.
As shown in the figure, the digital signal (Sd) input to the VRAM 2 from the timing of the external HD signal (HDw) is written to the DRAM 2a in the VRAM 2 at the timing of the A / D clock signal (CK1) pixel by pixel.
After the end of the writing, until the next writing timing, the written data in the DRAM 2a refreshes the DRAM 2a or transfers one-line data from the DRAM 2a to the SAM 2b at the timing of the transfer clock signal (CK2). One line data transferred to the SAM 2b is input by the input of the internal HD signal (HDr).
At the timing of the read clock signal (CK3), the pixels are sequentially read one pixel at a time, and a read signal (Sr) is output.

[0008]

As described above, the VR according to the present invention is used.
According to AM driving method, a write to DRAM and converts the video signal into a digital signal at the timing of A / D clock signal, until the next data write, for A / D Black
Refresh or data transfer from the DRAM to the SAM is performed at the timing of a transfer clock signal having a frequency higher than that of the A / D clock signal, and is synchronized or asynchronous with the A / D clock signal.
Since the out sequentially read at the timing of the period of the read clock signal, to shorten the time from the refresh until the data transfer
Reduce the number of writes during that time and include it in the read data
It is possible to provide a VRAM driving method in which invalid data is reduced .

[Brief description of the drawings]

FIG. 1 is a main block diagram showing one embodiment of a VRAM driving method according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the VRAM driving method according to the present invention.

FIG. 3 is a timing chart of a conventional VRAM driving method.

FIG. 4 is a diagram showing the effect of invalid data on a screen.

FIG. 5 is a main block diagram showing a conventional VRAM driving method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 VRAM 2a DRAM 2b SAM 3 Memory drive part 4 A / D clock signal generation means 5 Transfer clock signal generation means 6 Read clock signal generation means

Claims (3)

(57) [Claims] An A / D converter converts an image signal from an image signal.
Digital signal synchronized with the synchronization signal of the video signal.
To temporarily store and synchronize or unsynchronize with the synchronization signal of the same video signal.
The digital signal stored in synchronization with the synchronization signal of the
Consisting of one DRAM and one SAM for reading data
A VRAM driving method for driving AM, which is synchronized with an external HD signal input in synchronization with the video signal.
A / D clock signal used in the A / D converter
A / D clock signal generating means for generating a signal , and refreshing of the DRAM or SAM from the DRAM.
Clock for transfer of digital signals to the
Transfer clock signal generating means for generating a clock signal, and an internal HD signal input separately from the external HD signal.
Digital signals transferred to the SAM
Read clock signal generating means for generating a read clock signal for reading, an external HD signal, an A / D clock signal,
RAS, C from the clock signal and the read clock signal
It generates a signal AS such as would be provided and a memory drive unit for driving the VRAM, the frequency of the transfer clock signal the A / D converter
V characterized by having a higher frequency than the clock signal.
RAM drive system. Wherein the frequency of the transfer clock signal, before
The A / D clock signal is at least 16 times
The transfer from the DRAM to the SAM can be completed in the time from the end of writing the data for one pixel of the digital signal to the DRAM until the start of writing the data for the next one pixel.
2. The VRAM driving method according to claim 1, wherein Wherein said transfer clock signal, the A / D
Clock signal for reading and the clock signal for reading
2. The VRAM driving method according to claim 1, wherein the VRAM driving method is synchronized with the VRAM.