JP2001054018A - Driving method for solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a frame rate without reducing dealing charge quantity of a vertical CCD(charge coupled device) at the time of transferring plural lines in one horizontal synchronous period. SOLUTION: In a waveform drawing showing horizontal synchronous timing of a CCD solid-sate image pickup element, a thinning mode is displayed and signal charges are verticality transferred for two lines in one horizontal synchronous period. It is characteristic that an overlap period of respective phases of a vertical transfer clock is taken to be long so that dealing charge quantity is not reduced since plural lines are given. It is preferable that the timing is adjusted to be substantially similar to that at the time of a regular mode when one line is vertically transferred. CLK shows a waveform of a master clock, HD the waveform of a horizontal synchronizing signal (one period), Hϕ1 the waveform of a horizontal CD driving cock, and Vϕ1, Vϕ2 and Vϕ3 the waveforms of the vertical CCD driving clock (three phase transfer driving).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CCD (Charge C)
The present invention relates to a solid-state imaging device, and more particularly, to a method of driving a solid-state imaging device with an improvement in signal drive timing when transferring two or more lines of signal during one horizontal synchronization period.

[0002]

2. Description of the Related Art A CCD solid-state imaging device may be provided with a mode in which two or more lines (line means a scanning line) are vertically transferred in one horizontal synchronization period with respect to driving timing of an imaging signal. . As a result, the readout rate can be increased by making full use of techniques such as thinning out vertical pixels and adding horizontal pixels.

FIGS. 6 and 7 are waveform diagrams showing the horizontal synchronization timing of a general CCD solid-state imaging device.
Each has a vertical transfer overlap period in a horizontal blanking period, and FIG. 6 shows a normal mode and FIG. 7 shows a thinning mode. In each figure, CLK is a master clock, HD is a horizontal synchronization signal (one cycle), and Hφ1 is a horizontal CC.
D drive clock, Vφ1, Vφ2, Vφ3 are vertical CCD
3 shows a waveform of a driving clock (three-phase transfer driving).

[0006] As shown in FIGS. 6 and 7, a vertical blanking period is fixed, and vertical transfer timing is created. For this reason, when the signal charges are transferred in two lines as in the thinning mode in FIG. 7, the transfer time is reduced to half as compared with the case where one line is transferred in the overlap period of the vertical transfer clock in FIG.

[0005]

FIG. 8 is a characteristic diagram showing the dependence of the signal charge handling amount of the vertical CCD on the vertical transfer clock overlap period in the solid-state imaging device. As shown, as the vertical transfer time becomes shorter, the dynamic range of the vertical transfer section decreases. That is, as the frame rate (readout rate) is improved, the amount of electric charges handled by the vertical CCD decreases.

As described above, in the solid-state image pickup device, when the vertical transfer time given by the overlap period of the vertical transfer clock is shortened, the amount of electric charges handled by the vertical CCD is reduced at present. As a result, the dynamic range over of the vertical transfer unit may occur.

For this reason, when the rate is increased beyond the normal frame rate (reading rate), there is no way to normally secure the dynamic range of the vertical transfer unit only by reducing the saturation signal amount of the electric charge to be handled. .

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to reduce the amount of charge handled by a vertical CCD when transferring a plurality of lines during one horizontal synchronization period with respect to the driving timing of an image signal. An object of the present invention is to provide a driving method of a solid-state imaging device capable of improving a frame rate without reducing the frame rate.

[0009]

According to the method of driving a solid-state image pickup device of the present invention, a signal charge of each light receiving unit is obtained from a vertical transfer unit provided for each vertical column of a plurality of light receiving units arranged on a matrix. The driving of the solid-state imaging device in which the signal charges transferred in accordance with the vertical synchronization timing and the transferred signal charges are transferred to the output unit in accordance with the horizontal synchronization timing in the horizontal transfer unit, wherein the signal charge is transferred in one horizontal synchronization period according to the horizontal synchronization timing Is characterized in that in a mode in which a plurality of lines are vertically transferred, a period in which vertical transfer can be performed for a longer time than in a normal mode in which a single line is vertically transferred in one horizontal synchronization period is provided.

Further, according to the driving method of the solid-state image pickup device of the present invention, the signal charges of the respective light receiving units are changed in accordance with the vertical synchronization timing by the vertical transfer units provided for each of the vertical columns of the plurality of light receiving units arranged on the matrix. The driving of the solid-state imaging device in which the transferred signal charges are transferred to an output unit in accordance with horizontal synchronization timing in a horizontal transfer unit, wherein the signal charges are vertically transferred by a plurality of lines in one horizontal synchronization period according to the horizontal synchronization timing. In the transferred mode, the overlap period of each phase of the vertical transfer clock based on the vertical synchronization timing is substantially the same as that in the normal mode in which a single line is vertically transferred in one horizontal synchronization period.

According to the method of the present invention, in the mode in which the signal charges are vertically transferred by a plurality of lines in one horizontal synchronization period, the overlap period of each phase of the vertical transfer clock is handled by the number of lines to be handled. Is long so that it does not decrease, and is preferably substantially the same as in the normal mode in which the single line is vertically transferred.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a CCD solid-state imaging device to which a method according to an embodiment of the present invention is applied, a three-phase transfer driving device having the following specifications will be used. Horizontal invalid pixel + horizontal dummy + horizontal blanking = 60 vertical effective pixel = 480 vertical invalid pixel + vertical dummy + vertical blanking = 4 horizontal drive frequency = 14 MHz 1 horizontal synchronization bit number = 700 bits ((1/14) ×
700 = 50 μsec) 1 number of vertical lines = 484 lines Frame rate = 41.3 frames / sec

FIG. 1 shows the CC according to the embodiment of the present invention.
FIG. 4 is a waveform chart showing horizontal synchronization timing of a D solid-state imaging device. This embodiment shows a thinning mode, in which signal charges are vertically transferred by two lines in one horizontal synchronization period. Characteristically, the overlap period of each phase of the vertical transfer clock is set to be long so that the amount of handled electric charges does not decrease by the number of lines. If possible, it is preferable to adjust the timing substantially the same as in the normal mode in which one line is vertically transferred. That is, the horizontal blanking period is made longer than in the normal mode.

In FIG. 1, CLK is a master clock, HD is a horizontal synchronizing signal (one cycle), and Hφ1 is a horizontal CC.
D drive clock, Vφ1, Vφ2, Vφ3 are vertical CCD
3 shows a waveform of a driving clock (three-phase transfer driving).

A description will be given of the vertical synchronization timing which is a premise to which the features of the above embodiment are applied. 2 and 3 are waveform diagrams showing vertical synchronization timing of the CCD solid-state imaging device. FIG. 2 shows a normal mode for reading out all pixels,
FIG. 3 shows a thinning mode that is read by thinning transfer. In each figure, VD indicates a vertical synchronizing signal (one cycle is one frame), Vφ1, Vφ2, and Vφ3 indicate a vertical CCD drive clock (three-phase transfer drive), and CCDout indicates a read timing transferred to an output unit.

The normal mode shown in FIG. 2 is a method of reading all 480 vertical pixels in one frame, as shown in the CCD readout image of FIG. On the other hand, in the thinning mode in FIG. 3, as shown in the CCD reading image of FIG.
Only two of the 480 vertical pixels are read out of four pixels. In other words, this method is to vertically transfer the pixels to be read and the pixels not to be read as one packet to double the frame rate. That is, two vertical transfers are performed during one horizontal synchronization period.
(See FIG. 1).

In the conventional method, the horizontal blanking period is fixed to 60 bits as shown in FIGS. Therefore, when the vertical transfer is performed twice, the vertical transfer clock (Vφ
The overlap period of 1 to φ3) is reduced from 10 bits during normal transfer to 5 bits. Then, as described above, the amount of electric charges handled by the vertical CCD is reduced, and there is a possibility that the dynamic range is exceeded.

In the thinning mode according to the present invention, the horizontal blanking period is not fixed as in the related art. That is, as shown in FIG. 1, for example, the horizontal blanking period is set long so that 10 bits are provided as in the normal mode vertical transfer clock overlap period shown in FIG.
As a result, thinning-out reading can be performed without reducing the amount of electric charges handled by the vertical CCD.

By applying the above-mentioned drive timing, the horizontal blanking period is reduced by two compared to FIG.
Doubled. As a result, one horizontal synchronization period at the time of thinning-out increases from 52 μsec to 54.3 μsec (conventionally, 52 μsec remains). For this reason, the frame rate is not doubled, but is 65.3 frames / sec.
It is about 1.6 times that of c.

Generally, in the normal mode, the horizontal blanking period is a, the horizontal effective pixel output period is b, the horizontal invalid pixel output period is c, the horizontal dummy pixel output period is d, and the vertical effective pixel is e. Assuming that the vertical invalid pixel + vertical dummy + vertical blanking period is f and the horizontal drive frequency is g, the time of one frame of the operation in the normal mode is expressed by equation (1). (1 / g) × (a + b + c + d) × (e + f) (1) Here, if ト ー タ ル of the total vertical pixels is thinned out,
The time of one frame at the time of thinning-out to which the drive timing of the present invention is applied can be expressed by equation (2). (1 / g) × (2a + b + c + d) × (e + f) × 1/2 (2)

On the other hand, the time of one frame in the conventional thinning can be expressed by the following equation (3). (1 / g) × (a + b + c + d) × (e + f) × 1/2 (3) However, the number of effective pixels in the horizontal direction of the CCD increases (b
Becomes longer), the ratio of the horizontal blanking period a to one horizontal synchronization period decreases. Therefore, in the thinning mode to which the drive timing of the present invention is applied, a frame rate almost twice as high as that in the normal mode can be achieved. In addition, this can be realized without reducing the amount of electric charges handled by the vertical CCD as described above.

According to the drive timing in the above embodiment, the vertical pixels of the solid-state image sensor are thinned out or the horizontal CCD is used.
This is effective when increasing the addition frame rate (readout rate). That is, when two or more lines are transferred during one horizontal synchronization period, only the horizontal blanking period of one horizontal synchronization period is set longer than during normal transfer. Thereby, the overlap period of the vertical transfer clock is sufficiently ensured. As a result, the frame rate can be increased without reducing the amount of electric charges handled by the vertical CCD. In particular, the application of the method of the present invention is useful for a multi-pixel type solid-state imaging device having a large number of effective pixels for the horizontal blanking period.

[0023]

As described above, according to the present invention,
When transferring a plurality of lines in one horizontal synchronization period, a horizontal blanking period for performing vertical transfer is set longer than in a normal operation. As a result, it is possible to provide a highly reliable driving method of the solid-state imaging device in which the overlap period of the vertical transfer clock is sufficiently secured and the dynamic range of the vertical CCD is sufficiently secured.

[Brief description of the drawings]

FIG. 1 is a waveform chart showing horizontal synchronization timing of the CCD solid-state imaging device according to the embodiment of the present invention.

FIG. 2 is a waveform diagram showing vertical synchronization timing of the CCD solid-state imaging device according to the present invention, showing a normal mode in which all pixels are read.

FIG. 3 is a waveform diagram showing vertical synchronization timing of the CCD solid-state imaging device according to the present invention, showing a thinning mode for reading by thinning transfer.

FIG. 4 shows a normal mode CC in a CCD solid-state imaging device.
It is a conceptual diagram explaining D read image.

FIG. 5 is a diagram illustrating C in a thinning mode in a CCD solid-state imaging device.
It is a conceptual diagram explaining a CD read image.

FIG. 6 is a waveform diagram showing horizontal synchronization timing of a general CCD solid-state imaging device, showing a normal mode.

FIG. 7 is a waveform diagram showing horizontal synchronization timing of a general CCD solid-state imaging device, showing a thinning mode.

FIG. 8 is a characteristic diagram showing a dependence of a signal charge handling amount of a vertical CCD on a vertical transfer clock overlap period in a solid-state imaging device.

[Explanation of symbols]

CLK: master clock, HD: horizontal synchronization signal (one cycle), Hφ1: horizontal CCD drive clock, Vφ1, Vφ
2, Vφ3: vertical CCD drive clock (three-phase transfer drive).

Claims (2)

[Claims] A signal charge of each light receiving unit is transferred from a vertical transfer unit provided for each vertical column of a plurality of light receiving units arranged on a matrix in accordance with vertical synchronization timing, and the transferred signal charge is The driving of the solid-state imaging device, which is transferred to the output unit in accordance with the horizontal synchronization timing in the horizontal transfer unit, includes:
A method for driving a solid-state imaging device, wherein a period in which vertical transfer is possible for a longer time than in a normal mode in which a single line is vertically transferred in a horizontal synchronization period is provided. 2. The signal charge of each light receiving section is transferred from a vertical transfer section provided for each vertical column of a plurality of light receiving sections arranged on a matrix according to vertical synchronization timing, and the transferred signal charge is The driving of the solid-state imaging device which is transferred to the output unit in accordance with the horizontal synchronization timing in the horizontal transfer unit, wherein the signal charges are vertically transferred in a plurality of lines in one horizontal synchronization period by the horizontal synchronization timing. A method for driving a solid-state imaging device, wherein an overlap period of each phase of a vertical transfer clock is made substantially the same as in a normal mode in which a single line is vertically transferred in one horizontal synchronization period.