JP3157750B2 - Triplet circuit and triplet processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triplet circuit for returning a triplet signal obtained by combining three pieces of data into one data in order to reduce the amount of data, and a decompression processing method thereof.

[0002]

2. Description of the Related Art Since image data of a television or the like and audio data of a CD or the like have an enormous amount of data, such data can be efficiently transmitted or recorded on a recording medium such as a magnetic tape, a magnetic disk or an optical disk. For this purpose, image signals are compressed and transmitted or recorded, and compressed data received at the receiving end or when reading a disk is expanded.

According to this kind of data compression technique, three data within a certain range is converted into one data to create data called a triplet, and the triplet data is expanded using the triplet technique, and the original data is expanded. There is a technique to return to the three types of data. This has the advantage that the data length of the triplet data combined into one is smaller than the total bit length of the three data. The triplet data is obtained by multiplying each of the three data by a different value of the power of 3 and summing them, and multiplying each of the three data by a different value of the power of 5 and summing them. The five triplets are frequently used, and the present invention will be described below using this example.

As shown in (Equation 1), the triplet 3 is obtained by multiplying 9, 9 and 3 by data M1, M2 and M3, respectively, and taking the sum. M1, M2 and M3 are each limited to values of 0, 1 or 2.

Y3 = 9 × M1 + 3 × M2 + M3 ‥‥‥ (Equation 1) As a result, the possible values of the triplet 3 are values from 0 to 26. In this case, the maximum value 26 is 5-bit data that is “11010” in binary. On the other hand, the original data 0, 1, and 2 each require 2 bits, and the three data require 6 bits. That is, the data amount of the triplet data of 3 is smaller by 1 bit.

Similarly, in the case of a triplet of 5, as shown in (Equation 2), data M is stored in 25, 5 and 1 respectively.
The sum of the values obtained by multiplying 1, M2, and M3 is calculated.

Y3 = 25 × M1 + 5 × M2 + M3 (Expression 2) In this case, M1, M2, and M3 are each 0 to 4
Limited to those with values up to. Thus, the possible value of the triplet 5 is a value from 0 to 124, which is 7-bit data. The values up to 4 allowed for M1 to M3 require 3 bits, for a total of 9 bits. In the case of a triplet of 5, the data is shortened by 2 bits.

Next, a more practical conventional triplet technique will be described with reference to the block diagram of FIG. 10 and the timing chart of the triplet shown in FIG.
This will be described with reference to a timing chart in the case of 5 triplets shown in FIG. As shown in FIG. 10, the triplet circuit includes a serial input terminal 100 for receiving triplet data in series and a triplet selection signal input terminal 10.
And 3. In response to the triplet selection signal, constant output units 102 and 107 output "-" if the triplet is three.
"3" is output to the adder circuits 105 and 110 if the triplet is "5".
In steps 05 and 110, "3" or "5" is substantially subtracted.

The triplet data from the serial input terminal 100 is sequentially taken into the shift register A101. The data of the shift register A101 is output to the constant output unit 10
The constant data from 2 is added (subtracted) by the adding circuit 105, and the result is sent to the selector 114. The borrow output a of the adding circuit 105 is applied to the serial input terminal 109 of the shift register B106. Shift register B1
The data 06 is also added (subtracted) by the adding circuit 110 to the constant data from the constant output unit 107, and the result is sent to the selector 115. The borrow output b of the adder circuit 110 is applied to the serial input terminal 112 of the shift register C111. In the case of the triplet of 3, the lower 2 bits of the shift register C111 (the lower 3 bits in the case of the triplet of 5) become the triplet result 113 of M1. From selector 115, triplet result 10 of M2
8 is the triplet result 1 of M3 from the selector 114
04 is obtained. M2, M3 triplet result 10
Each of 8 and 104 is a 2-bit value in the case of 3 triplets, and a 3-bit value in the case of 5 triplets. Next, FIG. 1 shows the case of triplet data of 3.
This will be described with reference to the timing chart of FIG. The triplet data is “01010” in binary (“1” in decimal)
0 ”). It is assumed that the constant“ −3 ”is selected from the constant output units 102 and 107 by the triplet selection signal 103.

First, each shift register 101, 106,
The content of 111 is “00000”, and data “0” is taken into the shift register 101 at timing (A). The contents of this shift register 101 "000
00 and the constant “−3” from the constant output unit 102 are added by the adder circuit 105 to obtain a result output “a” of “11101” and a borrow a of “1” When the borrow a is “1” Since "0" is input to the shift register B106, the contents of the shift register B106 do not change.

Similarly, the contents of the shift register 106 "00"
000 ”and the constant“ −3 ”from the constant output unit 107 are added to the addition circuit 110, and the result output b“ 1 ”of“ 11101 ”
Is obtained. At the time of borrow b “1”, “0” is input to the shift register C111, so that the contents of the shift register C111 do not change.

Next, at timing (B), data "1"
Is input to the shift register A101, but the addition circuit 1
The outputs of 05 and 110 are "11110", and the borrow is "1".
Therefore, since "0" is input to the shift registers B106 and C111, the contents of the shift registers B106 and C111 do not change.

Next, at timing (C), data "0" is input to the shift register A101, and the output of the adder circuits 105 and 110 is "1" as in timing (B).
1111 "and borrow are" 1 ", so that the contents of the shift registers B106 and C111 do not change.

Next, at timing (D), data "1" is input to the shift register A101. As a result, the content of the shift register A101 becomes “00101”, the result output a of the adder circuit 105 becomes “00010”, and the borrow a
Becomes “0”. Also, borrow a at timing (C)
And the borrow b are “1”, the shift register B1
06, the contents of C111 do not change.

Next, at timing (E), since the borrow a at timing (D) is "0", the result a "00010" of timing (D) is shifted by one bit to the left and data "0" is shifted into the shift register A101. And becomes “00100”. Similarly, since the borrow a at the timing (D) is “0”, “1” is inverted and “1” is also taken in the shift register B106 to “000”.
01. The result output b of the addition circuit 110 is “111”.
10 ", borrow b becomes" 1 "and shift register C1
The content of 11 does not change.

Next, at the timing (F), there is no valid data because the data of the triplet of 3 is 5 bits. The shift register A101 captures the data at the timing (E) of the shift register B106 without shifting. As a result, the result output a of the addition circuit 105
Is "11110" and borrow a is "1". The shift register B106 sets “0” of the borrow a at the timing (E).
Is obtained as "00011" by inverting "1", the result output b of the adder circuit 110 becomes "0000".
0 and the borrow b are “0.” At the next timing (G), the shift register B 106 captures the result output b (“00000”) at the next timing (G).
The shift register C111 takes in “1”. The value of the shift register A101 at this timing (F) becomes the triplet result M3.

At timing (G), the shift register A1
01 is shifted to “00011” by “1” of the borrow a at the timing (F). Shift register B10
6, C111 is “00000”, “000” as described above.
01 ", the shift registers B106 and C
The value of 111 is the triplet M2, M1.

The above is the case of triplet 3,
5 can be processed in the same manner. This timing chart is shown in FIG. The difference between the triplet and the triplet is that the constant output of the constant output units 102 and 107 is "-5" by the triplet selection signal 103, and the timing is eight clocks from (A) to (H). Others can be considered in the same manner as in the case of the triplet 3, and the detailed description is omitted.

[0019]

In such conventional triplet processing, triplet data is fetched serially into a shift register, so that it takes a long time to use a clock longer than the data length of the triplet data. For this reason, in the examples of FIGS. 11A and 11B, the processing time of 7 clocks is required in the case of the triplet, and the processing time of 8 clocks is required in the case of the triplet.

Further, even when the triplet data is over a predetermined range (27 or more for triplet 3 and 125 or more for triplet 5), the triplet data is decompressed, resulting in an erroneous output. become. In order to prevent this, it is necessary to provide a circuit for determining the value of the triplet data in advance, but there is a disadvantage that the circuit scale for this becomes large and the processing time becomes long. In particular, the processing time cannot be determined until after all the triplet data has been fetched. Therefore, the time required to fetch all the triplet data before the decompression processing in FIG. 11 is required, so that the processing time is twice or more.

As shown in the circuit block of FIG. 10, the conventional circuit requires three shift registers.
There is a disadvantage that the circuit scale becomes large.

[0022]

According to the present invention, there is provided a data input section for receiving triplet data, and a data for selecting data to be output selected by a triplet selection signal with the data of the data input section as one input. A selector, a constant output unit that receives a triplet selection signal and outputs a constant corresponding to the triplet data, and subtracts the output of the data selector from the output constant of the constant output unit,
An arithmetic means for outputting the subtraction value and the borrow data, and a decoder for receiving the output of the data selector and the subtraction value and the borrow data of the arithmetic means, outputting a triplet result and supplying data to the other input of the data selector. To obtain a triplet circuit.

The constant output section outputs a negative constant, and the arithmetic means may be constituted by an adder circuit. Further, an error detection unit for determining whether or not the triplet data is within a normal range from the triplet data and the triplet selection signal of the data input unit can be provided. The error detection unit may output a constant for determination from the constant output unit and obtain an error detection signal from the output of the arithmetic unit.

[0024]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an outline of an embodiment of the present invention. The triplet data is input from the data input unit 1 in parallel. The triplet selection signal is input from the terminal 5 and supplied to the selector 2 and the constant output unit 6. A plurality of predetermined negative constants are output from the constant output unit 6 and provided to the calculation means. This negative constant will be described later in more detail with reference to FIG. The selector 2 operates in accordance with the triplet selection signal.
And the output from the selector / decoder 3 with priority order is output. The output of the selector 2 is supplied to the arithmetic means 7 and the selector /
It is provided to the decoder 3 in parallel. The arithmetic means 7 subtracts each data from the constant output unit 6 from the data from the selector 2 and outputs the result of the subtraction and a borrow. The selector / decoder 3 with priority order receives the output from the selector 2, the subtraction result from the operation means 7, and the borrow, and outputs a triplet result M3 and a triplet result M2, 1 from output terminals 4, 8. The relationship between the input data and the output terminals 4 and 8 is as shown in FIG. 7, and will be described later in more detail with reference to FIG. The data 11 of the output terminal 4 of the selector / decoder 3 with priority order is returned to the other input terminal of the selector 2 in parallel.

FIG. 2 shows an embodiment further comprising an error detecting section 9 for detecting that the triplet data is a predetermined number or more of erroneous data and an output terminal 10 thereof. This wiring indicates a functional operation, and does not indicate that the error detection unit 9 must be provided separately from the triplet circuit. In fact, as shown in FIG.
Under the control of the triplet selection signal, a constant output for error detection may be output from the constant output unit, and the output of the arithmetic means may be determined to output an error detection signal.

Here, the principle of the present invention will be described. In the present invention, the triplet data value and the triplet result M
The fact that the relationship with 1, M2, and M3 is a specific relationship is used. FIG. 6 shows the relationship between the triplet data value and the triplet results M1, M2, and M3 in the case of three triplets. That is, as shown in equation (1), if the triplet result M1 is "0", the value of the triplet data is "0" to "8", and if the triplet result M1 is "1", the triplet data is "3". Are "9" to "17", and the triplet result M1
Is "2", the value of the triplet data is "18" to "26". Therefore, if the triplet result M1 is "0", the value of the triplet data is set to "9", "1".
Even if the subtraction is performed by either “8” or “27”, a borrow will occur.If the triplet result M1 is “1”, the borrow will not be established if the value of the triplet data is subtracted by “9”, but “18”. If the triplet result M1 is "2", if the value of the triplet data is subtracted by "9" and "18", no borrow will occur, but "27". A borrow will be made if you draw with.
Therefore, the triplet result M1 can be known by looking at the state of the borrow by pulling the triplet data by "9", "18" and "27".

If the triplet result M1 is determined, the value obtained by subtracting the value obtained by multiplying the triplet result M1 by "9" from the triplet data is (3.times.M2 + M1). Takes a value from “0” to “8”. Therefore, if the triplet result M2 is "0", a borrow will occur even if the value of the triplet temporary data is subtracted by any of "3", "6", and "9". Triplet result M2 is "1"
Then, if the value of the triplet temporary data is subtracted by "3", a borrow will not stand, but if it is pulled by "6" and "9", a borrow will stand. If the triplet result M2 is "2", a borrow will not stand if the value of the triplet temporary data is subtracted by "3" and "6", but a borrow will stand if it is pulled by "9". Therefore, the triplet temporary data is changed to “3”.
The triplet result M2 can be known by looking at the state of the borrow by pulling with "6" and "9". When the triplet result M2 is known, a value obtained by subtracting a value obtained by multiplying the triplet result M2 by "3" from the triplet provisional data becomes a triplet result M3.

Although the relationship between the triplet data and the triplet results M0, M1, and M2 for the triplet 3 has been described above, the same can be said for the triplet 5. In this case, the values to be subtracted to obtain the triplet result M1 are “25”, “50”, “75”, “10”.
The values to be subtracted to obtain the triplet result M2 (the triplet result M3 is also obtained) are "5", "10", "15", "20", and "25".

According to the present invention, the constant output unit 6
And the operation of the selector / decoder 3 with priority order. The triplet results M1, M2, and M3 are obtained from each triplet data in two operations, and the relationship between the value of the triplet selection signal and the triplet results M1, M2, and M3 is as shown in FIG. The value of the constant output unit 6 is determined by the triplet selection signal, and is as shown in FIG. The triplet select signals "0" and "1" are for a triplet, and the triplet select signals "2" and "3" are for a triplet. In addition,
If a borrow occurs when the triplet data of No. 3 is pulled by "27", it is an error, and the values of the constant e for the triplet selection signals "0" and "1" are "-27" and "-".
9 "is for detecting this error. Similar error detection for the triplet of 5 is performed by separately detecting a constant e as shown in the embodiment of FIG.

The relationship between the operation of the selector / decoder 3 with priority and each borrow is shown in FIG. Borrow a,
When b, c, d, and e are all “1”, the triplet result M1 (or triplet result M2) becomes “0”, and “0” is output to the terminal 8. The triplet data at that time (result a in FIG. 3) is output to the terminal 4. When only the borrow a is “0” and the others are “1”, the triplet result M1 (or the triplet result M2) becomes “1”, and “1” is output to the terminal 8. A value obtained by subtracting the constant a in FIG. 3 from the triplet data at that time (result b in FIG. 3) is output to the terminal 4. When the borrows a and b are "0" and the others are "1", the triplet result M1 (or the triplet result M2) becomes "2" and "2" is output to the terminal 8. A value obtained by subtracting the constant b in FIG. 3 from the triplet data at that time (result c in FIG. 3) is output to the terminal 4.
For triplet 3 above, triplet result M
1, M2, and M3 are determined. In the case of a triplet of 5, borrows a, b, and c are further "0" and others are "1".
And the case where only the borrow e is “1” is required.
When only borrows a, b, and c are "0", the triplet result M1 (or triplet result M2) becomes "3",
"3" is output to the terminal 8. A value obtained by subtracting the constant c in FIG. 3 from the triplet data at that time (result d in FIG. 3) is output to the terminal 4. When only the borrow e is “1”, the triplet result M1 (or the triplet result M2) becomes “4”, and “4” is output to the terminal 8. Terminal 4
Is a value obtained by subtracting the constant d in FIG. 3 from the triplet data at that time (result e in FIG. 3). When all borrows are "0", an error occurs.

Next, a more specific embodiment of the triplet circuit according to the present invention will be described with reference to FIG. 3 and FIGS.

The triplet data is input from the data input unit 20 in parallel. The input terminal 23 is supplied with a triplet selection signal. "0", "1", "2", and "3" are sequentially applied as triplet selection signals. The triplet selection signal is supplied to a constant output unit 22 to output a plurality of predetermined negative constants. The relationship between the predetermined negative constant and the value of the triplet selection signal is as shown in the constant output unit 22 of FIG. The addition circuit 25 has 5
Adders are provided, and the constants a,
b, c, d, e and data from the selector 21 are given, and the addition (substantial subtraction) of these is performed, and the subtraction results b, c, d, e and borrows a, b, c, d, e Is given to the selector / decoder 28 with priority. At this time,
The output of the selector 21 is given as it is as the subtraction result a. The prioritized selector / decoder 28 outputs the triplet result M3 to the output terminal 26 and the triplet results M2 and M1 to the output terminal 27 according to the values of the borrows a, b, c, d and e.

As described with reference to FIG. 7, when the borrows a to e are all "1", the operation of the priority-ordered selector / decoder 28 is such that the feedback signal 24 or the feedback signal 24 to the selector 21 is output to the output terminal 26. The subtraction result a which is the output itself from the selector 21 is output as the triplet result M3, and “0” is output to the output terminal 27 as the triplet results M2 and M1. Similarly, borrows a to e are “01”
111 ", the output terminal 26 (triplet result M3
, Etc.), and “1” is output as the output terminal 27 (triplet results M2, M1). Borrow a ~
If e is “00111”, the subtraction result c is output as the output terminal 26 (triplet result M3 and the like), “2” is output as the output terminal 27 (triplet result M2 and M1), and borrows a to e are “00011”. For example, the subtraction result d as the output terminal 26 (triplet result M3 and the like) and the output terminal
7 (triplet result M2, M1), if borrows a to e are "00001", subtraction result e as output terminal 26 (triplet result M3 etc.) and output terminal 27 (triplet result M2, M1) ) Is output as "4". If all of the borrows a to e are "0", it is determined that an error has occurred.

The output values of the output terminals 26 and 27 of the selector / decoder 28 with priority order are the triplet results M3 and M
Which one of M1 and M2 depends on the value of the triplet selection signal as described with reference to FIG. When the triplet selection signal is "0", the triplet result M1 of the triplet is output to the output terminal 27, and the value of the output terminal 28 is only returned to the selector 21 via the line 24.
When the triplet selection signal is “1”, the triplet result M2 of the triplet is output to the output terminal 27, and the triplet result M3 of the triplet is output to the output terminal. Therefore, in order to obtain a triplet result of triplet data, the triplet selection signal is set to "0".
And "1" twice and the triplet results M3, M2, M
You will get 1.

In the case of the triplet of 5, "2" and "3" are selected as the triplet selection signal. When the triplet selection signal is "2", the triplet result M1 of the triplet is output to the output terminal 27, and the value of the output terminal 26 is only returned to the selector 21 via the line 24. When the triplet selection signal is "3", the triplet result M2 of the triplet 5 is output to the output terminal 27, and the triplet result M3 of the triplet 5 is output to the output terminal 28.

The configuration and operation principle of the present invention have been described above. Next, a specific example will be described. It is assumed that the triplet data is set to 5 and the value is set to “124”. First, "2" is given to the triplet selection signal. From the constant output unit 22, "-2
5 "," -50 "," -75 "," -100 "," -1 "
25 "is output from the selector 21. The triplet data is selected from the selector 21 and supplied to the addition circuit 25. As a result, the borrow e is set to" 1 "while the borrow e is set to" 1 ". ”, And the triplet result M is output to the output terminal 27 of the selector / decoder 28 with priority.
“4” is output as 1 and the subtraction result e (a value obtained by subtracting “100” from the triplet data value, “24”) is output to the output terminal 26.

Next, the triplet selection signal is changed to "3". The output from the output terminal 26 of the selector / decoder 26 with priority order is selected as the selector 21, and “24” is added to the addition circuit 25 and the like. From the constant output unit 22, "-5", "-10", "-15", "-20", "-
25 "is output. In the adder circuit, only borrow e becomes" 1 ", and borrows a to e become" 00001. "As a result, as can be understood from FIG. The output terminal 27 outputs "4" as the triplet result M1, and the output terminal 26 outputs the subtraction result e (a value obtained by subtracting "20" from the value of the triplet data, "4"). Thus, the value of "1" can be obtained for each of the triplet results M1, M2, and M3 in two clocks, and the relationship between the operation and the clock is shown in the latter half of FIG.

In the case of the triplet, the same processing is performed, except that the value of the triplet selection signal and the output constant of the constant output section are different. The relationship between this operation and the clock is also shown in the first half of FIG. 5, and the operation ends in two clocks.

It should be noted that the detection of the case where the triplet data is "27" or more when the triplet is 3 or "125" or more when the triplet is 5 is impossible. In the present invention, it can be easily detected in the calculation process of the triplet result.
That is, in the case of the triplet 3, if the borrow c is "0" when the triplet selection signal is "0", it can be determined that an error has occurred. In the case of the triplet 5, if the borrow e is "0" when the triplet selection signal is "2", it can be determined that an error has occurred. Even when the triplet selection signal is "1" for the triplet 3 or when the triplet selection signal is "3" for the triplet 5, the error can be determined by the borrow c or the borrow e similarly. The circuit configuration for making this determination easily is shown in FIG.
It is shown in

In FIG. 4, even in the case of the triplet, 5
The borrow e is added to the error determination circuit 34 such as an inverter so that an error can be detected similarly in the case of the triplet. For this reason, in the case of the triplet, "-27" is output as the constant e when the triplet selection signal is "0", and "-9" is output as the constant e when the triplet selection signal is "1". ing. As a result, the same borrow as the borrow c appears on the borrow e. Therefore, the error of the triplet data can be determined by the error detection signal 32 which is the output value of the error determination circuit 34 regardless of whether the triplet is 3 or 5.

[0042]

According to the present invention, as described with reference to FIG. 5, the input triplet data is fetched at the first clock, the triplet result M1 is calculated, and the remaining triplet results M2 and M3 are calculated at the next clock. Is calculated, and all the triplet results M are obtained with only two clocks.
1, M2 and M3 can be calculated.

In the circuit configuration, the number of adders is 3 compared to the conventional example.
Although the number of shift registers has increased, the number of shift registers has decreased by three (the number of shift registers can be reduced by two even if a shift register is used in the input unit).
In terms of circuit scale, the number of shift registers can be reduced to be smaller than in the conventional example.

Furthermore, since an error of triplet data can be determined by the borrow value of the adder circuit (substantially subtraction), an extra processing step for error determination is not required, and the processing time becomes longer due to the error determination. There is no. Also,
Since this determination is based on whether the borrow value is logic “0”,
There is almost no increase in circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of another embodiment of the present invention.

FIG. 3 is a block diagram showing a more specific example of one embodiment of the present invention.

FIG. 4 is a block diagram showing a more specific example of another embodiment of the present invention.

FIG. 5 is a timing chart showing a processing operation according to an embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the value of triplet data and each of the triplet results M1, M2, and M3 for illustrating the principle of the present invention.

FIG. 7 is a diagram illustrating the operation of a selector / decoder with priority order according to the present invention.

FIG. 8 shows the triplet selection signal of the present invention and each constant a,
It is a figure which shows the relationship with the constant value of b, c, d, and e.

FIG. 9 is a diagram showing the relationship between the triplet selection signal of the present invention and the output of the selector / decoder with priority at that time.

FIG. 10 is a block diagram of a conventional triplet circuit that returns triplet results M1, M2, and M3 from triplet data.

FIG. 11A is a timing chart for explaining the operation of a conventional triplet circuit that returns triplet data M1, M2, and M3 from triplet data of 3;
(B) is a timing chart for explaining the operation of the conventional triplet circuit which returns triplet results M1, M2, and M3 from the triplet data of No. 5.

[Explanation of symbols]

 Reference Signs List 1 data input unit 2 selector 3 selector / decoder with priority order 4 output terminal 5 triplet selection signal input terminal 6 constant output unit 7 calculation means 8 output terminal 9 error detection unit 20 data input unit 21 selector 22 constant output unit 23 triplet selection signal Input terminal 25 Adder circuit 26 Output terminal 27 Output terminal 28 Selector / decoder with priority order 29 Operation result output 30 Borrow output 31 Constant output 32 Error detection signal 33 Constant output section 34 Error judgment circuit 100 Serial input terminal 101 Shift register 102 Constant output Unit 103 triplet selection signal input terminal 104 triplet result M3 output terminal 105 addition circuit 106 shift register 107 constant output unit 108 triplet result M2 output terminal 109 input unit 110 addition circuit 111 shift Register 112 input unit 113 triplets result M1 output terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/14 H03M 7/30

Claims (28)

(57) [Claims] 1. A data input section for receiving triplet data obtained by adding first, second and third data in accordance with a predetermined formula, and selecting the triplet data as one input data and selecting the triplet data by a triplet selection signal. A data selector that outputs data, a constant output unit that outputs a constant selected by the triplet selection signal, and performs subtraction between the output of the data selector and the output of the constant output unit to obtain a subtracted value and a borrow value. An operation means for outputting, receiving the output of the data selector, the subtraction value and the borrow value of the operation means, outputting the first, second and third data, and outputting the first, second and third data to the other input of the data selector. And a decoder for transmitting intermediate data. 2. The predetermined calculation formula is to add a value obtained by multiplying the first data by “9”, a value obtained by multiplying the second data by “3”, and the third data. The triplet circuit according to claim 1, wherein: 3. The arithmetic means has at least three adding circuits, each adding circuit adding an output from the data selector and one of constant outputs from the constant output section to obtain a value of an addition result. 3. The triplet circuit according to claim 2, wherein the triplet circuit outputs a borrow value indicating whether the addition result is negative. 4. A data processing apparatus comprising: a first selection signal and a second selection signal as the triplet selection signal; wherein the data selector outputs the triplet data in response to the first selection signal; The data selector outputs at least "-9", "-18" and "-27", the data selector outputs the intermediate data in response to the second selection signal, and the constant output unit outputs at least "-3". 4. The triplet circuit according to claim 3, wherein the triplet circuit outputs "-6" and "-9". 5. The decoder outputs the first data from a combination of borrow values of the three adders in response to the first selection signal, and outputs the first data from the triplet data. And outputs a value obtained by subtracting “9” times as the intermediate data, and outputs the second data from a combination of borrow values of the three adders in response to the second selection signal; 5. The triplet circuit according to claim 4, wherein a value obtained by subtracting "3" times the second data from the intermediate data is output as the third data. 6. The arithmetic means further includes at least fourth and fifth adders for outputting a value of an operation result and a borrow value indicating whether the operation result is negative.
In response to the selection signal, the constant output section further outputs “0” and “−”.
27 "to be added to the fourth and fifth adder circuits, respectively, and the constant output section further outputs" 0 "and" -9 "in response to the second selection signal, and outputs the" 0 "and" -9 ". 6. The triplet circuit according to claim 4, further comprising an error determination circuit for receiving said borrow value of said fifth addition circuit in addition to a corresponding one of said fourth and fifth addition circuits. 7. The predetermined calculation formula is to add a value obtained by multiplying the first data by “25”, a value obtained by multiplying the second data by “5”, and the third data. The triplet circuit according to claim 1, wherein: 8. The arithmetic means has at least five adder circuits, each adder circuit adding an output from the data selector and one of constant outputs from the constant output section to obtain a value of an addition result. The triplet circuit according to claim 7, wherein a borrow value indicating whether the addition result is negative is output. 9. A data processing apparatus comprising: a first selection signal and a second selection signal as the triplet selection signal, wherein the data selector outputs the triplet data in response to the first selection signal, and the constant output unit includes: At least "-25", "-50", "-75", "-100" and "-125"
The data selector outputs the intermediate data in response to the second selection signal, and the constant output unit outputs at least “−5”, “−10”, “−15”, and “−2”.
9. The triplet circuit according to claim 8, which outputs "0" and "-25". 10. The decoder outputs the first data from a combination of borrow values of the five adders in response to the first selection signal, and outputs the first data from the triplet data. And outputs a value obtained by subtracting "25" times as the intermediate data, outputs the second data from a combination of the borrow values of the five adding circuits in response to the second selection signal, 10. The triplet circuit according to claim 9, wherein a value obtained by subtracting "5" times the second data from the intermediate data is output as the third data. 11. An error judging unit that receives the borrow value of an addition circuit that receives a constant output “−125” according to the first selection signal among constant outputs from the constant output unit in the addition circuit. The triplet circuit according to claim 9, further comprising a circuit. 12. A value obtained by multiplying the first data by “9” and the second data
In the triplet processing method for extracting the first, second, and third data from the triplet data obtained by adding the value obtained by multiplying the data of "3" by the third data and the third data, "-9", "-" 18 "and" -2
7 "are subtracted from each other to determine the value of the first data from the sign of the respective subtraction results, and" -3 "," 3 "from the intermediate data obtained by subtracting" 9 "times the first data from the triplet data. -6 "and" -9 "are subtracted, and the value of the second data is determined from the sign of the respective subtraction results. The value" 3 "of the second data is determined from the intermediate data.
A triplet processing method characterized in that a value obtained by subtracting the double is used as the third data. 13. The first data is “0” or “−” when the triplet data becomes negative by subtraction by “−9”.
If the subtraction by "9" is positive and the subtraction by "-18" is negative, it is "1", and the subtraction by "-18" is positive and "-2".
In the subtraction by "7", if it is negative, it is "2".
Is "0" if the intermediate data becomes negative by subtraction by "-3", "1" if it is positive in subtraction by "-3" and "1" if it is negative in subtraction by "-6". 13. The triplet processing method according to claim 12, wherein the subtraction by "1" is positive and the subtraction by "-9" is negative if the subtraction is "2". 14. The triplet data obtained by adding a value obtained by multiplying the first data by “25”, a value obtained by multiplying the second data by “5”, and the third data, to the first, second, and third data. In the triplet processing method for extracting data, "-25", "-50", "-7"
5 "," -100 ", and" -125 "are respectively subtracted, the value of the first data is determined from the sign of each subtraction result, and" 25 "times the first data is subtracted from the triplet data. "-5", "-
10 ”,“ −15 ”,“ −20 ”, and“ −25 ”are subtracted from each other, and
A triplet processing method, wherein a value obtained by subtracting "5" times the second data from the intermediate data is determined as the third data. 15. The first data is “0” if the triplet data becomes negative by subtraction by “−25”,
If the subtraction by “−25” is positive and the subtraction by “−50” is negative, “1” if the subtraction by “−50” is positive and the subtraction by “−75” is negative, “2” or “−” 7
If the subtraction by "5" is positive and the subtraction by "-100" is negative, it is "3" if it is negative, and the subtraction by "-100" is positive and "-"
If the subtraction by "125" is negative, it is "4", and the second data is "0" if the intermediate data becomes negative by subtraction by "-5", and the second data is positive and "2" by subtraction by "-5". -1
If the subtraction by 0 is negative, it is "1" if the subtraction by "-10" is positive, and if the subtraction by "-15" is negative, it is "2" if it is negative, and the subtraction by "-15" is positive and "-20". 15. The triplet processing method according to claim 14, wherein the subtraction by "3" is negative if the subtraction by "-20" is positive and the subtraction by "-25" is negative by "4". . 16. A selector / decoder with priority order for outputting first, second, and third triplet output data, and input data and the third triplet output data, and one of them is input by a triplet selection signal. Selector means for outputting one of them, constant output means for inputting the triplet selection signal to output a constant value, inputting the output of the selector means and the output of the constant output means, subtracting these, and calculating Calculating means for outputting a processing result and a borrow; the selector / decoder with priority order inputs an output of the selector means, an arithmetic processing result of the calculating means and a borrow, and A triplet calculation method characterized by generating second and third triplet output data. 17. The triplet operation method according to claim 16, wherein said constant output means outputs n negative constants, said operation means has n adders, and said selector means And n of the constant output means
And the first to n-1st constant outputs.
Wherein the adder circuit outputs the addition result and a borrow, and the n-th adder circuit outputs only a borrow output. 18. The triplet operation method according to claim 16, wherein in the case of three triplets, said constant output means outputs three negative constants, and said operation means comprises three adder circuits. A triplet operation method characterized by being constituted. 19. The triplet operation method according to claim 16, wherein in the case of five triplets, said constant output means outputs five negative constants, and said operation means comprises five addition circuits. A triplet operation method characterized by being constituted. 20. The triplet operation method according to claim 18, wherein said three negative constants are "-9" and "-1".
A triplet operation method, wherein a first set of "8" and "-27" and a second set of "-3" and "-6" and "-9" are sequentially selected. 21. The triplet operation method according to claim 19, wherein said five negative constants are “−25”, “−5”.
0, “−75”, “−100” and “−125” and a first set of “−5”, “−10”, “−15”, “−2”.
A triplet operation method, wherein a second set of "0" and "-25" are sequentially selected. 22. The method of claim 20, wherein the first set of three negative constants is selected on a first clock and the second set is selected on subsequent clocks. The triplet operation method. 23. The triplet operation scheme according to claim 21, wherein said first set of five negative constants is selected at a first clock and said second set is selected at a subsequent clock. The triplet operation method. 24. The triplet operation method according to claim 17, further comprising two addition circuits, wherein said operation means has five addition circuits, and said constant output means outputs "-9" as a constant output. , "-18", "-27", "0" and a first set of "0" and "-3", "-6", "-
9 "," 0 "and a second set of" 0 "and" -25 ",
"-50", "-75", "-100" and "-12"
5 "and" -5 "," -10 "," -15 ",
A triplet operation method characterized in that a fourth set of "-20" and "-25" can be selectively output. 25. The triplet operation method according to claim 24, wherein in the case of three triplets, said constant output means outputs a first set of constant outputs at a first clock, and outputs a second set of constant outputs at a second clock. A triplet operation method characterized by outputting a set of constant outputs. 26. The triplet operation method according to claim 24, wherein in the case of 5 triplets, said constant output means outputs a third set of constant outputs at a first clock, and outputs a fourth set of constant outputs at a second clock. A triplet operation method characterized by outputting a set of constant outputs. 27. The triplet operation method according to claim 16, wherein the input data and the triplet selection signal are inputted, and it is detected whether or not the input data is larger than a maximum value that can be taken as normal input data. An error detection means for outputting an error detection signal. 28. The triplet operation method according to claim 27, wherein said constant output means outputs n constants, wherein said operation means has n adder circuits,
The output of the selector means and the n constant outputs of the constant output means are respectively inputted, the first to (n-1) th adder circuits output the addition result and the borrow, and the n-th adder circuit outputs the borrow. A triplet operation method comprising: outputting an output to the selector / decoder with priority order; and outputting the borrow as an error detection signal to the error detection means.