JP3149829B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3149829B2 JP3149829B2 JP29702397A JP29702397A JP3149829B2 JP 3149829 B2 JP3149829 B2 JP 3149829B2 JP 29702397 A JP29702397 A JP 29702397A JP 29702397 A JP29702397 A JP 29702397A JP 3149829 B2 JP3149829 B2 JP 3149829B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- adhesive tape
- adhesive
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に係り、
特にＬＯＣ（Lead On Chip）構造の樹脂封止型半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a resin-encapsulated semiconductor device having a LOC (Lead On Chip) structure.
【０００２】[0002]
【従来の技術】従来より、半導体装置のより小型化を目
的とし、安価で量産性に優れているＬＯＣ構造の樹脂封
止型半導体装置が知られている。図５は従来の半導体装
置の一例の透視斜視図、図６は図５のＡ−Ａ線に沿う縦
断面図を示す。両図中、同一構成部分には同一符号を付
してある。この従来の半導体装置は、ＬＯＣ構造の樹脂
封止型半導体装置で、チップ４の表面上に複数のリード
フレーム２が接着テープ３を介して接着固定され、更に
樹脂１で封止されている。接着テープ３はポリイミド層
６の上面と下面に接着剤５を配した構成であり、リード
フレーム２側の表面が平面である。2. Description of the Related Art Conventionally, there has been known a resin-sealed semiconductor device having a LOC structure which is inexpensive and excellent in mass productivity with the aim of further downsizing the semiconductor device. FIG. 5 is a perspective view showing an example of a conventional semiconductor device, and FIG. 6 is a longitudinal sectional view taken along line AA of FIG. In both figures, the same components are denoted by the same reference numerals. This conventional semiconductor device is a resin-encapsulated semiconductor device having a LOC structure, in which a plurality of lead frames 2 are adhesively fixed on the surface of a chip 4 via an adhesive tape 3 and further sealed with a resin 1. The adhesive tape 3 has a configuration in which the adhesive 5 is disposed on the upper surface and the lower surface of the polyimide layer 6, and the surface on the lead frame 2 side is flat.
【０００３】図８（Ａ）は従来の半導体装置の他の例の
要部の断面図を示す。この従来の半導体装置は、特開平
８−１１１４９８号公報記載の半導体装置で、リードフ
レーム２をチップ４の表面に固着する接着剤５とリード
フレーム２の間にはさみ込んだ埋め込み状態でポリイミ
ドコート層７を介してチップ４の表面に固着した構造で
ある。FIG. 8A is a sectional view of a main part of another example of a conventional semiconductor device. This conventional semiconductor device is the same as the semiconductor device described in Japanese Patent Application Laid-Open No. HEI 8-111498, except that a polyimide coating layer is embedded in an embedded state sandwiched between an adhesive 5 for fixing the lead frame 2 to the surface of the chip 4 and the lead frame 2. The structure is fixed to the surface of the chip 4 via the gate 7.
【０００４】[0004]
【発明が解決しようとする課題】しかるに、図５及び図
６に示した従来の半導体装置では、図７（Ａ）にその拡
大断面図に示すように、リードフレーム２の上面と接着
テープ３の上面に段差ができる。この結果、リードフレ
ーム２が上部に存在しない接着テープ３のみの領域ａ
１、ａ２と、リードフレーム２が上部に存在する接着テ
ープ３の領域ｂ１、ｂ２において、チップ４とリードフ
レーム２を圧着させた時に、チップ４と接着テープ３と
の界面にて圧力差が生じ、図７（Ｂ）に示すように領域
ａ１及びａ２に加わる圧力の方が領域ｂ１及びｂ２に圧
力に比べて弱くなり、チップ４の表面と接着テープ３と
の密着性が低下し、更に実装ストレス等により剥離が発
生することがあり、その場合はコロージョン等の水分の
侵入による不良を引き起こす。However, in the conventional semiconductor device shown in FIGS. 5 and 6, as shown in an enlarged sectional view of FIG. A step is formed on the upper surface. As a result, the area a of only the adhesive tape 3 where the lead frame 2 does not exist on the upper part
When the chip 4 and the lead frame 2 are pressed against each other in the areas b1 and b2 of the adhesive tape 3 where the lead frame 2 is located at the top, a pressure difference occurs at the interface between the chip 4 and the adhesive tape 3. As shown in FIG. 7 (B), the pressure applied to the areas a1 and a2 is weaker than the pressure applied to the areas b1 and b2, and the adhesion between the surface of the chip 4 and the adhesive tape 3 is reduced. Peeling may occur due to stress or the like, and in such a case, a failure due to penetration of moisture such as corrosion is caused.
【０００５】一方、図８（Ａ）に示した従来の半導体装
置では、リードフレーム２下面とチップ４の上面の間に
接着テープが無いので、接着剤５のみの領域ｃ１、ｃ２
とリードフレーム２のみの領域ｄ１、ｄ２では図８
（Ｂ）に一点鎖線IIで示すように圧力差がなく、上記の
従来装置のような段差に起因した圧力差による密着性の
低下をある程度低減できるが、密着性の向上は不十分で
ある。On the other hand, in the conventional semiconductor device shown in FIG. 8A, since there is no adhesive tape between the lower surface of the lead frame 2 and the upper surface of the chip 4, the regions c1 and c2 where only the adhesive 5 is provided.
8 in the regions d1 and d2 of the lead frame 2 only.
As shown by the dashed line II in (B), there is no pressure difference, and the decrease in adhesion due to the pressure difference caused by the step as in the above-described conventional device can be reduced to some extent, but the improvement in adhesion is insufficient.
【０００６】本発明は以上の点に鑑みなされたもので、
実装ストレス等によるリードフレームの剥離を防止し得
る半導体装置を提供することを目的とする。[0006] The present invention has been made in view of the above points,
An object of the present invention is to provide a semiconductor device capable of preventing a lead frame from peeling due to mounting stress or the like.
【０００７】また、本発明の他の目的は、密着性を向上
し得る半導体装置を提供することにある。Another object of the present invention is to provide a semiconductor device capable of improving adhesion.
【０００８】[0008]
【課題を解決するための手段】本発明は上記の目的を達
成するため、複数のリードフレームをチップ表面に接着
テープを介して接着固定するＬＯＣ構造を有する半導体
装置において、リードフレームの下面及び接着テープ上
面の少なくともいずれか一方に、凹凸部を設け、互いに
嵌合させ、リードフレームの上面と接着テープの上面の
高さを揃えたことを特徴とする。According to the present invention, there is provided a semiconductor device having a LOC structure in which a plurality of lead frames are bonded and fixed to a chip surface via an adhesive tape. At least one of the upper surfaces of the tape is provided with an uneven portion, which is fitted to each other, and the upper surface of the lead frame and the upper surface of the adhesive tape are
It features a uniform height .
【０００９】上記の接着テープは、ポリイミド層とその
上下両面にそれぞれ配置された接着剤からなる積層構造
であり、リードフレーム側の前記接着剤に前記リードフ
レームを嵌合させるための凹部が形成されていることを
特徴とする。The above-mentioned adhesive tape has a laminated structure composed of a polyimide layer and an adhesive disposed on the upper and lower surfaces of the polyimide layer, and a concave portion for fitting the lead frame to the adhesive on the lead frame side is formed. It is characterized by having.
【００１０】ここで、凹部は、リードフレームの配列方
向にリードフレームの配置間隔で前記リードフレーム側
の前記接着剤に形成されていてもよく、また、凹部は、
リードフレームの長手方向に接着テープ幅でリードフレ
ームに形成されていてもよい。Here, the concave portion may be formed in the adhesive on the lead frame side at an interval of arrangement of the lead frame in the arrangement direction of the lead frame.
The lead frame may be formed with an adhesive tape width in the longitudinal direction of the lead frame.
【００１１】本発明は、リードフレームの下面及び接着
テープ上面の少なくともいずれか一方に、凹凸部を設
け、互いに嵌合させたため、リードフレームの上面と接
着テープ上面の段差をなくすことができる。According to the present invention, the unevenness is provided on at least one of the lower surface of the lead frame and the upper surface of the adhesive tape, and they are fitted to each other.
【００１２】[0012]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。図１は本発明になる半導体装置
の一実施の形態の透視斜視図、図２（Ａ）、（Ｂ）はそ
れぞれ本発明装置の第１の実施の形態の図１中のＡ−Ａ
線、Ｂ−Ｂ線に沿う縦断面図を示す。各図中、同一構成
部分には同一符号を付してある。この実施の形態はＬＯ
Ｃ構造の半導体装置で、図１に示すように、チップ４の
表面に接着テープ８を介してリードフレーム２が接着固
定されている。リードフレーム２は一部が樹脂１内に封
止され、一部が樹脂１の外に出ている。チップ４及び接
着テープ８は樹脂１に封止されている。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a transparent perspective view of an embodiment of a semiconductor device according to the present invention, and FIGS. 2A and 2B are AA in FIG. 1 of a first embodiment of the device of the present invention.
FIG. 2 shows a vertical cross-sectional view along the line BB. In each figure, the same components are denoted by the same reference numerals. In this embodiment, the LO
In the semiconductor device having the C structure, as shown in FIG. A part of the lead frame 2 is sealed in the resin 1, and a part thereof is outside the resin 1. The chip 4 and the adhesive tape 8 are sealed in the resin 1.
【００１３】上記の接着テープ８は図２（Ａ）、（Ｂ）
に示すように、ポリイミド層６の下面と上面にそれぞれ
接着剤５ａと５ｂが配置された積層構造である。また、
接着剤５ａと５ｂのうちリードフレーム２側の接着剤５
ｂは、図２（Ａ）に示すように、断面凹凸形状とされ、
その深さと幅はリードフレーム２の厚さと幅に対応して
いる。このため、図２（Ａ）に示すように、接着剤５ｂ
の凹部にリードフレーム２が丁度嵌合して、リードフレ
ーム２の上面と接着テープ８の上面は段差の無い形状と
なっている。The above adhesive tape 8 is shown in FIGS. 2A and 2B.
As shown in FIG. 6, the adhesive has a laminated structure in which adhesives 5a and 5b are arranged on the lower surface and the upper surface of the polyimide layer 6, respectively. Also,
Adhesive 5 on lead frame 2 side among adhesives 5a and 5b
b has an uneven cross section as shown in FIG.
The depth and width correspond to the thickness and width of the lead frame 2. For this reason, as shown in FIG.
The lead frame 2 is just fitted into the concave portion, and the upper surface of the lead frame 2 and the upper surface of the adhesive tape 8 have a shape with no step.
【００１４】これにより、チップ４とリードフレーム２
を圧着させた時には、図４（Ａ）の要部拡大断面図に示
すように、接着剤５ｂの凸部が存在する領域ｅ１、ｅ２
と接着剤５ｂの凹部とリードフレーム２が存在する領域
ｆ１、ｆ２において、チップ４と接着テープ８との界面
には図４（Ｂ）に示すように圧力差が生じることはな
い。また、その密着性は図８（Ｂ）に実線Ｉで示すよう
に、図８（Ａ）に示した従来の半導体装置の密着性（図
８（Ｂ）の一点鎖線II）に比べて十分な密着性が得られ
た。Thus, the chip 4 and the lead frame 2
4A, the areas e1 and e2 where the protrusions of the adhesive 5b are present, as shown in the main part enlarged sectional view of FIG.
In the regions f1 and f2 in which the lead frame 2 and the concave portion of the adhesive 5b are present, no pressure difference is generated at the interface between the chip 4 and the adhesive tape 8 as shown in FIG. Further, as shown by a solid line I in FIG. 8B, the adhesiveness is more sufficient than the adhesiveness of the conventional semiconductor device shown in FIG. 8A (dashed line II in FIG. 8B). Adhesion was obtained.
【００１５】次に、本発明の第２の実施の形態について
説明する。図３（Ａ）及び（Ｂ）は本発明になる半導体
装置の第２の実施の形態の断面図で、それぞれ図１中の
Ａ−Ａ線、Ｂ−Ｂ線に沿う断面図を示す。同図中、図２
と同一構成部分には同一符号を付してある。Next, a second embodiment of the present invention will be described. FIGS. 3A and 3B are cross-sectional views of a semiconductor device according to a second embodiment of the present invention, which are cross-sectional views taken along lines AA and BB in FIG. 1, respectively. In FIG.
The same components as those described above are denoted by the same reference numerals.
【００１６】この実施の形態は、図３（Ａ）に示すリー
ドフレームの長手方向に直交する方向（リードフレーム
配列方向）であるＡ−Ａ線に沿う断面形状は図２（Ａ）
に示した断面形状と同様に、接着テープ８はポリイミド
層６の下面と上面にそれぞれ接着剤５ａと５ｂが配置さ
れた積層構造で、接着剤５ａと５ｂのうちリードフレー
ム９側の接着剤５ｂは断面凹凸形状とされ、その深さと
幅はリードフレーム９の厚さと幅に対応しているため、
リードフレーム９の上面と接着テープ８の上面は段差の
無い形状となっている。In this embodiment, FIG. 2A is a sectional view taken along line AA which is a direction (lead frame arrangement direction) orthogonal to the longitudinal direction of the lead frame shown in FIG.
The adhesive tape 8 has a laminated structure in which adhesives 5a and 5b are arranged on the lower surface and the upper surface of the polyimide layer 6, respectively, in the same manner as the cross-sectional shape shown in FIG. Has a concave-convex section, and its depth and width correspond to the thickness and width of the lead frame 9,
The upper surface of the lead frame 9 and the upper surface of the adhesive tape 8 have no step.
【００１７】更に、この実施の形態では、図３（Ｂ）に
示すリードフレーム長手方向であるＢ−Ｂ線に沿う断面
形状が、第１の実施の形態の断面形状と異なり、リード
フレーム９に凹部９ａが接着テープ幅で形成されてお
り、接着テープ８の接着剤５ａと嵌合する形状とされて
いる。これにより、リードフレーム９の長手方向に沿う
上面と接着テープ８の上面は段差の無い形状となってい
る。本実施の形態はより一層密着性の高い形状とされて
いる。Further, in this embodiment, the cross-sectional shape along the line BB which is the longitudinal direction of the lead frame shown in FIG. 3 (B) is different from the cross-sectional shape of the first embodiment. The concave portion 9a is formed to have the width of the adhesive tape, and has a shape to be fitted with the adhesive 5a of the adhesive tape 8. As a result, the upper surface of the lead frame 9 along the longitudinal direction and the upper surface of the adhesive tape 8 have no step. In the present embodiment, the shape is further improved.
【００１８】[0018]
【発明の効果】以上説明したように、本発明によれば、
リードフレームの下面及び接着テープ上面の少なくとも
いずれか一方に、凹凸部を設け、互いに嵌合させること
で、リードフレームの上面と接着テープ上面の段差をな
くすようにしたため、リードフレームとチップを固定さ
せるときの接着テープにおける圧力差をなくすことがで
き、チップ表面と接着テープとの圧着性を向上でき、よ
って、接着テープとチップ表面の剥離を防ぐことができ
る。また、本発明によれば、上記の剥離発生による水分
や腐食性ガスの侵入等による不良の発生を防止でき、信
頼性を向上できる。As described above, according to the present invention,
An uneven portion is provided on at least one of the lower surface of the lead frame and the upper surface of the adhesive tape, and they are fitted to each other to eliminate a step between the upper surface of the lead frame and the upper surface of the adhesive tape, so that the lead frame and the chip are fixed. The pressure difference in the adhesive tape at that time can be eliminated, and the pressure-bonding property between the chip surface and the adhesive tape can be improved, and therefore, peeling of the adhesive tape and the chip surface can be prevented. Further, according to the present invention, it is possible to prevent the occurrence of defects due to the intrusion of moisture or corrosive gas due to the above-mentioned peeling, and to improve the reliability.
【図１】本発明になる半導体装置の一実施の形態の透視
斜視図である。FIG. 1 is a transparent perspective view of an embodiment of a semiconductor device according to the present invention.
【図２】図１中のＡ−Ａ線、Ｂ−Ｂ線に沿う本発明にな
る半導体装置の第１の実施の形態の縦断面図である。FIG. 2 is a longitudinal sectional view of the first embodiment of the semiconductor device according to the present invention, taken along line AA and line BB in FIG.
【図３】図１中のＡ−Ａ線、Ｂ−Ｂ線に沿う本発明にな
る半導体装置の第２の実施の形態の縦断面図である。FIG. 3 is a vertical sectional view of a semiconductor device according to a second embodiment of the present invention along line AA and line BB in FIG. 1;
【図４】図２、図３の要部の拡大断面図と圧力特性を示
す図である。FIG. 4 is an enlarged sectional view of a main part of FIGS. 2 and 3 and a diagram showing pressure characteristics.
【図５】従来の半導体装置の一例の透視斜視図である。FIG. 5 is a perspective view of an example of a conventional semiconductor device.
【図６】図５中のＡ−Ａ線に沿う縦断面図である。FIG. 6 is a longitudinal sectional view taken along line AA in FIG.
【図７】図５の要部拡大断面図と圧力特性を示す図であ
る。7 is an enlarged sectional view of a main part of FIG. 5 and a diagram showing pressure characteristics.
【図８】従来の半導体装置の他の例の要部拡大断面図
と、従来と本発明の密着性特性図である。FIG. 8 is an enlarged cross-sectional view of a main part of another example of the conventional semiconductor device, and an adhesion characteristic diagram of the conventional and the present invention.
１ 樹脂 ２、９ リードフレーム ４ チップ ５ａ、５ｂ 接着剤 ６ ポリイミド層 ８ 接着テープ ９ａ 凹部 DESCRIPTION OF SYMBOLS 1 Resin 2, 9 Lead frame 4 Chip 5a, 5b Adhesive 6 Polyimide layer 8 Adhesive tape 9a Depression
Claims (4)
着テープを介して接着固定するＬＯＣ構造を有する半導
体装置において、 前記リードフレームの下面及び接着テープ上面の少なく
ともいずれか一方に、凹凸部を設け、互いに嵌合させ、
前記リードフレームの上面と前記接着テープの上面の高
さを揃えたことを特徴とする半導体装置。1. A semiconductor device having a LOC structure for bonding and fixing a plurality of lead frames to a chip surface via an adhesive tape, wherein an uneven portion is provided on at least one of a lower surface of the lead frame and an upper surface of the adhesive tape. Mated with each other ,
Height between the upper surface of the lead frame and the upper surface of the adhesive tape
Wherein a stocked with of.
上下両面にそれぞれ配置された接着剤からなる積層構造
であり、前記リードフレーム側の前記接着剤に前記リー
ドフレームを嵌合させるための凹部が形成されているこ
とを特徴とする請求項１記載の半導体装置。2. The adhesive tape according to claim 1, wherein the adhesive tape has a laminated structure including a polyimide layer and an adhesive disposed on both upper and lower surfaces of the polyimide layer, and a concave portion for fitting the lead frame to the adhesive on the lead frame side. The semiconductor device according to claim 1, wherein the semiconductor device is formed.
方向に該リードフレームの配置間隔で前記リードフレー
ム側の前記接着剤に形成されていることを特徴とする請
求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein the recess is formed in the adhesive on the lead frame side at an arrangement interval of the lead frame in an arrangement direction of the lead frame.
方向に前記接着テープ幅で前記リードフレームに形成さ
れていることを特徴とする請求項１又は２記載の半導体
装置。4. The semiconductor device according to claim 1, wherein the recess is formed in the lead frame with the width of the adhesive tape in a longitudinal direction of the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29702397A JP3149829B2 (en) | 1997-10-29 | 1997-10-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29702397A JP3149829B2 (en) | 1997-10-29 | 1997-10-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135684A JPH11135684A (en) | 1999-05-21 |
| JP3149829B2 true JP3149829B2 (en) | 2001-03-26 |
Family
ID=17841233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29702397A Expired - Fee Related JP3149829B2 (en) | 1997-10-29 | 1997-10-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3149829B2 (en) |
-
1997
- 1997-10-29 JP JP29702397A patent/JP3149829B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11135684A (en) | 1999-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2611748B2 (en) | Resin-sealed semiconductor device | |
| JP2936669B2 (en) | Resin-sealed semiconductor device | |
| JPH06227189A (en) | Production of ic card module | |
| US6028368A (en) | Semiconductor device with potting resin structures | |
| US6002181A (en) | Structure of resin molded type semiconductor device with embedded thermal dissipator | |
| JP3149829B2 (en) | Semiconductor device | |
| JPS63179557A (en) | Lead frame for semiconductor device | |
| JPH0972804A (en) | Semiconductor pressure sensor | |
| JP2908255B2 (en) | Semiconductor device | |
| JP3520976B2 (en) | Bonding structure of semiconductor device | |
| JPS611042A (en) | Semiconductor device | |
| JPH06216313A (en) | Semiconductor device sealed with resin | |
| US6211573B1 (en) | Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor | |
| JPH083059Y2 (en) | Piezoelectric vibration parts | |
| JPH0365023B2 (en) | ||
| JP3965767B2 (en) | Semiconductor chip substrate mounting structure | |
| JP2658353B2 (en) | IC card | |
| JP4071121B2 (en) | Semiconductor device | |
| JPS62108545A (en) | Printed substrate type package | |
| JPH09116076A (en) | Lead frame and semiconductor device | |
| JPH0468558A (en) | Semiconductor module | |
| JPH0685110A (en) | Semiconductor device | |
| JP3810975B2 (en) | Semiconductor module | |
| JPS60239046A (en) | Semiconductor device and manufacture thereof | |
| JPH0366150A (en) | Semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080119 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090119 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100119 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |