JP3144392B2 - Method and apparatus for designing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a design method and a design apparatus for arranging cells and the like of a semiconductor integrated circuit in a predetermined area.

[0002]

2. Description of the Related Art Conventionally, a design apparatus for arranging cells or the like in a predetermined area is known (allocation algorithm for gate-laying gate array, 4th Circuit and System Karuizawa Workshop, pp.367-372). ). FIG. 7 is a block diagram showing a conventional semiconductor integrated circuit designing apparatus, and FIG. 8 is a flowchart showing a designing method thereof. As shown in FIG. 7, the semiconductor integrated circuit design device includes a control device 43, and the control device 43 generates a cut line creating device 45 that creates a cut line that divides a base of the semiconductor integrated circuit into predetermined regions. Dividing device (mini-cut device) 4 for dividing a cell block into regions divided by cut lines
4 and a predetermined cell block are connected to a mapping device 46 that arranges the cell blocks in areas divided by cut lines.

A method for arranging a cell block of a semiconductor integrated circuit by using the designing apparatus configured as described above will be described below. As shown in FIG. 8, first, the control device 43 reads a cut line instruction file, which is a file in which directions, positions, and orders for creating cut lines are registered, and creates a cut line in the cut line creating device 45. To instruct. As a result, the cut line creation device 45 creates a cut line on the base of the semiconductor integrated circuit based on the designated direction and position (step 51).

After creating the cut line, the control device 43 requests the dividing device 44 to divide the cell block. The dividing device 44 divides the plurality of cell blocks so as to minimize the number of nets crossing the cut line (Step 5).
2).

[0005] Thereafter, the control device 43 checks whether or not the cut line instruction file is empty (step 53). The division processing of the cell block in step 52 is repeated.

If it is determined in step 53 that the cut line instruction file is empty, the controller 4
3 requests the mapping device 46 to arrange the cell block on the base. The mapping device 46 determines the arrangement position of the given cell block so as to minimize the total length of the net, and arranges the cell block in each area (step 54).

FIG. 9 is a schematic diagram showing a cell block divided in step 52 to minimize the number of nets crossing the cut line. As shown in FIG. 9, the cell blocks 61 and 62 are connected to nets 67 and 6 respectively.
8, and the cell blocks 62 and 63 are connected by nets 69 and 70. The cell block 64 and the cell block 65 are connected by a net 71, and the cell block 65 and the cell block 66 are connected by a net 72. Therefore, if the cell blocks 61, 62 and 63 and the cell blocks 64, 65 and 66 are divided and arranged on both sides of the cut line 73, the number of nets crossing the cut line 73 becomes zero.

However, since each cell block has various sizes, as shown in FIG. 9, if the number of nets crossing the cut line is to be minimized, the total size of the divided cell blocks may be biased. There is. Then, since the size of the base region in which the divided cell blocks are arranged is limited, if the total size of the cell blocks arranged in the region is larger than the size of the base region, the size of the designed region is reduced. Cell blocks cannot be placed.

Therefore, in step 52, the number of nets crossing the cut line is minimized, and the total size of one of the divided cell blocks and the total size of the other cell block are respectively reduced by the cut. It is necessary to design the division of the cell block so as not to exceed the size of one base region and the size of the other base region divided by the line.

[0010]

However, when arranging cell blocks by the above-mentioned conventional design method,
It is necessary to minimize the number of nets crossing the cut line, and to consider the size of the base region divided by the cut line and the total size of the cell blocks arranged on each region. This is an NP complete problem (NP- complete proble
m), and the cell block to be divided may not be obtained in practical time.

Therefore, it may be necessary to arrange the divided cell blocks in an area different from the designed area in order to minimize the number of nets crossing the cut line. For example, as a result of dividing a plurality of cell blocks in order to minimize the number of nets crossing the cut line, as shown in FIG. 9, a group to which the cell blocks 61, 62, and 63 belong and cell blocks 64, 65, and 66 belong to If it is divided into groups to which it belongs, the number of nets crossing the cut line 73 is zero.

However, in this case, the cell block 61,
Since the total size of the areas 62 and 63 is larger than the total size of the areas to be arranged, the cell blocks 65 to be arranged in one area 75a as shown in FIG.
In the other region 75b.
As a result, the cut line 73 has a distorted shape, and if the cut line 73 is designed to be linear, the number of nets crossing the cut line becomes two. As described above, by minimizing the number of nets crossing the cut line, the degree of wiring congestion is minimized. As a result, a plurality of cell blocks can be arranged in a favorable state on both sides of the preset cut line. Instead, the wiring congestion is degraded.

[0013] Even when the divided cell blocks have a total size that can be arranged in the base area divided by the cut line, a predetermined cell block is set on the set base. You may not be able to place them. This is because, as shown in FIG. 11, when designing a gate array, the base on which the cell blocks are arranged has various types and directions. In addition,
In FIG. 11, background characteristics 1A and 1B indicating the type and direction of the base are shown in each region of the base 75, and the base characteristics of the base that can be arranged in each region of the cell block 74 are shown.

As shown in FIG. 11, a cell block 61,
Since the characteristics of 63, 64, 65 and 66 match the base characteristics 1A and 1B at the designed arrangement positions, the cell blocks 61 and 63 can be arranged on one area 75a, and the other can be arranged. The cell block 6 is placed on the area 75b.
4, 65 and 66 can be arranged. However, the cell block 74 is a cell block that can be arranged only on the lower ground of the base characteristic 1B, and the characteristic of the cell block 74 does not match the base characteristic 1A of the area 75a.
Cell block 74 cannot be arranged on region 75a. As a result, it is necessary to arrange the cell block 74 on a region different from the designed region 75a, and the degree of wiring congestion is deteriorated as in the case shown in FIG.

Various other layout methods have been proposed as cell layout methods for semiconductor integrated circuits that can optimize the signal propagation delay time (Japanese Patent Laid-Open Nos. 5-206271 and 5-206271). 5-343522
JP, JP-A-7-94586 and JP-A-7-1
No. 69839). However, even with these conventional layout methods, a plurality of cell blocks cannot be easily arranged in a region divided by a cut line.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and a semiconductor integrated circuit in which a plurality of cell blocks can be easily arranged in a region divided by a cut line without deteriorating a wiring congestion degree. An object of the present invention is to provide a circuit design method and a circuit design device.

[0017]

A method of designing a semiconductor integrated circuit according to the present invention comprises the steps of: forming a cut line on a base of a semiconductor integrated circuit to divide the base into two or more regions; The step of dividing a plurality of cell blocks into two or more groups under the condition of minimizing the number of nets and assigning them to each of the two or more areas of the base corresponds to the total size of the plurality of cell blocks belonging to the cell block group When the size is larger than the size of the area to be replaced, one or more cell blocks selected from the cell block group are replaced with one or more spare cell blocks prepared in advance, respectively, and Making the total size of the arranged cell blocks and the spare cell blocks equal to or smaller than the size of the corresponding region.

The method of designing a semiconductor integrated circuit according to the present invention may further comprise, before the step of reducing the total size of the cell blocks and spare cell blocks arranged on the corresponding area to the size of the corresponding area or less. A step of calculating a slack value of a net connected to the cell blocks belonging to the cell block group, wherein the total size of the cell blocks and spare cell blocks arranged on the corresponding area is equal to or smaller than the size of the corresponding area. In one or more cell blocks selected from the group of cell blocks in the step of making, the slack value of the net connected to the cell block may be a positive value.

In this case, the one or more spare cell blocks have the same function as the cell block to be exchanged respectively, have a smaller size than the cell block to be exchanged, and After the replacement, the slack value of the net connected to the spare cell block may be 0 or a positive value.

Another method of designing a semiconductor integrated circuit according to the present invention includes a step of forming a cut line on a base of a semiconductor integrated circuit and dividing the base into two or more regions, and a method of reducing the number of nets crossing the cut line. Dividing the plurality of cell blocks into two or more groups under the condition of minimizing and assigning the divided cell blocks to two or more regions of the base, respectively; In a different case, one or two or more cell blocks having different base characteristics from the base to be arranged are replaced with one or more spare cell blocks prepared in advance, respectively, and cells arranged on the corresponding area are replaced. Matching the base characteristics of the block and the spare cell block with the base characteristics of the corresponding region.

In this case, the one or more spare cell blocks have the same function as the cell block to be exchanged, have the same base characteristic as the base to be arranged, and have the same function as the spare cell block. After the replacement, the slack value of the net connected to the spare cell block may be 0 or a positive value.

A semiconductor integrated circuit designing apparatus according to the present invention includes a cut line creating apparatus for creating a cut line on a base of a semiconductor integrated circuit and dividing the base into two or more regions;
A dividing device that divides a plurality of cell blocks into two or more groups under the condition of minimizing the number of nets crossing the cut line and allocates the divided cell blocks to two or more regions of the base, and a plurality of spare cell blocks stored in advance. When the total size of the library and the plurality of cell blocks belonging to the cell block group is larger than the size of the corresponding area, one or more cell blocks selected from the cell block group are stored in the library, respectively. A block exchange device that replaces one or more spare cell blocks that have been set and makes the total size of the cell blocks and spare cell blocks arranged on the corresponding area equal to or smaller than the size of the corresponding area. It is characterized by the following.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit designing apparatus, comprising: a cut line forming apparatus for forming a cut line on a base of a semiconductor integrated circuit to divide the base into two or more regions; A dividing device that divides a plurality of cell blocks into two or more groups under the condition of minimizing the number of cells and allocates the divided cell blocks to two or more regions of the base, a library in which a plurality of spare cell blocks are stored in advance, When the background characteristics of the cell blocks belonging to the block group are different from the background characteristics of the corresponding region, one or more cell blocks having the background characteristics different from the arranged background are stored in the library. Of the cell block and the spare cell block arranged on the corresponding area, and And a block replacement unit to match the characteristics, that it has a characterized.

The semiconductor integrated circuit designing apparatus according to the first and second aspects of the present invention includes a slack calculator for calculating a slack value of a net connected to the cell block and the spare cell block. Preferably, the switching device determines a cell block to be selected based on the slack value and a spare cell block stored in the library. It is preferable that the library has the same function as each other and stores spare cell blocks having different background characteristics, sizes and shapes.

According to the conventional method for designing a semiconductor integrated circuit, the number of nets crossing the cut line is minimized, and the size of the base region divided by the cut line and the total size of the cell blocks arranged on each region are reduced. And a plurality of cell blocks in consideration of the characteristics of the base and the like.
Although it was necessary to divide the cell blocks into the above groups and assign them to two or more regions divided by the cut lines, it is extremely difficult to divide a plurality of cell blocks in consideration of the number of nets, the region size, and the like. It was difficult. In addition, if the divided cell blocks are placed in an area different from the designed area in order to minimize the number of nets crossing the cut line, the number of nets crossing the cut line increases, and the degree of wiring congestion deteriorates. May be.

However, in the present invention, the cell blocks divided into two or more groups are assigned to two or more base regions under the condition of minimizing the number of nets crossing the cut line, When a cell block belonging to the group cannot be arranged on the corresponding base area for a reason such as a total size or a base property, the cell block is replaced with a spare cell block prepared in advance. If the total size of a plurality of cell blocks belonging to the cell block group is larger than the size of the corresponding area, the cell block to be replaced has, for example, a slack value of a net connected thereto that is positive. The spare cell block has the same function as the cell block to be exchanged, and has a smaller size than the cell block to be exchanged. Later, a slack value of a net connected to the spare cell block can be selected to be 0 or a positive value. As a result, the total size of the cell blocks and the spare cell blocks arranged in the corresponding area can be made equal to or smaller than the size of the corresponding area. Can be arranged on a predetermined area.

When the background characteristics of the cell blocks belonging to the cell block group are different from the background characteristics of the corresponding area, the spare cell blocks to be replaced have the same function as the cell blocks to be replaced. In addition, it is possible to select one having a base property that matches the base to be arranged, and having a slack value of 0 or a positive value of a net connected to the spare cell block after replacement with the spare cell block. As a result, the base characteristics of the cell blocks and the spare cell blocks arranged in the corresponding region can be matched with the base characteristics of the corresponding region, so that two or more nets crossing the cut line are minimized. The cell blocks divided into groups can be arranged on a predetermined area.

Therefore, in the present invention, it is not necessary to arrange the cell blocks divided in order to minimize the number of nets crossing the cut line in a region different from the designed region. Can be prevented from increasing and the degree of wiring congestion being degraded.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method and an apparatus for designing a semiconductor integrated circuit according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an apparatus for designing a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a flowchart showing a designing method thereof.

As shown in FIG. 1, the semiconductor integrated circuit designing apparatus has a control unit 3 and a library 9 storing spare cell blocks having various functions, sizes, types of bases that can be arranged, and directions. The control device 3 includes a cut line creating device 5 that creates a cut line that divides a base of the semiconductor integrated circuit into a predetermined region, and a dividing device (mini-cut device) that divides a cell block into regions divided by the cut line. 4. A mapping device 6 for arranging a predetermined cell block in an area divided by a cut line, a slack calculator 8 for calculating a slack value of a net connecting between cell blocks, and a cell that cannot be arranged on a predetermined lower ground It is connected to a block exchange device 7 for exchanging blocks for spare cell blocks stored in a library 9.

A method for arranging the cell blocks of the semiconductor integrated circuit by using the designing apparatus configured as described above will be described below. As shown in FIG. 2, first, the control device 3 reads a cut line instruction file which is a file in which the direction, position, and order in which the cut line is created are registered, and creates a cut line in the cut line creating device 5. To instruct. As a result, the cut line creation device 5 creates a cut line on the base of the semiconductor integrated circuit based on the designated direction, position, and the like (step 11).

After creating the cut line, the control device 3 requests the dividing device 4 to divide the cell block. Dividing device 4
Divides the cell block so as to minimize the number of nets crossing the cut line (step 12). At this time, if the total size of the cell blocks arranged on both sides of the cut line can be made not to exceed the area size of the base to be arranged, with the number of nets crossing the cut line minimized, In this state, the cell block is divided.

Thereafter, the control device 3 checks whether or not the cut line instruction file is empty (step 1).
3) If the cut line instruction file is not empty, the cut line creation processing in step 11 and the cell block division processing in step 52 are repeated.

If it is determined in step 13 that the cut line instruction file is empty, the controller 3
Requests the slack calculator 8 to calculate a slack value.
Thereby, the slack calculator 8 calculates a slack value of each net connecting the cell blocks using, for example, the zero slack method (step 14). At this time, the slack calculator 8 calculates the slack value assuming that the cell block is arranged at the center of the area divided by the cut line. Note that one of the methods for calculating the slack value is as follows.
One known method is the zero slack method (“Circuit Plac
ement for Predictable Performance ”, ICCAD90, PP.8
8-91).

After the slack value is calculated, the control device 3 requests the block exchange device 7 to exchange the cell blocks so that all the cell blocks can be arranged in the corresponding area. The block exchange device 7 compares the base characteristics (direction and type) of each base region with the base characteristics of the corresponding cell block, and checks whether a predetermined cell block can be arranged in the set base region. I do. As a result, if placement is not possible, a spare cell block that can be placed in the set base area and has the same function as the cell block that cannot be placed is placed in the library. And replace the cell block with a spare cell block. At this time, the block switching device 7 considers the slack value of the net connected to the cell block, and if there is no margin for the delay,
The spare cell block is selected in consideration that the slack value is not set to 0 even after the replacement.

The block switching device 7 compares the size of the base area with the total size of the arranged cell blocks. As a result, when the total size of the cell blocks to be arranged is larger than the area size of the base or is equal to the base size, among these cell blocks,
A cell block that has a slack value and does not make slack negative even when the replacement is performed is selected as a replacement target. On the other hand, a spare cell block having a smaller size than the cell block selected as a replacement target, having the same function, and having a slack value which does not become negative even after replacement is searched from the library, and the selected cell is searched. The block is replaced with a spare cell block (step 15).

After completion of the exchange, the mapping device 6 considers the total length of the nets connecting the cell blocks to be arranged to be minimum in each area, and takes into account the cell block and the exchanged spare cell block. Find the placement position of
These are arranged on each area of the base (step 16).

FIG. 3 is a schematic diagram showing a cell block divided in step 12 to minimize the number of nets crossing the cut line. As shown in FIG. 3, the cell blocks 21 and 22 are connected to nets 27 and 2 respectively.
8, and the cell blocks 22 and 23 are connected by nets 29 and 30. The cell block 24 and the cell block 25 are connected by a net 31, and the cell block 25 and the cell block 26 are connected by a net 32. Therefore, if the cell blocks 21, 22, and 23 and the cell blocks 24, 25, and 26 are divided and arranged on both sides of the cut line 33, the number of nets crossing the cut line 33 becomes zero.

However, when the cell blocks are divided in this way, the total size of the cell blocks 21, 22 and 23 becomes larger than the size of the base area where these cell blocks are arranged. The cell blocks 21, 22, and 23 cannot be arranged on one of the two areas. Further, as shown in FIG. 4, when a cell block that is to be arranged on one area 35a of the base 35 penetrates and is arranged on the other area 35b, the cut line 33 has a distorted shape. When trying to design the cut line 33 in a straight line,
The number of nets crossing the cut line is two.

Therefore, in the present embodiment, for example, of the cell blocks 21, 22, and 23, the cell block 22 having a slack value calculated in step 14 (at least the slack value is a positive value) is replaced. Select as target. As shown in FIG. 4, a spare cell block 34 having the same function as that of the cell block 22 and capable of being reduced in size without making the slack value negative by replacement is replaced with a spare cell block 34 from the library 9. By selecting, the cell block 22 is replaced with the spare cell block 34
Replace with As a result, as shown in FIG. 5, the total size of the cell blocks 21 and 23 and the spare cell block 34 becomes smaller than the size of one area 35a, so that the cell blocks 21 and 23 and the spare cell Block 34 can be located. As a result, all the divided cell blocks can be arranged on a predetermined area with the number of nets crossing the cut line 33 being minimized.

As shown in FIG. 6, when the cell block is divided into cell blocks 21, 36 and 23 and cell blocks 24, 25 and 26 in step 12, the total size of the cell blocks 21, 36 and 23 Is the base area 35
Even when the size is smaller than the size a, the characteristics of the cell block 36 and the base characteristics (base type and direction) 1A of the region 35a may not match. Then, the cell block 36 cannot be arranged on the region 35a,
If the cell block 36 is arranged in an area other than the set area 35a, the degree of wiring congestion deteriorates.

Therefore, when a part of the divided cell block cannot be arranged in a predetermined area because the base characteristics do not match, the present embodiment has the same function as the cell block 36. The spare cell block 37, which does not make the slack value negative by replacement and can be arranged on the area 35a having the base characteristic 1A, is selected from the library 9 and the cell block is selected. 36 is replaced with a spare cell block 37. Thus, the cell blocks 21 and 23 and the spare cell block 37 can be arranged on the region 35a, and the occurrence of unarranged cell blocks can be prevented. Further, since it is not necessary to arrange the cell blocks 36 in an area other than the set area 35a, it is possible to prevent the number of nets crossing the cut line from increasing.

[0043]

As described in detail above, according to the present invention,
2 with the minimum number of nets crossing the cut line
After allocating the cell blocks divided into the above groups to two or more background areas, the cell blocks belonging to the divided cell block groups are replaced with spare cell blocks prepared in advance, so that the nets crossing the cut line can be replaced. Cell blocks divided into two or more groups can be arranged on a predetermined area under the condition of minimizing the number, and it is possible to prevent the number of nets crossing the cut line from increasing and the degree of wiring congestion from deteriorating. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an apparatus for designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing a cell block divided in step 12 to minimize the number of nets crossing a cut line.

FIG. 4 is a schematic diagram showing an example in which a cell block is replaced with a spare cell block in the present embodiment.

FIG. 5 is a schematic diagram showing an example in which a spare cell block shown in FIG. 4 is arranged.

FIG. 6 is a schematic diagram showing an example in which a cell block is replaced with a spare cell block in the present embodiment.

FIG. 7 is a block diagram showing a conventional semiconductor integrated circuit designing apparatus.

FIG. 8 is a flowchart showing a conventional method for designing a semiconductor integrated circuit.

FIG. 9 is a schematic diagram showing a cell block divided in step 52 to minimize the number of nets crossing a cut line.

FIG. 10 is a schematic diagram showing a state where divided cell blocks are arranged on a base.

FIG. 11 is a schematic diagram showing characteristics of a base on which a cell block is arranged.

[Explanation of symbols]

3, 43; control device 4, 44; dividing device 5, 45; cut line creating device 6, 46; mapping device 7, block exchange device 8, slack calculating device 21, 22, 23, 24, 25, 26, 36, 61,6
2, 63, 64, 65, 66, 74; cell blocks 27, 28, 29, 30, 31, 32, 67, 68, 6
9, 70, 71, 72; nets 33, 73; cut lines 34, 37; spare cell blocks 35, 75; bases 35a, 35b, 75a, 75b;

Claims (9)

(57) [Claims] 1. A step of forming a cut line on a base of a semiconductor integrated circuit and dividing the base into two or more regions, and a step of dividing a plurality of cell blocks into two or more under the condition of minimizing the number of nets crossing the cut line. And allocating each of the plurality of cell blocks to the two or more regions of the base, and selecting from the cell block group when the total size of the plurality of cell blocks belonging to the cell block group is larger than the size of the corresponding region. Replacing one or more of the prepared cell blocks with one or more spare cell blocks prepared in advance,
Reducing the total size of the cell blocks and spare cell blocks arranged on the corresponding area to the size of the corresponding area or less. 2. A cell block connected to a cell block belonging to the cell block group before a step of reducing a total size of a cell block and a spare cell block arranged on the corresponding region to a size equal to or smaller than the size of the corresponding region. Calculating a slack value of a net, wherein the total size of the cell blocks and spare cell blocks arranged on the corresponding area is selected from the cell block group in the step of reducing the total size to less than or equal to the size of the corresponding area. 2. The method according to claim 1, wherein at least one of the cell blocks has a positive slack value of a net connected to the cell block. 3. The one or more spare cell blocks have the same function as the cell block to be replaced, have a smaller size than the cell block to be replaced, and are replaced with the spare cell block. 3. The method according to claim 2, wherein a slack value of a net connected to the spare cell block later becomes 0 or a positive value. 4. A step of forming a cut line on a base of a semiconductor integrated circuit and dividing the base into two or more regions, and a step of dividing a plurality of cell blocks into two or more regions under the condition of minimizing the number of nets crossing the cut line. And allocating to each of two or more areas of the base, and when the base properties of the cell blocks belonging to the cell block group are different from the base properties of the corresponding area, Is replaced with one or more spare cell blocks prepared in advance, respectively, and the base characteristics of the cell blocks and spare cell blocks arranged on the corresponding area and the corresponding base characteristics And a step of matching the underlying characteristics of the region. 5. The one or more spare cell blocks have the same function as the cell block to be replaced, have the same base characteristic as the base to be arranged, and are replaced with the spare cell block. 5. The method according to claim 4, wherein a slack value of a net connected to the spare cell block later becomes 0 or a positive value. 6. A cut line creating apparatus for creating a cut line on a base of a semiconductor integrated circuit to divide the base into two or more regions, and a plurality of cell blocks under conditions that minimize the number of nets crossing the cut line. Is divided into two or more groups and assigned to each of two or more areas of the base, a library in which a plurality of spare cell blocks are stored in advance, and a total size of a plurality of cell blocks belonging to the cell block group are When the size is larger than the size of the corresponding area, one or more cell blocks selected from the cell block group are replaced with one or more spare cell blocks stored in the library, respectively, and A block exchange device for setting the total size of cell blocks and spare cell blocks arranged on the area to be equal to or smaller than the size of the corresponding area. A semiconductor integrated circuit designing apparatus. 7. A cut line creating apparatus for creating a cut line on a base of a semiconductor integrated circuit to divide the base into two or more regions, and a plurality of cell blocks under conditions that minimize the number of nets crossing the cut line. Is divided into two or more groups and assigned to each of two or more areas of the base, a library in which a plurality of spare cell blocks are stored in advance, and base characteristics of the cell blocks belonging to the cell block group correspond. In the case where the background characteristics are different from those of the region, one or more cell blocks having background characteristics different from those of the placed background are replaced with one or more spare cell blocks stored in the library, respectively. A block exchange device for matching background characteristics of cell blocks and spare cell blocks arranged on the region with background characteristics of the corresponding region. A semiconductor integrated circuit designing apparatus. 8. A slack calculator for calculating a slack value of a net connected to the cell block and the spare cell block, wherein the block exchange device selects a cell block and the library based on the slack value. 8. The apparatus for designing a semiconductor integrated circuit according to claim 6, wherein the spare cell block stored in the semiconductor integrated circuit is determined. 9. The library according to claim 6, wherein the library has the same function as each other, and stores spare cell blocks having different background characteristics, sizes, and shapes. An apparatus for designing a semiconductor integrated circuit according to the above.