JP3144108B2 - Signal transmission device and image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission device and an image display device suitable for use in a large-sized video display device and the like.

[0002]

2. Description of the Related Art For example, as shown in FIG. 12, in a large-sized video apparatus 1 having a length and a width of several meters, a video signal is supplied from a VTR 3 or the like via a signal processing unit 2. The large-sized video device 1 and the signal processing unit 2 are connected by a wiring 4.

[0003]

[0004]

Since the large-sized video device 1 and the signal processing unit 2 are grounded, a ground loop is formed. A loop current flows through the wiring 4. This is superimposed on an image signal, a control signal, and the like transmitted on the wiring 4, and the screen 11 of the large-sized video device 1 is
However, there is a problem that the image projected on the camera is disturbed or each part malfunctions.

[0005]

Accordingly, the present invention has been made to solve the above-mentioned problem, and proposes a signal transmission device capable of preventing a ground loop from being formed and transmitting a signal accurately. It is.

[0007]

According to the present invention, in a signal transmission device for processing an image signal and transmitting the signal to an image display means, the image signal is divided for every predetermined number of pixels of the image display means. Packet generating means for generating a packet including each of the divided image signals obtained as described above, a synchronization signal being arranged at the head, and an end signal being arranged at the end, and a packet generated by the packet generating means. And an inverting means for inverting the divided image signal at least every predetermined unit, and a signal transmitting means for transmitting a signal relating to the packet inverted by the inverting means to the image display means. Also, the present invention provides a signal transmission apparatus for processing an input signal comprising an image signal or a control signal and transmitting the processed signal to an image display means, wherein the format conversion means converts the input signal into a conversion signal of a desired format; Inverting means for inverting the converted signal converted by the means every predetermined unit;
Signal transmission means for transmitting a signal relating to the conversion signal inverted by the inversion means to the image display means, the format conversion means converts a predetermined unit of signal into a conversion signal of an even number of adjacent contiguous signals, The inverting means alternately inverts a signal of a predetermined unit in which the converted signal is repeated. According to another aspect of the present invention, there is provided an image display apparatus comprising: an image display unit; and a signal transmission unit configured to process an image signal and transmit the processed signal to the image display unit. Packet generating means for generating a packet that divides every number of pixels, includes each of the divided image signals obtained by this division, has a synchronization signal arranged at the beginning, and an end signal arranged at the end. Inverting means for inverting the divided image signal at least every predetermined unit with respect to the packet generated by the packet generating means, and signal transmitting means for transmitting a signal relating to the packet which has been inverted by the inverting means to an image display unit Is provided.

[0008]

In FIG. 1, a video signal supplied from a VTR 3 or the like is supplied to a format conversion and inversion circuit 22 via an A / D converter 21 of a signal processing unit 2. Here, the data is converted into a transmission format as shown in FIGS. In this transmission format, the synchronization signal “SYN
Each data is 1 except for “C” and data end signal “EOF”.
Inverted every other data. This makes it possible to prevent DC components from being accumulated.

Further, as shown in FIG. 11, if the data is inverted between the signal on the nth line and the signal on the (n + 1) th line, the DC component is removed in units of two lines. Output SB of format conversion and inversion circuit 22
Is subjected to 8-10 conversion based on the 8-10 conversion table (FIGS. 7 and 8) stored in the 8-10 conversion circuit 23.
As a result, since "0" and "1" are converted into five data each, the DC component is removed.

[0010] The 8-10 converted signal SC is supplied to the light emitting unit 30 of the large-sized video device 1 and the pulse transformer 3
The data is supplied to the memory 36 via the 3 and 10-8 conversion circuit 35. Here, since the pulse transformer 33 is used, a ground loop is not formed between the signal processing unit 2 and the light emitting unit 30. Therefore, it is possible to prevent the occurrence of noise and errors due to the loop current.

The output data of the 10-8 conversion circuit 35 is supplied to an address determination circuit 39, where the light emitting unit address "ADD." Is analyzed. When this matches the address of each light-emitting unit 30, it is fetched and stored in the memory 36.
And the light is supplied to the light emitting element 38 to emit light from the three primary color light emitters. As a result, an image is displayed on the screen 11.

When the input signal SD of the 10-8 conversion circuit 35 is 1
If it is not in the 0-8 conversion table, it is determined that an error has occurred and a flag is output. At this time, writing to the memory 36 is prohibited,
The stored data immediately before is output. This prevents erroneous data from being supplied to the light emitting element 38, thereby preventing the image on the screen 11 from being disturbed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where a signal transmission apparatus according to the present invention is applied to a control system for a large-sized video apparatus will be described in detail with reference to the drawings. Here, the screen of the large-sized video device is composed of a large number of picture elements. Each of these picture elements is provided with an address and is connected in series. Then, an image signal having an address for each data is serially supplied to the picture element, and when the address of each picture element matches the address of each data of the image signal, this data is taken in, thereby forming each picture element. The three primary color light emitters emit light, and an image is displayed on the screen.

FIG. 1 shows a control system of a large-sized video device 1 to which a signal transmission device according to the present invention is applied. In the figure, a video signal output from a VTR 3 or the like is converted into an 8-bit digital signal S by an A / D converter 21 of a signal processing unit 2.
A, which is the format conversion and inversion circuit 2
2 is supplied.

In the format conversion and inversion circuit 22,
The input 8-bit signal SA is converted into a transmission format as shown in FIG. This transmission format is for transmitting an image signal, and the synchronization signal "SYNC"
And the light emitting unit address “ADD.” Are repeated twice, and then the light emitting data (image data) “DATA-BL”
UE1 "to" DATA-GREEN8 "are inserted once each, for a total of 24 characters, and finally the data end signal" EO "
F "is repeated twice.

In this transmission format, light emission data "DATA-BLUE1" to "DATA-GREEN"
Since the same signal is repeated twice except for "8", the reliability against transmission errors is improved. Data other than the synchronization signal “SYNC” is inverted every other data. As a result, adjacent data cancel each other's DC components.

The light emission data "DATA-BLUE"
1 to "DATA-GREEN8" are inserted only once because of the large number of data, and are not designed to invert the same signal. However, adjacent image data for each color, for example, "DATA-BLUE1" and "DATA-GREEN8" DATA-BLUE
2, "DATA-RED1" and "DATA-RED"
2 "is correlated, and one of them is inverted, so that the DC component is canceled. In this example, 30 characters are transmitted as one pack.

FIG. 3 shows a transmission format of the control signal. For example, when transmitting luminance data or the like for controlling the luminance of the screen 11, after the synchronization signal "SYNC" is repeated twice, the signals "F0" to "FF" for distinguishing various control types are transmitted. Are inserted twice, indicating that the brightness control is performed, followed by the brightness data "BR"
T ", a refresh" RFS "indicating a repetition period, and a block code" BLK "are inserted twice. The luminance data “BRT” to the block code “BLK” are repeated four times, for a total of 24 characters. Finally, a data end signal “EOF” is inserted.

In the transmission format of the control signal described above, except for the synchronization signal "SYNC" and the data end signal "EOF", one of the signals repeated twice is inverted, so that the DC component is canceled. In addition, the synchronization signal “SY
If the "NC" and the data end signal "EOF" are inverted signals, the DC component is canceled in block units. On the receiving side of the control signal, the inverted data is restored and compared with the non-inverted data, and when they match, it is determined that there is no error and the data is taken in. If they do not match, the data one packet before is used.

FIG. 4 shows a format conversion and inversion circuit 22.
5 and 6 are signal waveform diagrams. FIG.
, The clock supplied from the outside is converted into a signal a (FIG. 5A) by a 1/10 frequency dividing circuit 51,
The signal is converted into a signal b (FIG. 5B) by a / 2 frequency dividing circuit 52. The output signal b of the 1/2 frequency dividing circuit 52 is frequency-divided by the 1/15 frequency dividing circuit 53, from which the signals c to f (FIG. 5C) are obtained.
Is output and supplied to the decoder 54.

The decoder 54 generates the first to fifteenth pulses (FIG. 6D) based on the signals c to f supplied from the 1/15 frequency dividing circuit 53. Then, the first signal g is supplied to the switch 56 connected to the synchronization signal "SYNC" generating circuit 55, whereby the switch 56 is turned on and the synchronization signal "SYNC" is output. Note that the synchronization signal “SYNC” is generated twice during the period of the signal g.

The second signal h is supplied to a switch 58 connected to a light-emitting unit address "ADD." Generating circuit 57, which turns on the switch 58 so that the light-emitting unit address "ADD." 2 in sum circuit 59
Supplied once. The exclusive OR circuit 59 has an output signal b of the 1/2 frequency dividing circuit 52 and an output signal k of the NOR circuit 64.
The output of the AND circuit 65 having (FIG. 6F) as an input is also supplied.

The NOR circuit 64 outputs "1" when both the first signal g and the fifteenth signal j of the decoder 54 are "0", and the AND circuit 65 changes the signal k to "1".
In this case, the signal b is output as it is. That is, when the signal g and the signal j are not output from the decoder 54, the light emitting unit address “ADD.” Is output as it is or inverted from the exclusive OR circuit 59 by the output signal b of the １ ／ frequency dividing circuit 52. Is done.

That is, when the signal b is "0", the first light emitting unit address "ADD."
9 is output as it is, and when the signal b is “1”, the second light emitting unit address “ADD.” Is inverted and output.

The third to fourteenth output signals of the decoder 54 are converted by the OR circuit 60 into a continuous signal i (FIG. 6 (E)), which is supplied to a switch 61 connected to the A / D converter 21. Is done. Thus, the switch 61 is turned on, and the image signal SA or the control signal supplied from the A / D converter 21 is supplied to the exclusive OR circuit 59. Here, similarly to the above-mentioned light emitting unit address “ADD.”, It is output as it is or inverted.

The fifteenth output signal j of the decoder 54 is supplied to a switch 63 connected to a data end signal "EOF" generating circuit 62, which turns on the switch 63 and outputs the data end signal "EOF" twice. Is done. As a result, an output signal SB (FIG. 6 (G)) which is converted into a predetermined transmission format and which is inverted except for a part is output and supplied to the 8-10 conversion circuit 23.

In the 8-10 conversion circuit 23, the 8-10 code conversion table shown in FIGS. 7 and 8 is stored in the ROM, and the input 8 bit signal SB is converted into a 10 bit signal based on the code conversion table. Converted to SC.

FIG. 9 shows a specific example of the 8-10 conversion. For example, when the 8-bit input signal S is "00000010" as shown in the third diagram of FIG. It is “02” when expressed in base, and this is 1
When converting to 0 bits, "01" in hexadecimal notation
F "is assigned. Then, the first “0” is represented by 2 bits, and the next two digits “1F” are represented by 4 bits, respectively, so that the total becomes 10 bits. Therefore, "0
“1F” becomes “0000011111”.

Similarly, when the 8-bit input signal SB is hexadecimal "FB" as shown in the 252nd of the figure, 10-bit hexadecimal "3C8" is assigned. When each digit of "3C8" is displayed in bits, "11"
"1100" and "1000", and when these are consecutive, it becomes "1111001000" with 10 bits. In this way, 256 pieces of data that can be represented by 8 bits are
Convert to bits.

The 8-10 code conversion performed here is performed to prevent the DC component of the input signal SB from being accumulated, and the converted signal SC is "0" and "0" for each data. 1 "is selected to be 5 each.
That is, although the number of data that can be represented by 8 bits is 256, if this is represented by 8 bits as it is, the numbers of “0” and “1” are different, so that as the input signal SB increases, the DC component is accumulated, Will become indistinguishable.

In order to avoid this, the number of “0” and “1” in each data is made the same and “0”
And “1” may be canceled so that the DC component does not remain. Therefore, according to the present invention, it is possible to distinguish 256 data that can be represented by the 8-bit input signal SB, and furthermore, it is possible to represent 1 bit as “0” and “1” for each data.
0 bit is selected.

However, "0" and "1" in 10 bits
Are 5 bits each, and the remaining 4 bits are the first, second, 255th and 25th bits in FIG.
As shown in the sixth example, the numbers of “0” and “1” are different.

The 8-10 conversion circuit 23 shown in FIG.
The bit-converted signal SC is converted into a serial signal by a parallel / serial conversion circuit 24 and then amplified by a line driver 25, which is supplied to the light emitting unit 30 of the large-sized video device 1 via the wiring 4. . The light emitting units 30 constitute the screen 11 of the large-sized video device 1 as shown in FIG. In the light emitting unit 30, the input signal is amplified by a line receiver 31 and a driver 32 as shown in FIG. 1 and then supplied to an amplifier 34 via a pulse transformer 33.

Since the signal processing unit 2 and the light emitting unit 30 are separated by the pulse transformer 33, a ground loop is not formed, and therefore, noise is prevented from being superimposed on the image signal and the control signal due to the loop current. it can.

The output signal SD of the amplifier 34 is 10
In the -8 conversion circuit 35, the original 8 bits are converted in a method reverse to the above-mentioned 8-10 conversion circuit 23. Signal SD is 8-1
If it is not in the 0 code conversion table (FIGS. 7 and 8), it is determined that an error has occurred and an error flag is output. The 10-8 converted data is stored in the memory 36 and the address determination circuit 39.
Supplied to Then, the light emitting unit address “ADD.” Is analyzed by the address determination circuit 39, and when this matches the address set in the light emitting unit 30,
Output data of the 10-8 conversion circuit 35 is stored in the memory 36.

When the error flag is output, writing to the memory 36 is prohibited, and the data immediately before stored in the memory 36 is output again. The output signal of the memory 36 is supplied to the light emitting element 38 via the driver 37. The light emitting element 38 has a three primary color light emitting body, which emits light based on the supplied data. In this way, each light emitting unit 30 captures data corresponding to the address and emits light based on the data, whereby an image is displayed on the screen 11.

In this control system for a large-sized video device, the wiring 4 connecting the signal processing unit 2 and the light emitting unit 30
Is provided with a terminator 41. Here, for example, when the wiring 4 has 120Ω, a 120Ω terminator is used. As a result, the signal does not rebound on the wiring 4 and the signal can be transmitted flat.

In the above transmission format, the data is inverted every other character. However, as shown in FIG. 11A, the signal on the n-th line is inverted every other character, and as shown in FIG. In the next (n + 1) th line, each data can be inverted. As a result, the DC component is canceled by the sum of the n-th line and the (n + 1) -th line, so that it is possible to prevent the DC component from being accumulated even in long-time data transmission.

[0039]

As described above, according to the present invention, an image signal is divided into a predetermined number of pixels of an image display means (image display unit), and each divided image signal obtained by the division is divided Packet generation means for generating a packet including a synchronization signal at the beginning and an end signal at the end;
For the packet generated by this packet generation means,
At least a reversing means for reversing the divided image signal every predetermined unit and a signal transmitting means for transmitting a signal relating to the packet, which has been reversed by the reversing means, to the image display means. Also, the present invention provides a format conversion unit for converting an input signal into a conversion signal of a desired format, an inversion unit for inverting the conversion signal converted by the format conversion unit every predetermined unit, and an inversion process by the inversion unit. Signal transmission means for transmitting a signal related to the converted signal to the image display means, the format conversion means converts a predetermined unit of signal into a conversion signal of an even number of adjacent contiguous signals, and the inversion means converts the conversion signal of the conversion signal. The signal of a predetermined unit which is repeated is alternately inverted.

Therefore, according to the present invention, it is possible to prevent DC components from being accumulated during signal transmission. For example, it is possible to interpose a pulse transformer between the signal transmission device and the image display means. Accordingly, it is possible to prevent the formation of a ground loop and to prevent the occurrence of noise and errors due to the loop current. Further, according to the present invention, since the inversion processing is performed for each packet, the image display means (image display unit) which receives the inverted packet requires any part when the inverted part is restored. Can be easily determined based on the timing of the synchronization signal for each packet, and the reinversion process can be performed easily and accurately.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a control system of a large-sized video device to which a signal transmission device according to the present invention is applied.

FIG. 2 is a diagram illustrating a transmission format of an image signal.

FIG. 3 is a diagram illustrating a transmission format of a control signal.

FIG. 4 is a system diagram of a format conversion and inversion circuit 22;

FIG. 5 is a signal waveform diagram (1/2) of a format conversion and inversion circuit 22;

FIG. 6 is a signal waveform diagram (2/2) of the format conversion and inversion circuit 22;

FIG. 7 is a diagram illustrating an 8-10 code conversion table (1/2).

FIG. 8 is a diagram illustrating an 8-10 code conversion table (2/2).

FIG. 9 is a diagram illustrating a method of 8-10 code conversion.

FIG. 10 is a configuration diagram of a large-sized video device 1.

FIG. 11 is a diagram illustrating a transmission format when the inversion position is shifted line by line.

FIG. 12 is a diagram illustrating a control system of a general large-sized video device 1.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Large-sized video apparatus 2 Signal processing part 4 Wiring 11 Screen 22 Format conversion and inversion circuit 23 8-10 conversion circuit 30 Light emitting unit 33 Pulse transformer 36 Memory 38 Light emitting element 39 Address judgment circuit 41 Terminator 52 1/2 frequency dividing circuit 54 Decoder 55 Synchronization signal generation circuit 57 Light emitting unit address generation circuit 62 Data end signal generation circuit

Claims (7)

(57) [Claims] 1. A signal transmitting apparatus for processing an image signal and transmitting the processed signal to an image display means, wherein the image signal is divided into a predetermined number of pixels of the image display means, and each of the divided image signals is obtained. A packet generation unit for generating a packet including a divided image signal, a synchronization signal being arranged at the beginning, and an end signal being arranged at the end; and at least the division is performed on the packet generated by the packet generation unit. A signal transmission device comprising: inversion means for inverting an image signal every predetermined unit; and signal transmission means for transmitting a signal relating to the packet, which has been inverted by the inversion means, to the image display means. 2. Converting a first data code constituting the packet, which has been inverted by the inverting means, into a second data code in which the number of “1” and “0” are substantially equal. 2. The signal transmission device according to claim 1, further comprising code conversion means, wherein the signal transmission means transmits the packet subjected to the code conversion processing by the code conversion means to the image display means. 3. The packet generated by the packet generating means further includes an address signal corresponding to a position of a predetermined number of pixels of the image display means to be driven by the divided image signal included in the packet. The signal transmission device according to claim 1, wherein the signal transmission is performed. 4. An end signal arranged at the end of the packet generated by the packet generating means is a signal obtained by inverting a synchronization signal arranged at the head of the packet. 2. The signal transmission device according to 1. 5. A signal transmission apparatus for processing an input signal comprising an image signal or a control signal and transmitting the processed signal to an image display means, comprising: a format conversion means for converting the input signal into a conversion signal of a desired format; Inverting means for inverting the converted signal converted by the converting means at predetermined intervals, and signal transmitting means for transmitting a signal related to the converted signal inverted by the inverting means to the image display means, The conversion means converts the predetermined unit signal into a conversion signal of a form in which an even number of adjacent signals are repeated adjacently, and the inversion means alternately inverts the repeated predetermined unit signal of the conversion signal. Signal transmission device. 6. An image display apparatus comprising: an image display unit; and a signal transmission unit that processes an image signal and transmits the signal to the image display unit, wherein the signal transmission unit converts the image signal into the image signal. A packet that is divided for each predetermined number of pixels of the display unit, includes a divided image signal obtained by the division, and generates a packet in which a synchronization signal is arranged at the beginning and an end signal is arranged at the end. Generating means; inverting means for inverting the divided image signal at least every predetermined unit with respect to the packet generated by the packet generating means; and converting the signal of the packet, which has been inverted by the inverting means, into the image An image display device comprising: a signal transmission unit that transmits a signal to a display unit. 7. The packet generated by the packet generating means further includes an address signal corresponding to a position of a predetermined number of pixels of the image display unit to be driven by the divided image signal included in the packet. The image display device according to claim 6, wherein the image display is performed.