WO2013051223A1 - Image data signal output device, image data signal input device, and image display device - Google Patents

Image data signal output device, image data signal input device, and image display device Download PDF

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Publication number
WO2013051223A1
WO2013051223A1 PCT/JP2012/006157 JP2012006157W WO2013051223A1 WO 2013051223 A1 WO2013051223 A1 WO 2013051223A1 JP 2012006157 W JP2012006157 W JP 2012006157W WO 2013051223 A1 WO2013051223 A1 WO 2013051223A1
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Prior art keywords
image data
data signal
output device
unit
signal output
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PCT/JP2012/006157
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French (fr)
Japanese (ja)
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英司 廣田
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シャープ株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present invention relates to an image display device such as a liquid crystal display device, an image data signal output device for transmitting an image data signal for image display, and an image data signal input device.
  • the image data signal is transmitted between the generation source and a processing unit (controller) that performs processing such as ⁇ correction and overdrive processing, or the above processing. For example, between the display unit and the driver of the display unit. Also, for example, within the processing unit, the data is transmitted between processing circuits performing various processes via a transmission path. In these cases, every time the level of the transmitted image data signal changes, a current flows through the transmission path, so that EMI (Electro Magnetic Interference) is likely to occur and power consumption tends to increase.
  • EMI Electro Magnetic Interference
  • the technique for inverting the polarity according to the number of bits whose signal level transitions as described above can always suppress the number of transition bits to less than half, the original number of transition bits is half. If the polarity of all bits is reversed, the number of transition bits cannot be significantly reduced even if the polarity of all bits is reversed, and EMI and power consumption cannot be significantly suppressed.
  • the above method is premised on the transmission of parallel signals, and cannot be applied to the transmission of serial signals.
  • the present invention has been made in view of this point, and an object of the present invention is to easily reduce EMI and power consumption by reducing signal level transition when an image data signal is transmitted. There is.
  • the first invention is An image data signal output device for outputting an image data signal for transmission, A repetitive detection unit that detects repetitive transition patterns of the level of the image data signal and outputs a control signal according to the detection result; According to the detection result, an output suppression unit that suppresses the output of the image data signal, It is provided with.
  • the image data signal can be easily reproduced using the transition pattern of the level of the previous image data signal even if the output is suppressed. . Therefore, it is possible to easily reduce the EMI and the power consumption by suppressing the transition of the level of the output signal while enabling the transmission of an appropriate image data signal.
  • the second invention is An image data signal output device according to a first invention
  • the detection unit is A holding unit for holding a previously input image data signal;
  • a comparison unit that compares the newly input image data signal with the image data signal held in the holding unit; It is provided with.
  • the third invention is An image data signal output device according to a second invention,
  • the comparison unit is configured to perform comparison with the newly input image data signal for a smaller number of bits than the image data signal held in the holding unit.
  • the fourth invention is: An image data signal output device according to any one of the second and third inventions,
  • the holding unit holds an image data signal for pixels of one scanning line or more, or one screen or more,
  • the comparison unit compares an image data signal of a pixel at a position corresponding to a pixel to which a new image data signal is input on the preceding scanning line or screen with the newly input image data signal. It is configured.
  • the fifth invention is: An image data signal output device according to any one of the first to fourth inventions,
  • the output suppression unit may change the level of the output image data signal to one of a current level and a predetermined level when a repetition of the transition pattern of the level of the image data signal is detected. It is configured to be fixed.
  • the configuration can be simplified.
  • the sixth invention is: An image data signal output device according to any one of the first to fifth inventions,
  • the detection unit is configured to detect repetition of the transition pattern at the level for an image data signal having a predetermined number of bits.
  • the eighth invention An image data signal output device according to any one of the first to seventh inventions,
  • the detection unit is configured to detect that all the level transition patterns of the image data signals of a plurality of systems are repeated.
  • the ninth invention An image data signal output device according to an eighth invention,
  • the plurality of image data signals are image data signals for red, green, and blue pixels.
  • the number of detection signals can be reduced for transmission of a plurality of image data signals such as when a color image is displayed.
  • the tenth invention is An image data signal input device to which an image data signal transmitted from any one of the image data signal output devices of the first invention to the ninth invention is input, A holding unit for holding a previously input image data signal; A selection unit that selects an image data signal held in the holding unit or a newly input image data signal based on the control signal; It is provided with.
  • the output is suppressed by selecting the image data signal held in the holding unit.
  • the reproduced image data signal can be easily reproduced.
  • the eleventh invention is An image data signal input device according to a tenth invention,
  • the holding unit is configured to be used as a serial-to-parallel conversion unit that outputs a series of image data signals input and held in series in parallel.
  • the twelfth invention is An image display device, Any one of the first to ninth image data signal output devices; Any one of the tenth invention and the eleventh invention, the image data signal input device; It is provided with.
  • the thirteenth invention is An image display device according to a twelfth aspect of the invention, An image data signal processor for processing the image data signal; An image display unit for displaying an image; With The image data signal processing unit is provided with the image data signal output device, The image display unit is provided with the image data signal input device.
  • the fourteenth invention is The image display device according to any one of the twelfth and thirteenth inventions, An image data signal generator for generating an image data signal; The image data signal generation unit is provided with the image data signal output device.
  • the fifteenth invention The image display device according to any one of the twelfth to fourteenth aspects, further comprising: An overdrive processing unit that performs overdrive processing on the image data signal; A frame memory for holding an image data signal for the overdrive process; With At least one of the image data signal output device and the image data signal input device is provided in the overdrive processing unit, The frame memory is provided with at least one of the image data signal output device and the image data signal input device corresponding to the overdrive processing unit.
  • the present invention it is possible to easily reduce EMI and power consumption by reducing the transition of the signal level when the image data signal is transmitted.
  • FIG. 1 is a block diagram illustrating a configuration of an image display device according to a first embodiment.
  • 3 is a block diagram illustrating specific configurations of an image data signal processing unit 102 and a driver 104 according to Embodiment 1.
  • FIG. 3 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 1.
  • FIG. 3 is a circuit diagram illustrating a specific configuration of an input control unit 121 according to the first embodiment.
  • 3 is a timing chart illustrating an image data signal transmission operation according to the first exemplary embodiment.
  • 6 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 2.
  • FIG. 10 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 3.
  • FIG. 10 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to a fourth embodiment.
  • FIG. 10 is a circuit diagram illustrating a specific configuration of an input control unit 121 according to the fourth embodiment.
  • FIG. 10 is a block diagram illustrating a configuration of a main part of an image display device according to a fifth embodiment.
  • FIG. 10 is a block diagram illustrating a configuration of a main part of another image display device according to the fifth embodiment.
  • Embodiment 1 As an example of the image display device of the present invention, an example of a so-called liquid crystal television that receives a television broadcast and displays an image on a liquid crystal display panel will be described.
  • the liquid crystal television includes an image data signal generation unit 101 that receives a television broadcast and outputs an image data signal, and an image that performs ⁇ correction and overdrive processing on the image data signal.
  • a data signal processing unit 102, a liquid crystal display panel 105, and a driver 104 that generates a drive signal for driving the liquid crystal display panel 105 are provided.
  • the image data signal processing unit 102 and the driver 104 are connected by a flexible substrate 103, for example.
  • the transmission of the image data signal between the image data signal generation unit 101 and the image data signal processing unit 102 or between the image data signal processing unit 102 and the driver 104 is not particularly limited.
  • LVDS Low voltage differential signaling
  • mini-LVDS mini-LVDS.
  • the image data signal processing unit 102 and the driver 104 include an output control unit 111 (image data signal output device) or an input control unit 121 (image data signal input device), respectively.
  • the output control unit 111 of the image data signal processing unit 102 sequentially receives, for example, 8-bit image data signals serially input from a processing circuit such as ⁇ correction according to the serial transmission clock signal. Detects that the 8-bit shift registers 112 and 113 (part of the repetitive detection unit, holding unit) that are held by shifting coincide with the 8-bit values held in these shift registers 112 and 113.
  • Comparator 114 (a part of the repetitive detection unit), a flip-flop that holds the detection result in accordance with the divided-by-8 clock signal obtained by dividing the serial transmission clock signal by 8, and outputs the control signal 103b, and the control In accordance with the signal 103b, the output of the shift register 112 or the signal fixed to the L (Low) level is selectively selected as data. It is configured to include a switch 116 (output suppression unit) for outputting a No. 103a.
  • the input control unit 121 of the driver 104 includes, for example, a shift register 123 (holding unit) and a switch 124 (selection unit) as shown in FIG.
  • the shift register 123 sequentially shifts and holds the output of the switch 124 based on the serial transmission clock signal, and the switch 124 responds to the control signal 103b output from the output control unit 111 of the image data signal processing unit 102.
  • the output of the shift register 123 or the data signal 103a output from the output control unit 111 is selectively output.
  • the driver 104 In addition to the input control unit 121, the driver 104 also converts a serial image data signal output from the input control unit 121 into a parallel image data signal 122 as shown in FIG. And a shift register 131 for generating a shift pulse obtained by sequentially shifting the horizontal synchronization pulse by the pixel clock signal, and sampling for sampling the image data signal of each pixel output from the serial-parallel converter 122 according to the shift pulse.
  • Memory 132 hold memory 133 that collectively holds image data signals for one scanning line, level shifter 134 that converts the level of the held image data signal, and level-shifted image data signal that is an analog image signal D / A converter 135 for converting to voltage, and above
  • the image signal voltage buffered is configured to include an output circuit 136 for outputting a driving signal of the liquid crystal display panel 105.
  • the output control unit 111 when an 8-bit image data signal for one pixel a is sequentially input to the shift register 112 together with the serial transmission clock signal, the data is temporarily held in the shift register 112 and then sequentially shifted. In addition to being input to the register 113, the data is output from the output control unit 111 through the switch 116 as the data signal 103 a. Subsequently, when the image data signal for the next pixel b is input and held in the shift register 112, the image data signal for the pixel a is held in the shift register 113.
  • the switch 116 selects the output of the shift register 112, and the image data signal of the pixel b held in the shift register 112 is sequentially output from the output control unit 111 as the data signal 103a.
  • the switch 124 selects the data signal 103a for the pixels a and b input to the input control unit 121 and selects the serial-parallel conversion unit. It outputs to 122.
  • the data signals 103a for the pixels a and b are sequentially input to the shift register 123, and finally the data signal 103a for the pixel b is held.
  • the output control unit 111 when the image data signal for the pixel c is input and held in the shift register 112 and the image data signal for the pixel b is held in the shift register 113, the output data of the pixels b and c If the image data signals coincide with each other, the output of the comparator 114 becomes H (High) level, and the control signal 103b output from the flip-flop 115 is maintained at the H level. Therefore, the switch 116 selects a signal fixed at the L level, and the level transition of the data signal 103a is stopped.
  • the switch 124 selects the output of the shift register 123. Therefore, the data signal 103 a for the pixel b held in the shift register 123 is output to the serial-parallel converter 122. At the same time, the data signal 103a for the pixel b is sequentially input to the shift register 123, and the data signal 103a for the pixel b is held again.
  • the output control unit 111 similarly maintains the control signal 103b output from the flip-flop 115 at the H level, and the data signal 103a is In addition to being fixed to the L level, the input control unit 121 repeatedly outputs the data signal 103 a for the pixel b held in the shift register 123 to the serial-parallel conversion unit 122.
  • the control signal 103 b output from the flip-flop 115 returns to the L level in the output control unit 111. Therefore, the switch 116 outputs the image data signal for the pixel e held in the shift register 112 as the data signal 103a.
  • the switch 124 selects the data signal 103a as the image data signal for the pixel e and outputs it to the serial-parallel conversion unit 122, and the image data signal for the pixel e is received by the shift register 123. Retained.
  • the data signal 103a output from the output control unit 111 is constant.
  • the image data signal held in the shift register 123 is used in the input control unit 121. Therefore, for example, when the luminance of adjacent pixels is the same, the transition of the signal level when the image data signal is transmitted is reduced, and thus EMI and power consumption are reduced.
  • the switch 116 is used to switch the data signal 103a in the output control unit 111.
  • the present invention is not limited to using the switch, and for example, the output of the shift register 112 and the control signal 103b An AND circuit that takes a logical product may be used.
  • the switch 124 in the input control unit 121 the logical product of the output of the shift register 123 and the control signal 103b and the data signal 103a may be taken.
  • a latch that holds the output level of the shift register 112 immediately before the control signal 103b becomes H level may be used instead of the switch 116. In this case, since the level of the data signal 103a does not change when the control signal 103b becomes H level, EMI and power consumption are further reduced.
  • the shift register 123 of the input control unit 121 can output the value of each bit of the held data signal 103a in parallel, and also serves as the serial-parallel conversion unit 122 for the operation of the driver 104. May be.
  • the matching of the transition pattern of the level of the image data signal is detected in pixel units.
  • the transition pattern for a predetermined number of consecutive bits is not limited to pixel units.
  • the level transition of the transmitted signal may be stopped as described above, and the already transmitted data signal may be used.
  • Embodiment 2 For example, when image data signals for red, green, and blue (R, G, B) for displaying color images are transmitted in parallel, the image data signals of the respective colors are described in the first embodiment.
  • the output control unit 111 and the input control unit 121 may be provided as described above, for example, the control signal 103b may be commonly used as shown in FIG.
  • shift registers 112 and 113, a comparator 114, and a switch 116 similar to those of the first embodiment are provided for each color, and an AND circuit 117 that calculates the logical product of the outputs of the comparators 114 for each color,
  • One flip-flop 115 that holds the output is provided.
  • one control signal 103b becomes H level, and the same operation as in the first embodiment is performed. That is, when the colors of adjacent pixels are the same, the luminance for each color is the same, so that the transition of the signal level when the image data signal is transmitted is reduced as in the first embodiment. Therefore, EMI and power consumption are reduced.
  • the number of control signals 103b can be reduced.
  • the number of bits compared by the comparator 114 may be smaller than the number of bits held in the shift registers 112 and 113. Specifically, for example, only the upper 6 bits of the 8-bit image data signals held in the shift registers 112 and 113 are compared, and if they match, the comparator 114 outputs a match detection result.
  • An H level signal is output and held in the flip-flop 115.
  • the control signal 103b is not the output of the flip-flop 115 as it is as in the first embodiment, but is a forced output signal that becomes an L level at a timing corresponding to the lower 2 bits of the image data signal by the AND circuit 118. It is masked with and output.
  • the input control unit 121 the same one as in the first embodiment can be used.
  • the level of the data signal 103a is constant when the upper 6 bits of the image data signal match, that is, when the brightness of the display pixels is not necessarily the same.
  • the control signal 103b is always set to the L level, so that the output from the shift register 112 is transmitted as it is. Therefore, although the lower 2 bits in the image data signal are not suppressed as described above even if they coincide between adjacent pixels, the 6 bits of the upper 6 bits coincide with each other.
  • the frequency of suppressing level transition is high, it is possible to obtain an effect of reducing EMI and power consumption by suppressing level transition as a whole than the configuration of the first embodiment.
  • An AND circuit 118 similar to the output control unit 111 is also provided in the input control unit 121, and the output of the flip-flop 115 is directly transmitted as the control signal 103b between the output control unit 111 and the input control unit 121. In this way, the level transition of the control signal 103b may be reduced.
  • the output of the flip-flop 115 is directly used as the control signal 103b, and the level transition of the data signal 103a for all 8 bits is suppressed as in the first embodiment. Only when the upper 6 bits match and the lower 2 bits are different, the output of the shift register 112 may be forcibly transmitted as the data signal 103a for the lower 2 bits as described above.
  • Embodiment 4 For example, as shown in FIGS. 8 and 9, as the shift register 113 of the output control unit 111 and the shift register 123 of the input control unit 121, image data signals for one or more scanning lines or one or more screens are input. A line memory or a frame memory may be used. When a line memory is used, the level transition of the data signal 103a is suppressed when the image data signals for the pixels at the same position (for example, vertically adjacent pixels) in the adjacent scan lines are the same, and the previous scan line Display is performed using the image data signal held for the upper pixel.
  • the level transition of the data signal 103a is suppressed and held for the pixels of the previous frame. Display is performed using the image data signal. In this case, for example, when a still image is displayed, the level transition of the data signal 103a can be prevented from occurring at all.
  • Embodiment 5 The output control unit 111 and the input control unit 121 as described in the first to fourth embodiments are not limited to being used for transmission of an image data signal between the image data signal processing unit 102 and the driver 104.
  • it may be used for transmission of an image data signal between the image data signal generation unit 101 and the shift register 112.
  • an overdrive processing unit 141 and a frame memory for holding an image data signal for the processing 142 may be used for transmission of one-way or two-way image data signals to / from 142.
  • an EMI reduction effect or the like is particularly easily obtained.
  • the example applied to the image display device which is a liquid crystal television has been described.
  • the present invention is not limited to this.
  • the present invention is applied to an image display device to which an image data signal is input from an external tuner or personal computer. You may make it do.
  • the liquid crystal display panel 105 is not limited to being used.
  • an organic EL (electroluminescent) display panel may be used.
  • the output control unit 111 and the input control unit 121 are configured as a single semiconductor chip, or incorporated in the image data signal processing unit 102, the driver 104, or a circuit chip having a part of the function. It may be done.
  • the image signal data of each pixel is serially transmitted.
  • the present invention is not necessarily limited to this, and a signal that causes a level transition even when a multi-bit data signal is transmitted in parallel. The same method can be applied if the transmission is as follows.
  • the present invention is useful for an image display device such as a liquid crystal display device, an image data signal output device for transmitting an image data signal for image display, and an image data signal input device.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

To minimize signal level transition when an image data signal is transferred, an image data signal output device (111) comprises repeat detector units (112, 113, 114) which detect repeats of image data signal level transition patterns and output a control signal based on the result of the detections, and an output suppression unit (116) which suppresses image data signal output according to the result of the detection, and an image data signal input device (121) comprises a retention unit (123) which retains a previously inputted image data signal, and a selection unit (124) which, on the basis of the control signal, selects either the image data signal which is retained in the retention unit (123) or a newly inputted image data signal.

Description

画像データ信号出力装置、画像データ信号入力装置、および画像表示装置Image data signal output device, image data signal input device, and image display device
　本発明は、液晶表示装置等の画像表示装置、ならびに画像表示のための画像データ信号を伝送する画像データ信号出力装置、および画像データ信号入力装置に関するものである。 The present invention relates to an image display device such as a liquid crystal display device, an image data signal output device for transmitting an image data signal for image display, and an image data signal input device.
　液晶表示装置等の画像表示装置で表示が行われる際には、画像データ信号は、その発生源と、γ補正やオーバードライブ処理などの処理を行う処理部（コントローラ）との間や、上記処理部と、表示部のドライバとの間などで、伝送路を介して伝送される。また、例えば処理部内でも、種々の処理を行う処理回路間で伝送路を介して伝送される。これらの場合、伝送される画像データ信号のレベルが遷移するごとに伝送路に電流が流れるため、ＥＭＩ（Electro Magnetic Interference）が発生したり、消費電力が増大したりしがちである。 When display is performed on an image display device such as a liquid crystal display device, the image data signal is transmitted between the generation source and a processing unit (controller) that performs processing such as γ correction and overdrive processing, or the above processing. For example, between the display unit and the driver of the display unit. Also, for example, within the processing unit, the data is transmitted between processing circuits performing various processes via a transmission path. In these cases, every time the level of the transmitted image data signal changes, a current flows through the transmission path, so that EMI (Electro Magnetic Interference) is likely to occur and power consumption tends to increase.
　画像表示装置においてＥＭＩを低減する技術としては、例えば、複数ビットのパラレル信号が伝送される場合に、信号レベルが遷移するビットの数を検出し、その数が過半数となる場合には、全てのビットの極性を反転させて、信号レベルが遷移するビットの数を半数未満に低減する技術が知られている（例えば、特許文献１参照）。 As a technique for reducing EMI in an image display device, for example, when a parallel signal of a plurality of bits is transmitted, the number of bits whose signal level transitions is detected, and when the number becomes a majority, A technique is known in which the polarity of bits is inverted to reduce the number of bits whose signal level transitions to less than half (for example, see Patent Document 1).
特開２００５－１８１６６９号公報JP 2005-181669 A
　しかしながら、上記のように信号レベルが遷移するビットの数に応じて極性を反転させる技術は、上記遷移するビットの数を常に半数以下に抑えることは可能であるものの、元の遷移ビット数が半数に近い場合には、全てのビットの極性を反転させても、遷移ビット数を大幅に低減することはできず、ＥＭＩや消費電力を大幅に抑制することもできない。 However, although the technique for inverting the polarity according to the number of bits whose signal level transitions as described above can always suppress the number of transition bits to less than half, the original number of transition bits is half. If the polarity of all bits is reversed, the number of transition bits cannot be significantly reduced even if the polarity of all bits is reversed, and EMI and power consumption cannot be significantly suppressed.
　しかも、上記の手法はパラレル信号の伝送が前提であり、シリアル信号の伝送に適用することはできない。 Moreover, the above method is premised on the transmission of parallel signals, and cannot be applied to the transmission of serial signals.
　本発明は、かかる点に鑑みてなされたものであり、その目的は、画像データ信号が伝送される際の信号レベルの遷移を低減して、ＥＭＩや消費電力の低減などを容易に可能にすることにある。 The present invention has been made in view of this point, and an object of the present invention is to easily reduce EMI and power consumption by reducing signal level transition when an image data signal is transmitted. There is.
　第１の発明は、
　画像データ信号を伝送するために出力する画像データ信号出力装置であって、
　画像データ信号のレベルの遷移パターンの繰り返しを検出し、検出結果に応じた制御信号を出力する繰り返し検出部と、
　上記検出結果に応じて、画像データ信号の出力を抑制する出力抑制部と、
　を備えたことを特徴とする。 The first invention is
An image data signal output device for outputting an image data signal for transmission,
A repetitive detection unit that detects repetitive transition patterns of the level of the image data signal and outputs a control signal according to the detection result;
According to the detection result, an output suppression unit that suppresses the output of the image data signal,
It is provided with.
　これにより、画像データ信号のレベルの遷移パターンが繰り返されていれば、その画像データ信号は、出力を抑制されても、先立つ画像データ信号のレベルの遷移パターンを用いて再現することが容易にできる。したがって、適切な画像データ信号の伝送を可能にしつつ、出力信号のレベルの遷移を抑制して、ＥＭＩや消費電力の低減を容易に図ることができる。 Thus, if the transition pattern of the level of the image data signal is repeated, the image data signal can be easily reproduced using the transition pattern of the level of the previous image data signal even if the output is suppressed. . Therefore, it is possible to easily reduce the EMI and the power consumption by suppressing the transition of the level of the output signal while enabling the transmission of an appropriate image data signal.
　第２の発明は、
　第１の発明の画像データ信号出力装置であって、
　上記検出部は、
　以前に入力された画像データ信号を保持する保持部と、
　新たに入力された画像データ信号と、上記保持部に保持された画像データ信号とを比較する比較部と、
　を備えたことを特徴とする。 The second invention is
An image data signal output device according to a first invention,
The detection unit is
A holding unit for holding a previously input image data signal;
A comparison unit that compares the newly input image data signal with the image data signal held in the holding unit;
It is provided with.
　これにより、画像データ信号のレベルの遷移パターンの繰り返しを容易に検出することができる。 This makes it possible to easily detect the repetition of the level transition pattern of the image data signal.
　第３の発明は、
　第２の発明の画像データ信号出力装置であって、
　上記比較部は、上記保持部に保持された画像データ信号よりも少ないビット数について、上記新たに入力された画像データ信号との比較を行うように構成されていることを特徴とする。 The third invention is
An image data signal output device according to a second invention,
The comparison unit is configured to perform comparison with the newly input image data signal for a smaller number of bits than the image data signal held in the holding unit.
　これにより、画像データ信号のレベルの遷移パターンが繰り返されたと判定される頻度が増大し得るので、出力信号のレベルの遷移が抑制される可能性を高くすることができる。 This can increase the frequency with which it is determined that the level transition pattern of the image data signal has been repeated, thereby increasing the possibility that the level transition of the output signal is suppressed.
　第４の発明は、
　第２の発明および第３の発明のうち何れか１つの画像データ信号出力装置であって、
　上記保持部は、１走査ライン以上、または１画面以上の画素についての画像データ信号を保持し、
　上記比較部は、先行する走査ラインまたは画面における、新たに画像データ信号が入力された画素に対応する位置の画素の画像データ信号と、上記新たに入力された画像データ信号とを比較するように構成されていることを特徴とする。 The fourth invention is:
An image data signal output device according to any one of the second and third inventions,
The holding unit holds an image data signal for pixels of one scanning line or more, or one screen or more,
The comparison unit compares an image data signal of a pixel at a position corresponding to a pixel to which a new image data signal is input on the preceding scanning line or screen with the newly input image data signal. It is configured.
　これにより、隣り合う走査ラインにおける同一位置の画素や、相前後するフレームの同一位置の画素についての画像データ信号が同じ場合に、画像データ信号の出力が抑制されるので、例えば静止画が表示される場合などに、やはり、ＥＭＩや消費電力の低減を容易に図ることができる。 This suppresses output of the image data signal when the image data signal is the same for the pixel at the same position in adjacent scanning lines or the pixel at the same position in successive frames, so that, for example, a still image is displayed. In such a case, EMI and power consumption can be easily reduced.
　第５の発明は、
　第１の発明から第４の発明のうち何れか１つの画像データ信号出力装置であって、
　上記出力抑制部は、画像データ信号のレベルの遷移パターンの繰り返しが検出された場合に、出力される画像データ信号のレベルを、その時点のレベル、およびあらかじめ定められたレベルのうち何れか一方に固定するように構成されていることを特徴とする。 The fifth invention is:
An image data signal output device according to any one of the first to fourth inventions,
The output suppression unit may change the level of the output image data signal to one of a current level and a predetermined level when a repetition of the transition pattern of the level of the image data signal is detected. It is configured to be fixed.
　これにより、上記繰り返しが検出された時点で、出力される画像データ信号のレベルの遷移が生じないようにして、一層、消費電力等の低減を図ったり、または、あらかじめ定められたレベルに固定するようにして構成の簡素化を図ったりすることができる。 As a result, when the repetition is detected, the level of the output image data signal does not change, and the power consumption or the like is further reduced, or the level is fixed to a predetermined level. In this way, the configuration can be simplified.
　第６の発明は、
　第１の発明から第５の発明のうち何れか１つの画像データ信号出力装置であって、
　上記検出部は、あらかじめ定められたビット数の画像データ信号について、上記レベルの遷移パターンの繰り返しの検出をするように構成されていることを特徴とする。 The sixth invention is:
An image data signal output device according to any one of the first to fifth inventions,
The detection unit is configured to detect repetition of the transition pattern at the level for an image data signal having a predetermined number of bits.
　これにより、例えば画素単位であるかどうかに係わらず、画像データ信号のレベルの遷移パターンの繰り返しを検出し、出力信号のレベルの遷移を抑制して、ＥＭＩや消費電力の低減を容易に図ることができる。 This makes it possible to easily reduce the EMI and power consumption by detecting the repetition of the transition pattern of the level of the image data signal regardless of whether it is, for example, a pixel unit, and suppressing the transition of the level of the output signal. Can do.
　第７の発明は、
　第６の発明の画像データ信号出力装置であって、
　上記検出部は、画素単位の画像データ信号について、上記レベルの遷移パターンの繰り返しの検出をするように構成されていることを特徴とする。 The seventh invention
An image data signal output device according to a sixth invention,
The detection unit is configured to detect the repetition of the transition pattern at the level with respect to an image data signal in pixel units.
　これにより、画素単位での処理を容易に行うことができる。 This makes it possible to easily perform processing in units of pixels.
　第８の発明は、
　第１の発明から第７の発明のうち何れか１つの画像データ信号出力装置であって、
　上記検出部は、複数系統の画像データ信号のレベルの遷移パターンが何れも繰り返されていることを検出するように構成されていることを特徴とする。 The eighth invention
An image data signal output device according to any one of the first to seventh inventions,
The detection unit is configured to detect that all the level transition patterns of the image data signals of a plurality of systems are repeated.
　第９の発明は、
　第８の発明の画像データ信号出力装置であって、
　上記複数系統の画像データ信号は、赤、緑、および青の画素についての画像データ信号であることを特徴とする。 The ninth invention
An image data signal output device according to an eighth invention,
The plurality of image data signals are image data signals for red, green, and blue pixels.
　これらにより、カラー画像が表示される場合などの複数系統の画像データ信号の伝送について、検出信号の数を低減することができる。 Thus, the number of detection signals can be reduced for transmission of a plurality of image data signals such as when a color image is displayed.
　第１０の発明は、
　第１の発明から第９の発明のうち何れか１つの画像データ信号出力装置から伝送された画像データ信号が入力される画像データ信号入力装置であって、
　以前に入力された画像データ信号を保持する保持部と、
　上記制御信号に基づいて、上記保持部に保持された画像データ信号、または新たに入力された画像データ信号を選択する選択部と、
　を備えたことを特徴とする。 The tenth invention is
An image data signal input device to which an image data signal transmitted from any one of the image data signal output devices of the first invention to the ninth invention is input,
A holding unit for holding a previously input image data signal;
A selection unit that selects an image data signal held in the holding unit or a newly input image data signal based on the control signal;
It is provided with.
　これにより、画像データ信号のレベルの遷移パターンが繰り返されていて、その画像データ信号の出力が抑制された場合に、保持部に保持された画像データ信号が選択されることにより、出力を抑制された画像データ信号を再現することが容易にできる。 Thus, when the transition pattern of the level of the image data signal is repeated and the output of the image data signal is suppressed, the output is suppressed by selecting the image data signal held in the holding unit. The reproduced image data signal can be easily reproduced.
　第１１の発明は、
　第１０の発明の画像データ信号入力装置であって、
　上記保持部は、直列的に入力されて保持した一連の画像データ信号を並列的に出力する直列並列変換部として用いられるように構成されていることを特徴とする。 The eleventh invention is
An image data signal input device according to a tenth invention,
The holding unit is configured to be used as a serial-to-parallel conversion unit that outputs a series of image data signals input and held in series in parallel.
　これにより、構成要素を兼用化して、回路構成の簡潔化を図ることができる。 This makes it possible to simplify the circuit configuration by combining the components.
　第１２の発明は、
　画像表示装置であって、
　第１の発明から第９の発明のうち何れか１つの画像データ信号出力装置と、
　第１０の発明および第１１の発明のうち何れか１つの画像データ信号入力装置と、
　を備えたことを特徴とする。 The twelfth invention is
An image display device,
Any one of the first to ninth image data signal output devices;
Any one of the tenth invention and the eleventh invention, the image data signal input device;
It is provided with.
　第１３の発明は、
　第１２の発明の画像表示装置であって、さらに、
　画像データ信号の処理を行う画像データ信号処理部と、
　画像の表示を行う画像表示部と、
　を備え、
　上記画像データ信号処理部に、上記画像データ信号出力装置が設けられ、
　上記画像表示部に、上記画像データ信号入力装置が設けられていることを特徴とする。 The thirteenth invention is
An image display device according to a twelfth aspect of the invention,
An image data signal processor for processing the image data signal;
An image display unit for displaying an image;
With
The image data signal processing unit is provided with the image data signal output device,
The image display unit is provided with the image data signal input device.
　第１４の発明は、
　第１２の発明および第１３の発明のうち何れか１つの画像表示装置であって、さらに、
　画像データ信号を生成する画像データ信号生成部を備え、
　上記画像データ信号生成部に、上記画像データ信号出力装置が設けられていることを特徴とする。 The fourteenth invention is
The image display device according to any one of the twelfth and thirteenth inventions,
An image data signal generator for generating an image data signal;
The image data signal generation unit is provided with the image data signal output device.
　第１５の発明は、
　第１２の発明から第１４の発明のうち何れか１つの画像表示装置であって、さらに、
　画像データ信号に対してオーバードライブ処理を行うオーバードライブ処理部と、
　上記オーバードライブ処理のための画像データ信号を保持するフレームメモリと、
　を備え、
　上記オーバードライブ処理部に、上記画像データ信号出力装置、および上記画像データ信号入力装置のうち少なくとも一方が設けられ、
　上記フレームメモリに、上記オーバードライブ処理部に対応する上記画像データ信号出力装置、および上記画像データ信号入力装置のうち少なくとも一方が設けられていることを特徴とする。 The fifteenth invention
The image display device according to any one of the twelfth to fourteenth aspects, further comprising:
An overdrive processing unit that performs overdrive processing on the image data signal;
A frame memory for holding an image data signal for the overdrive process;
With
At least one of the image data signal output device and the image data signal input device is provided in the overdrive processing unit,
The frame memory is provided with at least one of the image data signal output device and the image data signal input device corresponding to the overdrive processing unit.
　これらにより、画像データ信号処理部と画像表示部との間や、画像データ信号生成部と生成された画像データ信号を受け取る部分との間、またはオーバードライブ処理部とフレームメモリとの間などで、上記のように画像データ信号のレベルの遷移を抑制して、ＥＭＩや消費電力の低減を容易に図ることができる。 With these, between the image data signal processing unit and the image display unit, between the image data signal generation unit and the part that receives the generated image data signal, or between the overdrive processing unit and the frame memory, etc. As described above, it is possible to easily reduce the EMI and the power consumption by suppressing the transition of the level of the image data signal.
　本発明によれば、画像データ信号が伝送される際の信号レベルの遷移を低減することにより、ＥＭＩや消費電力の低減などが容易に可能になる。 According to the present invention, it is possible to easily reduce EMI and power consumption by reducing the transition of the signal level when the image data signal is transmitted.
実施形態１の画像表示装置の構成を示すブロック図である。1 is a block diagram illustrating a configuration of an image display device according to a first embodiment. 実施形態１の画像データ信号処理部１０２、およびドライバ１０４の具体的な構成を示すブロック図である。3 is a block diagram illustrating specific configurations of an image data signal processing unit 102 and a driver 104 according to Embodiment 1. FIG. 実施形態１の出力制御部１１１の具体的な構成を示す回路図である。3 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 1. FIG. 実施形態１の入力制御部１２１の具体的な構成を示す回路図である。FIG. 3 is a circuit diagram illustrating a specific configuration of an input control unit 121 according to the first embodiment. 実施形態１の画像データ信号の伝送動作を示すタイミングチャートである。3 is a timing chart illustrating an image data signal transmission operation according to the first exemplary embodiment. 実施形態２の出力制御部１１１の具体的な構成を示す回路図である。6 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 2. FIG. 実施形態３の出力制御部１１１の具体的な構成を示す回路図である。10 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to Embodiment 3. FIG. 実施形態４の出力制御部１１１の具体的な構成を示す回路図である。FIG. 10 is a circuit diagram illustrating a specific configuration of an output control unit 111 according to a fourth embodiment. 実施形態４の入力制御部１２１の具体的な構成を示す回路図である。FIG. 10 is a circuit diagram illustrating a specific configuration of an input control unit 121 according to the fourth embodiment. 実施形態５の画像表示装置の要部の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a main part of an image display device according to a fifth embodiment. 実施形態５の他の画像表示装置の要部の構成を示すブロック図である。FIG. 10 is a block diagram illustrating a configuration of a main part of another image display device according to the fifth embodiment.
　以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、以下の各実施形態において、他の実施形態と同様の機能を有する構成要素については同一の符号を付して説明を省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each of the following embodiments, components having functions similar to those of the other embodiments are denoted by the same reference numerals and description thereof is omitted.
　《実施形態１》
　本発明の画像表示装置の例として、テレビジョン放送を受信して液晶表示パネルに画像を表示する、いわゆる液晶テレビの例について説明する。 Embodiment 1
As an example of the image display device of the present invention, an example of a so-called liquid crystal television that receives a television broadcast and displays an image on a liquid crystal display panel will be described.
　この液晶テレビは、例えば図１に示すように、テレビジョン放送を受信して画像データ信号を出力する画像データ信号生成部１０１と、上記画像データ信号に対してγ補正やオーバードライブ処理を施す画像データ信号処理部１０２と、液晶表示パネル１０５と、この液晶表示パネル１０５を駆動する駆動信号を発生するドライバ１０４とを備えている。上記画像データ信号処理部１０２とドライバ１０４とは、例えばフレキシブル基板１０３によって接続されている。また、上記画像データ信号生成部１０１と画像データ信号処理部１０２との間や、画像データ信号処理部１０２とドライバ１０４との間での画像データ信号の伝送は、特に限定されないが、例えばＬＶＤＳ（Low voltage differential signaling）やｍｉｎｉ－ＬＶＤＳによって行われる。 For example, as shown in FIG. 1, the liquid crystal television includes an image data signal generation unit 101 that receives a television broadcast and outputs an image data signal, and an image that performs γ correction and overdrive processing on the image data signal. A data signal processing unit 102, a liquid crystal display panel 105, and a driver 104 that generates a drive signal for driving the liquid crystal display panel 105 are provided. The image data signal processing unit 102 and the driver 104 are connected by a flexible substrate 103, for example. Further, the transmission of the image data signal between the image data signal generation unit 101 and the image data signal processing unit 102 or between the image data signal processing unit 102 and the driver 104 is not particularly limited. For example, LVDS ( Low voltage differential signaling) or mini-LVDS.
　上記画像データ信号処理部１０２、およびドライバ１０４は、図２に示すように、それぞれ出力制御部１１１（画像データ信号出力装置）、または入力制御部１２１（画像データ信号入力装置）を備え、これらの間で、後述するシリアルのデータ信号１０３ａ、および制御信号１０３ｂが送受されるようになっている。 As shown in FIG. 2, the image data signal processing unit 102 and the driver 104 include an output control unit 111 (image data signal output device) or an input control unit 121 (image data signal input device), respectively. A serial data signal 103a and a control signal 103b, which will be described later, are transmitted and received.
　上記画像データ信号処理部１０２の出力制御部１１１は、例えば図３に示すように、γ補正等の処理回路からシリアルに入力される例えば８ビットの画像データ信号をシリアル伝送クロック信号に応じて順次シフトして保持する２段の８ビットのシフトレジスタ１１２，１１３（繰り返し検出部の一部、保持部）と、これらのシフトレジスタ１１２，１１３に保持された８ビットの値が一致したことを検出するコンパレータ１１４（繰り返し検出部の一部）と、その検出結果をシリアル伝送クロック信号が８分周された８分周クロック信号に応じて保持し、制御信号１０３ｂとして出力するフリップフロップと、上記制御信号１０３ｂに応じて、シフトレジスタ１１２の出力、またはＬ（Ｌｏｗ）レベルに固定された信号を選択的にデータ信号１０３ａとして出力するスイッチ１１６（出力抑制部）とを備えて構成されている。 For example, as shown in FIG. 3, the output control unit 111 of the image data signal processing unit 102 sequentially receives, for example, 8-bit image data signals serially input from a processing circuit such as γ correction according to the serial transmission clock signal. Detects that the 8-bit shift registers 112 and 113 (part of the repetitive detection unit, holding unit) that are held by shifting coincide with the 8-bit values held in these shift registers 112 and 113. Comparator 114 (a part of the repetitive detection unit), a flip-flop that holds the detection result in accordance with the divided-by-8 clock signal obtained by dividing the serial transmission clock signal by 8, and outputs the control signal 103b, and the control In accordance with the signal 103b, the output of the shift register 112 or the signal fixed to the L (Low) level is selectively selected as data. It is configured to include a switch 116 (output suppression unit) for outputting a No. 103a.
　一方、ドライバ１０４の入力制御部１２１は、例えば図４に示すように、シフトレジスタ１２３（保持部）と、スイッチ１２４（選択部）とを備えて構成されている。シフトレジスタ１２３は、シリアル伝送クロック信号に基づいてスイッチ１２４の出力を順次シフトして保持し、スイッチ１２４は、画像データ信号処理部１０２の出力制御部１１１から出力された制御信号１０３ｂに応じて、上記シフトレジスタ１２３の出力、または出力制御部１１１から出力されたデータ信号１０３ａを選択的に出力するようになっている。 On the other hand, the input control unit 121 of the driver 104 includes, for example, a shift register 123 (holding unit) and a switch 124 (selection unit) as shown in FIG. The shift register 123 sequentially shifts and holds the output of the switch 124 based on the serial transmission clock signal, and the switch 124 responds to the control signal 103b output from the output control unit 111 of the image data signal processing unit 102. The output of the shift register 123 or the data signal 103a output from the output control unit 111 is selectively output.
　ドライバ１０４は、また、上記入力制御部１２１に加えて、図３に示すように、入力制御部１２１から出力されるシリアルの画像データ信号をパラレルの画像データ信号に変換するシリアル－パラレル変換部１２２と、画素クロック信号によって水平同期パルスを順次シフトしたシフトパルスを発生するシフトレジスタ１３１と、上記シフトパルスに応じて、シリアル－パラレル変換部１２２から出力される各画素の画像データ信号をサンプリングするサンプリングメモリ１３２と、１走査ライン分の画像データ信号を一括して保持するホールドメモリ１３３と、保持された画像データ信号のレベルを変換するレベルシフタ１３４と、レベルシフトされた画像データ信号をアナログの画像信号電圧に変換するＤ／Ａコンバータ１３５と、上記画像信号電圧をバッファリングして、液晶表示パネル１０５の駆動信号を出力する出力回路１３６とを備えて構成されている。 In addition to the input control unit 121, the driver 104 also converts a serial image data signal output from the input control unit 121 into a parallel image data signal 122 as shown in FIG. And a shift register 131 for generating a shift pulse obtained by sequentially shifting the horizontal synchronization pulse by the pixel clock signal, and sampling for sampling the image data signal of each pixel output from the serial-parallel converter 122 according to the shift pulse. Memory 132, hold memory 133 that collectively holds image data signals for one scanning line, level shifter 134 that converts the level of the held image data signal, and level-shifted image data signal that is an analog image signal D / A converter 135 for converting to voltage, and above The image signal voltage buffered, is configured to include an output circuit 136 for outputting a driving signal of the liquid crystal display panel 105.
　上記のように構成された画像表示装置において、画像データ信号処理部１０２の出力制御部１１１と、ドライバ１０４の入力制御部１２１との間で行われる画像データ信号の伝送動作について、図５を参照して説明する。 In the image display apparatus configured as described above, the transmission operation of the image data signal performed between the output control unit 111 of the image data signal processing unit 102 and the input control unit 121 of the driver 104 is described with reference to FIG. To explain.
　まず、出力制御部１１１において、１つの画素ａについての８ビットの画像データ信号がシリアル伝送クロック信号と共に順次シフトレジスタ１１２に入力されると、このシフトレジスタ１１２に一旦保持された後、順次、シフトレジスタ１１３に入力されるとともに、スイッチ１１６を介してデータ信号１０３ａとして出力制御部１１１から出力される。続いて次の画素ｂについての画像データ信号がシフトレジスタ１１２に入力されて保持されるときには、上記画素ａについての画像データ信号がシフトレジスタ１１３に保持される。このとき、画素ａ，ｂの画像データ信号が同じでなければ、コンパレータ１１４の出力はＬレベルになり、フリップフロップ１１５から出力される制御信号１０３ｂもＬレベルに保たれる。そこで、スイッチ１１６はシフトレジスタ１１２の出力を選択し、シフトレジスタ１１２に保持された画素ｂの画像データ信号がデータ信号１０３ａとして出力制御部１１１から順次出力される。 First, in the output control unit 111, when an 8-bit image data signal for one pixel a is sequentially input to the shift register 112 together with the serial transmission clock signal, the data is temporarily held in the shift register 112 and then sequentially shifted. In addition to being input to the register 113, the data is output from the output control unit 111 through the switch 116 as the data signal 103 a. Subsequently, when the image data signal for the next pixel b is input and held in the shift register 112, the image data signal for the pixel a is held in the shift register 113. At this time, if the image data signals of the pixels a and b are not the same, the output of the comparator 114 becomes L level, and the control signal 103b output from the flip-flop 115 is also kept at L level. Therefore, the switch 116 selects the output of the shift register 112, and the image data signal of the pixel b held in the shift register 112 is sequentially output from the output control unit 111 as the data signal 103a.
　このとき、入力制御部１２１では、制御信号１０３ｂが上記のようにＬレベルなので、スイッチ１２４は入力制御部１２１に入力された画素ａ，ｂについてのデータ信号１０３ａを選択してシリアル－パラレル変換部１２２に出力する。また、同時に、上記画素ａ，ｂについてのデータ信号１０３ａはシフトレジスタ１２３にも順次入力され、最終的に画素ｂについてのデータ信号１０３ａが保持された状態になる。 At this time, in the input control unit 121, since the control signal 103b is at the L level as described above, the switch 124 selects the data signal 103a for the pixels a and b input to the input control unit 121 and selects the serial-parallel conversion unit. It outputs to 122. At the same time, the data signals 103a for the pixels a and b are sequentially input to the shift register 123, and finally the data signal 103a for the pixel b is held.
　次に、出力制御部１１１において、画素ｃについての画像データ信号がシフトレジスタ１１２に入力されて保持され、画素ｂについての画像データ信号がシフトレジスタ１１３に保持されたときに、画素ｂ，ｃの画像データ信号が一致していたとすると、コンパレータ１１４の出力はＨ（Ｈｉｇｈ）レベルになり、フリップフロップ１１５から出力される制御信号１０３ｂはＨレベルに遷移して保たれる。そこで、スイッチ１１６はＬレベルに固定された信号を選択し、データ信号１０３ａのレベル遷移が停止される。 Next, in the output control unit 111, when the image data signal for the pixel c is input and held in the shift register 112 and the image data signal for the pixel b is held in the shift register 113, the output data of the pixels b and c If the image data signals coincide with each other, the output of the comparator 114 becomes H (High) level, and the control signal 103b output from the flip-flop 115 is maintained at the H level. Therefore, the switch 116 selects a signal fixed at the L level, and the level transition of the data signal 103a is stopped.
　このとき、入力制御部１２１では、制御信号１０３ｂが上記のようにＨレベルになるので、スイッチ１２４はシフトレジスタ１２３の出力を選択する。そこで、シフトレジスタ１２３に保持された画素ｂについてのデータ信号１０３ａが、シリアル－パラレル変換部１２２に出力される。また、同時に、上記画素ｂについてのデータ信号１０３ａはシフトレジスタ１２３にも順次入力され、再度、画素ｂについてのデータ信号１０３ａが保持された状態になる。 At this time, in the input control unit 121, since the control signal 103b becomes H level as described above, the switch 124 selects the output of the shift register 123. Therefore, the data signal 103 a for the pixel b held in the shift register 123 is output to the serial-parallel converter 122. At the same time, the data signal 103a for the pixel b is sequentially input to the shift register 123, and the data signal 103a for the pixel b is held again.
　さらに、次の画素ｄについての画像データ信号も画素ｂと一致していたとすると、出力制御部１１１では、同様にフリップフロップ１１５から出力される制御信号１０３ｂはＨレベルに保たれ、データ信号１０３ａはＬレベルに固定されるとともに、入力制御部１２１では、シフトレジスタ１２３に保持されている画素ｂについてのデータ信号１０３ａが繰り返しシリアル－パラレル変換部１２２に出力される。 Further, assuming that the image data signal for the next pixel d also matches the pixel b, the output control unit 111 similarly maintains the control signal 103b output from the flip-flop 115 at the H level, and the data signal 103a is In addition to being fixed to the L level, the input control unit 121 repeatedly outputs the data signal 103 a for the pixel b held in the shift register 123 to the serial-parallel conversion unit 122.
　その後、さらに次の画素ｅについての画像データ信号が画素ｂと一致していなかった場合には、出力制御部１１１において、フリップフロップ１１５から出力される制御信号１０３ｂがＬレベルに戻る。そこで、スイッチ１１６はシフトレジスタ１１２に保持された画素ｅについての画像データ信号をデータ信号１０３ａとして出力する。また、入力制御部１２１では、スイッチ１２４は上記画素ｅについての画像データ信号としてデータ信号１０３ａを選択してシリアル－パラレル変換部１２２に出力するとともに、その画素ｅについての画像データ信号がシフトレジスタ１２３に保持される。 Thereafter, when the image data signal for the next pixel e does not coincide with the pixel b, the control signal 103 b output from the flip-flop 115 returns to the L level in the output control unit 111. Therefore, the switch 116 outputs the image data signal for the pixel e held in the shift register 112 as the data signal 103a. In the input control unit 121, the switch 124 selects the data signal 103a as the image data signal for the pixel e and outputs it to the serial-parallel conversion unit 122, and the image data signal for the pixel e is received by the shift register 123. Retained.
　上記のように、連続する画素の画像データ信号が一致している場合、すなわち同一の画像データ信号のレベルの遷移パターン繰り返される場合には、出力制御部１１１から出力されるデータ信号１０３ａは一定のレベルに固定され、入力制御部１２１においてはシフトレジスタ１２３に保持された画像データ信号が用いられる。したがって、例えば隣り合う画素どうしの輝度が同じである場合に、画像データ信号が伝送される際の信号レベルの遷移が低減され、したがって、ＥＭＩや消費電力が低減される。 As described above, when the image data signals of consecutive pixels match, that is, when the transition pattern of the same image data signal level is repeated, the data signal 103a output from the output control unit 111 is constant. The image data signal held in the shift register 123 is used in the input control unit 121. Therefore, for example, when the luminance of adjacent pixels is the same, the transition of the signal level when the image data signal is transmitted is reduced, and thus EMI and power consumption are reduced.
　《実施形態１の変形例》
　なお、上記の例では、出力制御部１１１でデータ信号１０３ａの切り替えにスイッチ１１６が用いられる例を示したが、切り替えスイッチを用いるのに限らず、例えばシフトレジスタ１１２の出力と制御信号１０３ｂとの論理積をとるＡＮＤ回路を用いるなどしてもよい。同様に、入力制御部１２１でスイッチ１２４として、シフトレジスタ１２３の出力と制御信号１０３ｂとの論理積と、データ信号１０３ａとの論理和をとるようにしたりしてもよい。 << Modification of Embodiment 1 >>
In the above example, the switch 116 is used to switch the data signal 103a in the output control unit 111. However, the present invention is not limited to using the switch, and for example, the output of the shift register 112 and the control signal 103b An AND circuit that takes a logical product may be used. Similarly, as the switch 124 in the input control unit 121, the logical product of the output of the shift register 123 and the control signal 103b and the data signal 103a may be taken.
　さらに、スイッチ１１６に代えて、制御信号１０３ｂがＨレベルになる直前のシフトレジスタ１１２の出力レベルを保持するラッチを用いるなどしてもよい。この場合には、制御信号１０３ｂがＨレベルになる際にデータ信号１０３ａのレベル変化が生じることはないので、一層、ＥＭＩや消費電力が低減されることになる。 Furthermore, instead of the switch 116, a latch that holds the output level of the shift register 112 immediately before the control signal 103b becomes H level may be used. In this case, since the level of the data signal 103a does not change when the control signal 103b becomes H level, EMI and power consumption are further reduced.
　また、上記入力制御部１２１のシフトレジスタ１２３は、保持したデータ信号１０３ａの各ビットの値を並列に出力し得るようにして、ドライバ１０４の動作のためのシリアル－パラレル変換部１２２を兼ねるようにしてもよい。 Also, the shift register 123 of the input control unit 121 can output the value of each bit of the held data signal 103a in parallel, and also serves as the serial-parallel conversion unit 122 for the operation of the driver 104. May be.
　また、上記の例では、画素単位で画像データ信号のレベルの遷移パターンの一致が検出される例を示したが、画素単位に限らず、連続する所定数ビットについての遷移パターンが一致している場合に、上記のように伝送される信号のレベル遷移が停止され、既に伝送されたデータ信号が用いられるようにしてもよい。 Further, in the above example, an example is shown in which the matching of the transition pattern of the level of the image data signal is detected in pixel units. However, the transition pattern for a predetermined number of consecutive bits is not limited to pixel units. In this case, the level transition of the transmitted signal may be stopped as described above, and the already transmitted data signal may be used.
　《実施形態２》
　例えばカラー画像表示するための赤、緑、青（Ｒ、Ｇ、Ｂ）についての画像データ信号が並列に伝送される場合には、それぞれの色の画像データ信号ごとに、上記実施形態１で説明したような出力制御部１１１、および入力制御部１２１が設けられるようにしてもよいが、例えば図６に示すように制御信号１０３ｂが共通に用いられるようにしてもよい。 << Embodiment 2 >>
For example, when image data signals for red, green, and blue (R, G, B) for displaying color images are transmitted in parallel, the image data signals of the respective colors are described in the first embodiment. Although the output control unit 111 and the input control unit 121 may be provided as described above, for example, the control signal 103b may be commonly used as shown in FIG.
　同図の例では、各色ごとに、実施形態１と同様のシフトレジスタ１１２，１１３、コンパレータ１１４、およびスイッチ１１６が設けられるとともに、各色のコンパレータ１１４の出力の論理積をとるＡＮＤ回路１１７と、その出力を保持する１つのフリップフロップ１１５とが設けられている。このように構成される場合には、各色についての画像データ信号が何れも一致している場合に、１本の制御信号１０３ｂがＨレベルになり、実施形態１と同様の動作が行われる。すなわち、隣り合う画素どうしの色が同じである場合には、各色についての輝度が同じになるので、やはり実施形態１と同様に、画像データ信号が伝送される際の信号レベルの遷移が低減され、したがって、ＥＭＩや消費電力が低減される。しかも、制御信号１０３ｂの数を少なく抑えることができる。 In the example shown in the figure, shift registers 112 and 113, a comparator 114, and a switch 116 similar to those of the first embodiment are provided for each color, and an AND circuit 117 that calculates the logical product of the outputs of the comparators 114 for each color, One flip-flop 115 that holds the output is provided. In such a configuration, when the image data signals for the respective colors match, one control signal 103b becomes H level, and the same operation as in the first embodiment is performed. That is, when the colors of adjacent pixels are the same, the luminance for each color is the same, so that the transition of the signal level when the image data signal is transmitted is reduced as in the first embodiment. Therefore, EMI and power consumption are reduced. In addition, the number of control signals 103b can be reduced.
　《実施形態３》
　例えば図７に示すように、シフトレジスタ１１２，１１３に保持されるビット数に対して、コンパレータ１１４によって比較されるビット数の方が少なくなるようにしてもよい。具体的には、例えばシフトレジスタ１１２，１１３に保持された８ビットの画像データ信号のうち、上位の６ビットだけが比較され、これらが一致している場合には、コンパレータ１１４から一致検出結果としてＨレベルの信号が出力され、フリップフロップ１１５に保持されるようになっている。制御信号１０３ｂは、実施形態１のようにフリップフロップ１１５の出力がそのまま出力されるのではなく、ＡＮＤ回路１１８により、画像データ信号の下位の２ビットに対応するタイミングでＬレベルになる強制出力信号でマスクされて出力されるようになっている。入力制御部１２１としては、実施形態１と同じものを用いることができる。 << Embodiment 3 >>
For example, as shown in FIG. 7, the number of bits compared by the comparator 114 may be smaller than the number of bits held in the shift registers 112 and 113. Specifically, for example, only the upper 6 bits of the 8-bit image data signals held in the shift registers 112 and 113 are compared, and if they match, the comparator 114 outputs a match detection result. An H level signal is output and held in the flip-flop 115. The control signal 103b is not the output of the flip-flop 115 as it is as in the first embodiment, but is a forced output signal that becomes an L level at a timing corresponding to the lower 2 bits of the image data signal by the AND circuit 118. It is masked with and output. As the input control unit 121, the same one as in the first embodiment can be used.
　このように構成されている場合には、画像データ信号の上位の６ビットが一致している場合、すなわち表示画素の輝度が全く同一でなくても近い場合には、データ信号１０３ａのレベルが一定に保たれて遷移が抑制される。ただし、下位の２ビットについては、常に制御信号１０３ｂがＬレベルにされることによって、シフトレジスタ１１２からの出力がそのまま伝送される。したがって、画像データ信号における下位の２ビットについては、隣り合う画素間で一致していたとしても上記のようにレベル遷移の抑制はなされないが、上位の６ビットが一致することによって、その６ビットについてのレベル遷移を抑制される頻度が高い場合には、実施形態１の構成よりも全体としてのレベル遷移抑制によるＥＭＩや消費電力の低減効果を得ることができる。 In the case of such a configuration, the level of the data signal 103a is constant when the upper 6 bits of the image data signal match, that is, when the brightness of the display pixels is not necessarily the same. To suppress the transition. However, for the lower two bits, the control signal 103b is always set to the L level, so that the output from the shift register 112 is transmitted as it is. Therefore, although the lower 2 bits in the image data signal are not suppressed as described above even if they coincide between adjacent pixels, the 6 bits of the upper 6 bits coincide with each other. When the frequency of suppressing level transition is high, it is possible to obtain an effect of reducing EMI and power consumption by suppressing level transition as a whole than the configuration of the first embodiment.
　なお、上記出力制御部１１１と同様のＡＮＤ回路１１８を入力制御部１２１にも設けて、出力制御部１１１と入力制御部１２１との間ではフリップフロップ１１５の出力がそのまま制御信号１０３ｂとして伝送されるようにして、制御信号１０３ｂのレベル遷移も低減されるようにしてもよい。 An AND circuit 118 similar to the output control unit 111 is also provided in the input control unit 121, and the output of the flip-flop 115 is directly transmitted as the control signal 103b between the output control unit 111 and the input control unit 121. In this way, the level transition of the control signal 103b may be reduced.
　また、画像データ信号の全８ビットが一致する場合には、フリップフロップ１１５の出力をそのまま制御信号１０３ｂとして、実施形態１と同様に全８ビットについてのデータ信号１０３ａのレベル遷移を抑制するとともに、上位の６ビットが一致し、下位の２ビットが異なる場合にだけ、その下位の２ビットについて上記のように強制的にシフトレジスタ１１２の出力をデータ信号１０３ａとして伝送するようにしてもよい。 When all 8 bits of the image data signal match, the output of the flip-flop 115 is directly used as the control signal 103b, and the level transition of the data signal 103a for all 8 bits is suppressed as in the first embodiment. Only when the upper 6 bits match and the lower 2 bits are different, the output of the shift register 112 may be forcibly transmitted as the data signal 103a for the lower 2 bits as described above.
　《実施形態４》
　例えば図８、および図９に示すように、出力制御部１１１のシフトレジスタ１１３、および入力制御部１２１のシフトレジスタ１２３として、１以上の走査ライン分、または１以上の画面分の画像データ信号を保持するラインメモリ、またはフレームメモリを用いるようにしてもよい。ラインメモリが用いられる場合には、隣り合う走査ラインにおける同一位置の画素（例えば上下に隣り合う画素）についての画像データ信号が同じ場合に、データ信号１０３ａのレベル遷移が抑制され、以前の走査ライン上の画素について保持されている画像データ信号を用いて表示が行われる。 << Embodiment 4 >>
For example, as shown in FIGS. 8 and 9, as the shift register 113 of the output control unit 111 and the shift register 123 of the input control unit 121, image data signals for one or more scanning lines or one or more screens are input. A line memory or a frame memory may be used. When a line memory is used, the level transition of the data signal 103a is suppressed when the image data signals for the pixels at the same position (for example, vertically adjacent pixels) in the adjacent scan lines are the same, and the previous scan line Display is performed using the image data signal held for the upper pixel.
　また、フレームメモリが用いられる場合に、相前後するフレームの同一位置の画素についての画像データ信号が同じ場合には、データ信号１０３ａのレベル遷移が抑制され、以前のフレームの画素について保持されている画像データ信号を用いて表示が行われる。この場合には、例えば静止画が表示される場合にデータ信号１０３ａのレベル遷移が全く生じないようにすることができる。 When the frame memory is used and the image data signal is the same for pixels at the same position in successive frames, the level transition of the data signal 103a is suppressed and held for the pixels of the previous frame. Display is performed using the image data signal. In this case, for example, when a still image is displayed, the level transition of the data signal 103a can be prevented from occurring at all.
　《実施形態５》
　上記実施形態１～４で説明したような出力制御部１１１、および入力制御部１２１は、画像データ信号処理部１０２とドライバ１０４との間の画像データ信号の伝送に用いられるのに限らず、例えば図１０に示すように画像データ信号生成部１０１とシフトレジスタ１１２との間の画像データ信号の伝送に用いられるようにしたりしてもよい。また、例えば画像データ信号処理部１０２の内部における種々の処理部間等、具体的には図１１に示すように、オーバードライブ処理部１４１と、その処理のための画像データ信号を保持するフレームメモリ１４２との間などでの１方向、または双方向の画像データ信号の伝送に用いられるようにしてもよい。ここで、特に限定されないが、例えば伝送路が長い場合やシールド効果を得にくい箇所に適用される場合には、特にＥＭＩ低減効果などが得られやすい。 << Embodiment 5 >>
The output control unit 111 and the input control unit 121 as described in the first to fourth embodiments are not limited to being used for transmission of an image data signal between the image data signal processing unit 102 and the driver 104. For example, As shown in FIG. 10, it may be used for transmission of an image data signal between the image data signal generation unit 101 and the shift register 112. Further, for example, between various processing units in the image data signal processing unit 102, specifically as shown in FIG. 11, an overdrive processing unit 141 and a frame memory for holding an image data signal for the processing 142 may be used for transmission of one-way or two-way image data signals to / from 142. Here, although not particularly limited, for example, when the transmission path is long or when it is applied to a place where it is difficult to obtain a shielding effect, an EMI reduction effect or the like is particularly easily obtained.
　《その他の変形例》
　上記各実施形態や変形例で説明した構成要素は、論理的に矛盾しない範囲で種々組み合わせてもよい。具体的には、例えば実施形態２で説明したようなカラー表示のための画像データ信号の伝送をするために実施形態３～５で説明したような構成を適用してもよい。また、実施形態１、４で説明したような構成を組み合わせて、上下左右に隣り合う画素間、または相前後するフレーム間の何れかで画像データ信号が一致する場合に、既に保持された画像データ信号が用いられるようにして、伝送される画像データ信号の遷移が一層抑制されるようにしてもよい。 << Other modifications >>
The constituent elements described in the above embodiments and modifications may be variously combined within a logically consistent range. Specifically, for example, the configuration described in the third to fifth embodiments may be applied to transmit an image data signal for color display as described in the second embodiment. In addition, by combining the configurations described in the first and fourth embodiments, when the image data signal matches between pixels adjacent vertically and horizontally, or between adjacent frames, image data that has already been held The signal may be used so that the transition of the transmitted image data signal is further suppressed.
　また、上記の例では液晶テレビである画像表示装置に適用される例について説明したが、これに限らず、例えば外部のチューナやパーソナルコンピュータなどから画像データ信号が入力される画像表示装置に適用されるようにしてもよい。また、液晶表示パネル１０５が用いられるのに限らず、例えば有機ＥＬ（electroluminescent）表示パネルが用いられるなどしてもよい。 Further, in the above example, the example applied to the image display device which is a liquid crystal television has been described. However, the present invention is not limited to this. For example, the present invention is applied to an image display device to which an image data signal is input from an external tuner or personal computer. You may make it do. Further, the liquid crystal display panel 105 is not limited to being used. For example, an organic EL (electroluminescent) display panel may be used.
　また、出力制御部１１１や入力制御部１２１の具体的な形態としては、単独の半導体チップとして構成されたり、画像データ信号処理部１０２やドライバ１０４、またはその一部の機能を有する回路チップに組み込まれるなどしてもよい。 Further, as a specific form of the output control unit 111 and the input control unit 121, the output control unit 111 and the input control unit 121 are configured as a single semiconductor chip, or incorporated in the image data signal processing unit 102, the driver 104, or a circuit chip having a part of the function. It may be done.
　また、上記の例では各画素の画像信号データがシリアルに伝送される例を示したが、必ずしもこれに限定されず、複数ビットのデータ信号がパラレルに伝送される場合でも、レベル遷移が生じる信号の伝送であれば、同様の手法を適用することができる。 In the above example, the image signal data of each pixel is serially transmitted. However, the present invention is not necessarily limited to this, and a signal that causes a level transition even when a multi-bit data signal is transmitted in parallel. The same method can be applied if the transmission is as follows.
　以上説明したように、本発明は、液晶表示装置等の画像表示装置、ならびに画像表示のための画像データ信号を伝送する画像データ信号出力装置、および画像データ信号入力装置等について有用である。 As described above, the present invention is useful for an image display device such as a liquid crystal display device, an image data signal output device for transmitting an image data signal for image display, and an image data signal input device.
　　　　１０１　　　画像データ信号生成部
　　　　１０２　　　画像データ信号処理部
　　　　１０３　　　フレキシブル基板
　　　　１０３ａ　　データ信号
　　　　１０３ｂ　　制御信号
　　　　１０４　　　ドライバ
　　　　１０５　　　液晶表示パネル
　　　　１１１　　　出力制御部
　　　　１１２　　　シフトレジスタ
　　　　１１３　　　シフトレジスタ
　　　　１１４　　　コンパレータ
　　　　１１５　　　フリップフロップ
　　　　１１６　　　スイッチ
　　　　１１７　　　ＡＮＤ回路
　　　　１１８　　　ＡＮＤ回路
　　　　１２１　　　入力制御部
　　　　１２２　　　シリアル－パラレル変換部
　　　　１２３　　　シフトレジスタ
　　　　１２４　　　スイッチ
　　　　１３１　　　シフトレジスタ
　　　　１３２　　　サンプリングメモリ
　　　　１３３　　　ホールドメモリ
　　　　１３４　　　レベルシフタ
　　　　１３５　　　Ｄ／Ａコンバータ
　　　　１３６　　　出力回路
　　　　１４１　　　オーバードライブ処理部
　　　　１４２　　　フレームメモリ DESCRIPTION OF SYMBOLS 101 Image data signal generation part 102 Image data signal processing part 103 Flexible board 103a Data signal 103b Control signal 104 Driver 105 Liquid crystal display panel 111 Output control part 112 Shift register 113 Shift register 114 Comparator 115 Flip-flop 116 Switch 117 AND circuit 118 AND circuit 121 Input Control Unit 122 Serial-Parallel Conversion Unit 123 Shift Register 124 Switch 131 Shift Register 132 Sampling Memory 133 Hold Memory 134 Level Shifter 135 D / A Converter 136 Output Circuit 141 Overdrive Processing Unit 142 Frame Memory

Claims (15)

  1. 　画像データ信号を伝送するために出力する画像データ信号出力装置であって、
    　画像データ信号のレベルの遷移パターンの繰り返しを検出し、検出結果に応じた制御信号を出力する繰り返し検出部と、
    　上記検出結果に応じて、画像データ信号の出力を抑制する出力抑制部と、
    　を備えたことを特徴とする画像データ信号出力装置。     An image data signal output device for outputting an image data signal for transmission,
    A repetitive detection unit that detects repetitive transition patterns of the level of the image data signal and outputs a control signal according to the detection result;
    According to the detection result, an output suppression unit that suppresses the output of the image data signal,
    An image data signal output device comprising:
  2. 　請求項１の画像データ信号出力装置であって、
    　上記検出部は、
    　以前に入力された画像データ信号を保持する保持部と、
    　新たに入力された画像データ信号と、上記保持部に保持された画像データ信号とを比較する比較部と、
    　を備えたことを特徴とする画像データ信号出力装置。     The image data signal output device according to claim 1,
    The detection unit is
    A holding unit for holding a previously input image data signal;
    A comparison unit that compares the newly input image data signal with the image data signal held in the holding unit;
    An image data signal output device comprising:
  3. 　請求項２の画像データ信号出力装置であって、
    　上記比較部は、上記保持部に保持された画像データ信号よりも少ないビット数について、上記新たに入力された画像データ信号との比較を行うように構成されていることを特徴とする画像データ信号出力装置。     The image data signal output device according to claim 2,
    The comparison unit is configured to perform comparison with the newly input image data signal for a smaller number of bits than the image data signal held in the holding unit. Output device.
  4. 　請求項２および請求項３のうち何れか１項の画像データ信号出力装置であって、
    　上記保持部は、１走査ライン以上、または１画面以上の画素についての画像データ信号を保持し、
    　上記比較部は、先行する走査ラインまたは画面における、新たに画像データ信号が入力された画素に対応する位置の画素の画像データ信号と、上記新たに入力された画像データ信号とを比較するように構成されていることを特徴とする画像データ信号出力装置。     An image data signal output device according to any one of claims 2 and 3,
    The holding unit holds an image data signal for pixels of one scanning line or more, or one screen or more,
    The comparison unit compares an image data signal of a pixel at a position corresponding to a pixel to which a new image data signal is input on the preceding scanning line or screen with the newly input image data signal. An image data signal output device characterized by being configured.
  5. 　請求項１から請求項４のうち何れか１項の画像データ信号出力装置であって、
    　上記出力抑制部は、画像データ信号のレベルの遷移パターンの繰り返しが検出された場合に、出力される画像データ信号のレベルを、その時点のレベル、およびあらかじめ定められたレベルのうち何れか一方に固定するように構成されていることを特徴とする画像データ信号出力装置。     An image data signal output device according to any one of claims 1 to 4,
    The output suppression unit may change the level of the output image data signal to one of a current level and a predetermined level when a repetition of the transition pattern of the level of the image data signal is detected. An image data signal output device configured to be fixed.
  6. 　請求項１から請求項５のうち何れか１項の画像データ信号出力装置であって、
    　上記検出部は、あらかじめ定められたビット数の画像データ信号について、上記レベルの遷移パターンの繰り返しの検出をするように構成されていることを特徴とする画像データ信号出力装置。     An image data signal output device according to any one of claims 1 to 5,
    The image data signal output device, wherein the detection unit is configured to detect the repetition of the transition pattern of the level for an image data signal having a predetermined number of bits.
  7. 　請求項６の画像データ信号出力装置であって、
    　上記検出部は、画素単位の画像データ信号について、上記レベルの遷移パターンの繰り返しの検出をするように構成されていることを特徴とする画像データ信号出力装置。     The image data signal output device according to claim 6,
    The image data signal output device, wherein the detection unit is configured to detect the repetition of the transition pattern of the level with respect to an image data signal in pixel units.
  8. 　請求項１から請求項７のうち何れか１項の画像データ信号出力装置であって、
    　上記検出部は、複数系統の画像データ信号のレベルの遷移パターンが何れも繰り返されていることを検出するように構成されていることを特徴とする画像データ信号出力装置。     The image data signal output device according to any one of claims 1 to 7,
    The image data signal output device, wherein the detection unit is configured to detect that the level transition patterns of the image data signals of a plurality of systems are all repeated.
  9. 　請求項８の画像データ信号出力装置であって、
    　上記複数系統の画像データ信号は、赤、緑、および青の画素についての画像データ信号であることを特徴とする画像データ信号出力装置。     The image data signal output device according to claim 8,
    The image data signal output apparatus, wherein the plurality of image data signals are image data signals for red, green, and blue pixels.
  10. 　請求項１から請求項９のうち何れか１項の画像データ信号出力装置から伝送された画像データ信号が入力される画像データ信号入力装置であって、
    　以前に入力された画像データ信号を保持する保持部と、
    　上記制御信号に基づいて、上記保持部に保持された画像データ信号、または新たに入力された画像データ信号を選択する選択部と、
    　を備えたことを特徴とする画像データ信号入力装置。     An image data signal input device to which an image data signal transmitted from the image data signal output device according to any one of claims 1 to 9 is input,
    A holding unit for holding a previously input image data signal;
    A selection unit that selects an image data signal held in the holding unit or a newly input image data signal based on the control signal;
    An image data signal input device comprising:
  11. 　請求項１０の画像データ信号入力装置であって、
    　上記保持部は、直列的に入力されて保持した一連の画像データ信号を並列的に出力する直列並列変換部として用いられるように構成されていることを特徴とする画像データ信号入力装置。     The image data signal input device according to claim 10,
    The image data signal input device, wherein the holding unit is configured to be used as a serial-to-parallel conversion unit that outputs a series of image data signals input and held in series in parallel.
  12. 　請求項１から請求項９のうち何れか１項の画像データ信号出力装置と、
    　請求項１０および請求項１１のうち何れか１項の画像データ信号入力装置と、
    　を備えたことを特徴とする画像表示装置。     An image data signal output device according to any one of claims 1 to 9,
    An image data signal input device according to any one of claims 10 and 11,
    An image display device comprising:
  13. 　請求項１２の画像表示装置であって、さらに、
    　画像データ信号の処理を行う画像データ信号処理部と、
    　画像の表示を行う画像表示部と、
    　を備え、
    　上記画像データ信号処理部に、上記画像データ信号出力装置が設けられ、
    　上記画像表示部に、上記画像データ信号入力装置が設けられていることを特徴とする画像表示装置。     The image display device according to claim 12, further comprising:
    An image data signal processor for processing the image data signal;
    An image display unit for displaying an image;
    With
    The image data signal processing unit is provided with the image data signal output device,
    An image display device, wherein the image data signal input device is provided in the image display unit.
  14. 　請求項１２および請求項１３のうち何れか１項の画像表示装置であって、さらに、
    　画像データ信号を生成する画像データ信号生成部を備え、
    　上記画像データ信号生成部に、上記画像データ信号出力装置が設けられていることを特徴とする画像表示装置。     The image display device according to any one of claims 12 and 13, further comprising:
    An image data signal generator for generating an image data signal;
    An image display device, wherein the image data signal generator is provided with the image data signal output device.
  15. 　請求項１２から請求項１４のうち何れか１項の画像表示装置であって、さらに、
    　画像データ信号に対してオーバードライブ処理を行うオーバードライブ処理部と、
    　上記オーバードライブ処理のための画像データ信号を保持するフレームメモリと、
    　を備え、
    　上記オーバードライブ処理部に、上記画像データ信号出力装置、および上記画像データ信号入力装置のうち少なくとも一方が設けられ、
    　上記フレームメモリに、上記オーバードライブ処理部に対応する上記画像データ信号出力装置、および上記画像データ信号入力装置のうち少なくとも一方が設けられていることを特徴とする画像表示装置。     The image display device according to any one of claims 12 to 14, further comprising:
    An overdrive processing unit that performs overdrive processing on the image data signal;
    A frame memory for holding an image data signal for the overdrive process;
    With
    At least one of the image data signal output device and the image data signal input device is provided in the overdrive processing unit,
    An image display device, wherein the frame memory is provided with at least one of the image data signal output device corresponding to the overdrive processing unit and the image data signal input device.
PCT/JP2012/006157 2011-10-03 2012-09-26 Image data signal output device, image data signal input device, and image display device WO2013051223A1 (en)

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