JP3139001B2 - Image recording device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus for recording a multi-tone image, and more particularly, to an image recording apparatus which records an image density signal corresponding to multi-tone input image data for each pixel. The present invention relates to an improvement in an image recording apparatus that performs beam scanning on a photosensitive member by turning on or off a beam of a beam scanning unit based on the beam scanning unit, and develops a latent image formed on the photosensitive member into a visible image.

2. Description of the Related Art Conventionally, as an image recording apparatus of this type, for example,
There is one published in Japanese Patent No. 101175.

This is an example of a laser beam printer. As shown in FIG. 42, multi-gradation input image data DT (for example, 8-bit data) is converted into an analog signal by a DA converter 300 and then one input terminal of a comparator 301. In addition, a threshold signal TS (for example, a triangular wave) from the signal generator 302 is input to the other input terminal of the comparator 301,
As shown in FIGS. 43 (a) and 43 (b), the comparator 30
After generating a pulse-shaped image density signal SD based on a threshold signal TS range equal to or greater than the number of density gradations of the input image data DT in 1, a laser driver 303 is generated based on the image density signal SD.
To turn on or off the laser 304, beam-scan a photosensitive member (not shown) according to the number of density gradations of the input image data DT, and develop a latent image formed on the photosensitive member into developing means ( (Not shown).

[Problems to be Solved by the Invention] However, in such a conventional image recording apparatus, a high-speed DA converter for converting multi-gradation input image data is used.
300, the high-speed comparator 301, and the signal generator 302 must be used, which complicates the device configuration and raises the cost of the device.

Further, in the above image recording apparatus, the input image data
The image density signal SD having a pulse width that completely matches the number of density gradations of the DT is generated, but even if the pulse width modulation of the image density signal SD is performed finely,
In view of the development accuracy in consideration of the toner particle diameter of the developing means, it is inherently difficult to reproduce the recorded image density finely according to the density gradation number of the input image data DT. After analog conversion
When the comparison is made in 301, the nozzle component is likely to enter into that much, and there arises a problem that the accuracy of the pulse width modulation itself of the image density signal SD is not so high.

As a prior art which solves such a problem, for example, one disclosed in Japanese Patent Application Laid-Open No. 63-74386 is already known.

This is because, as shown in FIG. 44, the density information of the input image data is made to correspond to the number M of the sub-pixels PS associated with the pixel P division by dividing the density gradation number of the input image data substantially equally. The pulse width of the image density signal SD is changed from SD (0) to SD based on the number M of sub-pixels (for example, M = 0 to 3).
By performing modulation as shown in (3), the laser beam is turned on or off to form a latent image corresponding to the density information of the input image data DT.

According to this type, it is not necessary to use the DA converter 300, the high-speed comparator 301 and the signal generator 302 required in the prior art shown in FIG. Reproduction can be performed.

However, in such an image recording apparatus, the pulse width of the image density signal SD is uniformly modulated with the increase in the number M of sub-pixels. A latent image scanned by a laser beam was developed based on the SD and the density of the recorded image was measured. As a result, a non-linear development density characteristic was obtained as shown in FIG. In this case, on the side where the number M of sub-pixels is large, in other words, on the side where the pulse width of the image density signal SD is large, the recording image density is saturated, and the pulse width modulation of the image density signal SD according to the number of sub-pixels is performed. Even if such an operation is performed, a change in the density of the recorded image cannot be obtained, causing a problem that the gradation reproducibility of the recorded image is poor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has been made in consideration of development density characteristics when scanning a photosensitive member with a beam scanning unit while simplifying the configuration of the apparatus and reducing the cost. And to provide an image recording apparatus capable of maintaining good tone reproduction.

[Means for Solving the Problems] That is, as shown in FIG. 1, the present invention provides a beam scanning unit based on a pulsed image density signal SD corresponding to multi-gradation input image data DT for each pixel. After the beam scanning of the photosensitive member 2 is performed by turning on or off the beam 1, the latent image formed on the photosensitive member 2 is
In the image recording apparatus developed in step (1), the density information N of the input image data DT of each pixel (for example, 0 to 255) is divided by a predetermined threshold value so that the density information of the input image data DT is Image density code S corresponding to the number of pixels
A density code generating means 4 for generating C, and after the image density code SC is generated by the density code generating means 4, the density gradation number N of the input image data DT and the recorded image density which has been visualized In order to correct the nonlinear development characteristic curve indicating the relationship to a linear one, the image density code S
And a multi-level modulation means for modulating the pulse width of the image density signal based on C.

In such technical means, the beam scanning unit 1 can be appropriately selected as long as it can scan a photosensitive member with a beam, such as a laser scanning unit. The beam scanning unit 1 is operated based on the image density signal SD. Whether the beam is turned on or off with a pulse width corresponding to the image density signal SD is determined based on the relationship with the developing method. It is necessary to form a latent image so as to obtain a recorded image density corresponding to the image density signal SD.

Further, the photosensitive member 2 can be appropriately selected irrespective of a drum shape or a belt shape. On the other hand, as for the developing means 3, if the latent image on the photosensitive member 2 can be visualized,
A developer, a developing method, and the like can be appropriately selected.

Further, if the density code generating means 4 includes at least a code setting means for dividing the number N of density gradations of the multi-gradation input image data DT by a predetermined threshold value to obtain an image density code SC, The design of the number of generated codes, the generation method, and the like can be appropriately changed.

In this case, as one means for maintaining good setting accuracy of the image density code SC, a data correction means for correcting the number of density gradations of the pixel of interest by an appropriate algorithm may be provided. The correction algorithm can be appropriately selected, and an error diffusion method can be given as an example. As the error diffusion method, at least the pixel of interest and the previous line corresponding to the pixels located before and after the pixel of interest can be used. It is preferable that the difference data between the pixel data and the threshold be added to the current data of the target pixel with a predetermined weight,
In addition to the above-described correction algorithm, it is particularly preferable that the difference data between the image data of the pixel immediately before the target pixel and the threshold is added to the current data of the target pixel with relatively large weight.

Further, as means for suppressing the generation of the unique pattern (texture) by the error diffusion method, design is made such that the threshold value of the code setting means can be variably set to two systems. That is, by alternately generating two types of thresholds, a line screen pattern having half the number of lines of the sampling frequency is superimposed on the texture, thereby forcing an error arrangement of dots in a certain direction. This makes the texture less visible.

Further, as the multi-level modulation means 5, if the pulse width of the image density signal SD based on the image density code SC can be variably set within a desired range, for example, the image density signal S
By generating the minimum unit of reference pulse required for setting the pulse width of D and multiplying this reference pulse by an integer,
The pulse width of the image density signal SD is set to a desired value, or the phase shift of the pulse signal based on the reference clock is used, and the pulse width of the image density signal SD is set corresponding to the phase shift of the pulse signal. The design can be changed as appropriate.

In this case, in the former method, the reference pulse is appropriately set based on the variation of the pulse width of the image density signal SD. However, if the frequency of the reference pulse is not set extremely high, , Multi-level modulation means 5
Inexpensive TTL without using expensive ECL as circuit configuration
This is particularly preferred in that it can be used for

In the latter case, for example, a delay unit can be used as a unit for extracting the phase shift of the pulse signal, and the delay unit can be designed to extract the amount of delay by a desired calculation unit. In this type, if the delay amount of the delay means is appropriately selected, the pulse width of the image density signal SD can be set to a desired value, so that the pulse width can be easily set without being restricted by the former method. The circuit can be configured at a relatively low cost.

Although any means can be selected as the delay means, from the viewpoint of simplification of the configuration, it is preferable to use a delay line provided with a plurality of output tappers having different delay amounts. Further, when the delay amount using the delay unit is used as the pulse width of the image density signal SD, from the viewpoint of simplifying the configuration of the arithmetic unit, the reference clock is reduced by half as a pulse signal based on the reference clock. It is preferable to use a frequency-divided value. Further, when a delay line is used as the delay unit, it is preferable to use a temperature correction unit that suppresses a change in the delay pulse width due to a temperature change of the delay line. Further, in order to set the pulse width of the image density signal SD with high accuracy, it is preferable to take out the output signal from the delay means through the waveform shaping means, and a CMOS gate is particularly preferable as the waveform shaping means.

Further, if the pulse width modulation pattern of the image density signal SD is changed according to the reproduction image mode (character mode, photograph mode), it is possible to perform optimal image reproduction according to each reproduction image mode.

More specifically, for example, when the pulse width modulation pattern of one pixel is formed into a sawtooth waveform that is sequentially repeated in ascending order of the threshold value of the density code generation unit 4, in other words, when the pulse width is sequentially expanded from one direction. Since one line is formed by one pixel, the resolution is high and the reproducibility of a fine line such as a character can be improved. In addition, the pulse width modulation pattern of one pixel is generated in the order of the threshold value of the density code generation unit 4 in the order of lower threshold,
In the case of a triangular wave shape that repeats alternately in the descending order, in other words, when adjacent pulse widths are expanded alternately from the left and right, two pixels form a line, so the resolution is higher than in the case of a sawtooth wave. On the other hand, the gradation expression is improved, but the reproducibility of a halftone image such as a photograph can be improved.

Further, this technical means includes, as an image recording apparatus, a plurality of developing means 3 using different developers, and develops a latent image individually formed by each developing means 3. You may. In this case, the multi-level modulation means 5 may modulate the pulse width of the image density signal SD by averaging the development characteristic curves of the respective development means 3, but the modulation accuracy is improved. From a viewpoint, it is preferable to provide a plurality of multi-level modulation means 5 corresponding to each development characteristic curve, and to set the modulation degree of each multi-level modulation means 5 based on each development characteristic curve. .

[Operation] According to the technical means as described above, as shown in FIG. 1, when the multi-tone input image data DT of each pixel is input to the density code generation means 4, the density code generation means 4 As shown in FIGS. 2 (a) and 2 (b), the density gradation number N of the multi-input image data DT is substantially equally divided by a predetermined threshold value, and the number M of sub-pixels Ps associated with the pixel P division (M ( For example, image density codes SC (specifically, SC (0) to SC (
(4)) is output.

Thereafter, as shown in FIG.
When C is input to the multi-level modulation unit 5, the multi-level modulation unit 5 outputs an image density signal SD corresponding to the image density code SC, and drives the beam scanning unit 1 based on the image density signal SD.

At this time, the pulse width of the image density signal SD (specifically, SD (0) to SD (4)) corresponding to the image density code SC is input as shown in FIGS. 3 (a) and 3 (b). In order to correct the non-linear development characteristic curve Y indicating the relationship between the image data DT and the visualized recorded image density to a linear one indicated by a virtual line, the image density code SC is unequally divided. Modulated.

Hereinafter, the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

Embodiment 1 In this embodiment, 256 density gradations (including a zero density level)
The present invention is applied to a laser printer which reproduces the input image data as a recorded image of four gradations (including a zero density level).

FIG. 4 shows a laser scanning unit (hereinafter abbreviated as ROS (Raster Output Scanner)) used in this embodiment.

In the figure, reference numeral 10 denotes a semiconductor laser, 11 denotes a polygon mirror that guides the beam Bm over a predetermined scanning range l by reflecting a beam Bm from the semiconductor laser 10 on a reflecting surface 11a during a rotating operation, and 12 denotes a polygon mirror. A polygon motor 13 for rotating the polygon mirror 11, a fθ lens 13 for correcting the beam Bm from the polygon mirror 11 to guide the beam Bm onto the photoreceptor 14 at uniform pixel intervals, and a reference numeral 15 for the beam Bm incident on the photoreceptor 14. A position detection sensor (hereinafter, referred to as an SOS sensor [Start of Scan Sensor]) 16 for detecting a scanning start point is interposed in a beam path corresponding to the scanning start point of the photoconductor 14 so that the SOS
The mirror guides the beam Bm to the sensor 15. A developing unit (not shown) is provided around the photoreceptor 14, and in this embodiment, the developing unit performs reversal development using an exposed portion on the photoreceptor 14 as an image portion. I have.

FIG. 5 shows the basic configuration of a laser printer equipped with such a ROS.

In the figure, reference numeral 20 denotes an image processing unit that appropriately processes and outputs multi-tone image data DT having, for example, 256 levels of density gradations. The image data DT from this image processing unit 20 is an image processing unit. The data is taken in the screen generator 30 in synchronization with a predetermined clock signal CKG on the 20 side. Then, the screen generator 30 generates an image density code SC corresponding to the density gradation number of the image data DT so as to reduce the density gradation number of the image data DT to a range suitable for ROS control, and generates a predetermined clock. Output in synchronization with the signal CKG. Further, the image density code SC from the screen generator 30 synchronizes with a predetermined clock signal CKG for one line of image data DT.
Are stored in a first-in-first-out memory (hereinafter referred to as FIFO) 40 and transmitted to the ROS control 50 in synchronization with a clock signal CKR which is a read timing signal from the ROS controller 40. It has become.

In this embodiment, the ROS controller 50 includes a synchronization signal generation circuit 51 for generating a predetermined clock signal CKR.
And a polygon motor controller 54 for controlling the polygon motor 12, and a clock signal CK from the synchronization signal generation circuit 51.
An image density code SC is taken in from the FIFO 40 in synchronization with R, and a multi-level modulation circuit 56 for modulating the pulse width of the image density signal SD in accordance with the image density code SC.

The synchronizing signal generating circuit 51 generates a predetermined clock signal CKR based on a video clock signal (hereinafter abbreviated as a V clock signal) from the video clock generator 52, and the video clock generator 52 , SOS
The detection signal of the sensor 15 is operated by a signal amplified by the sensor amplifier 53. Further, the polygon motor controller 54 controls the motor control clock signal SM
Is sent to the motor driver 55 to drive and control the polygon motor 12. Further, the multi-level modulation circuit 56 controls the drive of the laser 10 by transmitting the image density signal SD to the laser driver 57.

FIG. 6 shows details of the screen generator 30 used in this embodiment.

In the figure, reference numeral 31 denotes a buffer for temporarily storing 8-bit input image data DT and then outputting the same. The image data DT from this buffer 31 is input to one input terminal A of three digital comparators 32 to 34. Along with
The threshold values TH1, TH2, and TH3 set by the threshold setting switches 35 to 37 are input to the other input terminals B of the comparators 32 to 34. When A ≧ B, the outputs of the comparators 32 to 34 are set to “1”. "It is supposed to be. In this embodiment, the threshold values TH1, TH2, TH3 are:
The number of density gradations of the image data DT is divided into three,
For example, TH1 = 43, TH2 = 128, and TH3 = 203 are set.

Then, the 3-bit output SA (specifically, SA (0), SA (1), SA (2)) from each of the comparators 32 to 34 is input to the image density code generation circuit 38, and the 2-bit image density is generated. Code SC (specifically, SC (0) = 00, SC (1) = 1
0, SC (2) = 11, SC (3) = 01).
The relationship between the image density code SC and the number of density gradations of the input image data DT is as shown in Table 1 below.

FIG. 7 shows a synchronizing signal generation circuit 51, a video clock generation circuit 52, and a multi-level modulation circuit 56 used in this embodiment.
The details are shown below.

In the figure, reference numerals 60 and 61 constitute a video clock generating circuit 52, 60 is an oscillator for oscillating a high frequency clock signal, 61 is cleared by a detection signal SSOS from the SOS sensor 15, and the oscillator 60 Is a 1 / n divider that divides the clock signal from 1 / n (n = 6 in this embodiment), and the output from the divider 61 is the V clock signal VCK
Is generated as

Numerals 62 to 65 constitute a multi-level modulation circuit 56, 62 is an interface for taking in the image density code SC, 63 is a latch circuit for temporarily holding the image density code SC, and 64 is the latch circuit 63 image density codes SC
As an address signal, a P-ROM decoder converting and outputting 6-bit modulated pulse signals C1 to C6 corresponding to the image density signal SC, and 65 stores the modulated pulse signals C1 to C6 from the decoder 65. This is an n-bit shift register.

Then, the synchronization signal generation circuit 51 supplies the latch circuit 63 with the V clock signal VCK as a synchronization signal, and on the other hand, as the shift clock signal SCK of the shift register 65,
From the oscillator 60 and a V clock signal VCK
, A data load timing signal is generated and supplied to the shift register 65.

Accordingly, in this embodiment, as shown in FIG. 8, when the 3-bit image density code SC of an arbitrary pixel Pi is output from the latch circuit 63 in synchronization with the V clock signal VCK, the decoder 64 The modulated pulse signals C1 to C6 are output from the output ports a1 to a6 using the image density code SC as an address signal, and the shift register 65 loads the modulated pulse signals C1 to C6 based on the load signal. In this state, the shift register 65 sequentially outputs the modulated pulse signals C1 to C6 as the image density signal SD of one pixel in synchronization with the shift clock signal SCK.

In this embodiment, the contents of the decoder 64 are as shown in Table 2 below.

The reason for setting the contents of the decoder 64 in this manner is as follows.

In general, the relationship between the density gradation number N of the input image data DT and the recorded image density J is based on the characteristics of the photosensitive member 14 and the developing means (not shown), as shown by a solid line in FIG. Obtained as Y. In the development characteristic curve Y, the black circles indicate the recorded image density in the input image data (N / 6) × i (i = 1 to 6), and the upper and lower sections sandwiching the black circle indicate the amount of variation in the recorded image density.

For this reason, if the pulse width of the image density signal SD is evenly modulated according to the image density code SS, each of the image density codes SC (specifically, SC (0) to SC (
As shown in FIG. 9, the recorded image densities J corresponding to (3)) become J0 = 0, J1 = 0.65, J2 = 1.0, and J3 = 1.05, respectively.

At this time, although the density difference between the recorded image densities J0 and J1 is very large, the density difference between the recorded image densities J2 and J3 is very small, and the tone reproducibility of the recorded image may deteriorate. Understood.

Under such circumstances, as shown by a virtual line in FIG. 9, if the relationship between the image density code SC and the recorded image density is corrected to a linear development characteristic curve Y ', the image density code SC is corrected. It is possible to set the density difference of the print image density J with respect to (0) to SC (3) at substantially equal intervals, and it is considered that the tone reproducibility of the print image can be improved accordingly. .

From this viewpoint, the recorded image density corresponding to the image density codes SC (1) and SC (2) on the corrected development characteristic curve Y 'is examined.
It is understood that they correspond to the above Y1 and Y2. Therefore, when modulating the pulse width of the image density signal SD corresponding to the image density codes SC (1) and SC (2), the recording image density corresponding to Y1 and Y2 of the development characteristic curve Y can be obtained. do it.

In this case, according to the development characteristic curve Y, the recorded image density Y1 substantially corresponds to the density at a position near the density gradation number N / 6 of the input image data, and the recorded image density Y2 is the input image density. The density substantially corresponds to the density in the vicinity of the density density number 2N / 6 of the data. Therefore, each image density code SC
On the other hand, if the pulse width of the image density signal SD is modulated so that the number of density gradations 0, N / 6, 2N / 6, N of the input image data can be reproduced, the recording image density can be made substantially uniform. It becomes possible to reproduce.

Based on such a viewpoint, 6-bit modulation pulse codes C1 to C6 corresponding to the density gradation numbers 0, N / 6, 2N / 6, N of the input image data are set in advance, and the modulation pulse The contents of the decoder 64 are set by associating the codes C1 to C6 with the respective image density codes SC.

Next, the operation of the laser printer according to this embodiment will be described.

In FIG. 5, when multi-gradation input image data DT is input to the screen generator 30, the input image data
An image density code SC corresponding to the number of density gradations of DT is output. The image density code SC is set in accordance with the number of sub-pixels PS when one pixel P is divided into three as shown in FIG.

Thereafter, the image density code SC is taken into the multi-level modulation circuit 56 via the FIFO 40, and is converted into modulation pulse signals C1 to C6 by the decoder 64 of the multi-level modulation circuit 56. The modulated pulse signals C1 to C6 are
After being stored in the memory 65, it is output as a serial image density signal SD.

At this time, as shown in Table 2 and FIG. 10, when the image density code SC is SC (0), the modulation pulse codes C1 to C6 are all "0" and the image density signal SD
(0) is a low level signal, and when the image density code SC is SC (1), only the modulation pulse code C1 is "1" and the image density signal SD (1) is changed to C1. The pulse signal becomes a high level only in the corresponding range, and when the image density code SC is SC (2), only the modulation pulse codes C1 and C2 are "1" and the image density signal SD ( 2) is a pulse signal which becomes a high level only in the range corresponding to C1 and C2, and furthermore, when the image density code SC is SC (3), the modulation pulse codes C1 to C
6 are all "1", and the image density signal SD (3) becomes a pulse signal which becomes a high level in a range corresponding to C1 to C6.

The image density signal SD output in this way is sent to the laser driver 57 to control the drive of the laser 10, as shown in FIG.

Now, as shown in FIG. 11, assuming that the image density signals SD at the pixels Pi to Pi + 3 are SD (0) to SD (3), respectively, the laser 10 lights up based on the image density signal SD. This laser beam is applied to the photoconductor 14 charged in advance.

At this time, on the photoconductor 14, each pixel Pi or Pi +
The charge is removed in a range corresponding to the pulse width of the image density signal SD for every three, and the charge removing section forms a latent image Z (specifically, Zi + 1, Zi + 2, Zi + 3) as an image section. Thereafter, when the latent image Z portion passes through the developing device, the latent image Z portion is developed, and the toner images T (specifically, Ti + 1, Ti + 1
+ 2, Ti + 3) is formed.

Then, the toner image T is transferred to a recording sheet (not shown) by a transfer unit (not shown), and the toner image T is completely fixed on the recording sheet through a predetermined fixing process.

In the course of such an image recording operation, the relationship between the image density signals SD (0) to SD (3) and the recorded image density was examined, and as shown by the phantom line in FIG. However, it was confirmed that the development density characteristics were substantially linear.

Embodiment 2 In this embodiment, 256 density gradations (including a zero density level)
The present invention is applied to a laser printer that reproduces the input image data as a recorded image of five gradations (including the density example level). It was made.

The laser printer according to this embodiment has the basic configuration shown in FIG.
The multi-level modulation circuit 56 of the ROS controller 50 is different from that of the first embodiment. Incidentally, also in this embodiment, the area exposed by the laser beam is reversely developed as an image area.

FIG. 13 shows details of the screen generator according to this embodiment.

In the figure, reference numeral 70 denotes 8-bit input image data DT
Is temporarily stored and output.The image data DT from the buffer 70 is input to one input terminal A of the four digital comparators 71 to 74 via an error diffusion circuit 80 unique to this embodiment. The other input terminal B of the comparators 71 to 74 is connected to a threshold pattern setting circuit 85 (to be described later).
A threshold value TH (specifically, TH1, TH2, TH3, TH4) set by threshold setting switches 92 to 95, which are components of FIG. 16 and FIG. 17, is input. The outputs of the comparators 71 to 74 are set to "1". In this embodiment, the threshold values TH1, TH2, TH
3, TH4 is for dividing the number of density gradations of the image data DT into four, for example, TH1 = 32, TH2 = 96, TH3 = 160, TH4 = 224.
Is set as follows.

The comparators 71 to 74 output 4-bit address data ADT (specifically, [0000] and [000].
1], [0011], [0111], and [1111]), and the 4-bit address data ADT is converted by the coder 75 into a 3-bit image density code SC ( Specifically, SC (0) = 000, SC (1) = 001, SC
(2) = 011, SC (3) = 101, SC (4) = 111).

It should be noted that the density gradation number of the input image data, the address data AD
The relationship between T and the image density code SC is as shown in Table 3 below.

Further, the error diffusion circuit 80 used in this embodiment is designed to suppress the influence of difference data (error data) between the image data DT and the threshold TH generated when the image data DT is divided by the predetermined threshold TH. Image data DT
Is to be corrected.

In this embodiment, as shown in FIG. 14, the i-th pixel Pj (i) of the j-th line is set as the pixel of interest, and its image data is set as X, while i-1, i, i, i + 1-th pixel Pj-1 (i-1), Pj-1 (i), Pj-1 (i
+1) are defined as A, B, and C, respectively, and the target pixel Pj
Assuming that the difference data of the pixel Pj (i-1) immediately before (i) is D, the corrected image data X 'of the target pixel Pj (i) is calculated by the following equations (1) and (2). Has become. Note that Δ
X is difference correction data, and k1 to k4 are correction coefficients for performing weighting according to the degree of influence of the difference data of each pixel.

ΔX = k1A + k2B + k3C + k4D where Σki (i = 1 to 4) = 1 (1) X ′ = X + ΔX (2) In particular, in this embodiment, k1 = 0.2, k2 = 0.5, k3 =
0.2 and k4 are set to 0.1.

FIG. 15 shows the values of the difference data used in this embodiment and their polarities.

In the figure, NO. Indicates the division area number of the density gradation number of the image data DT, and NO.
No. 1 (virtual density gradation number -32 to -1 is added in this embodiment to make it equal to the other density gradation division areas). 32 to 95 density gradations
NO.2 represents the number of density gradations of the image data DT of 96 to 159, NO.3 represents the number of density gradations of the image data DT of 160 to 223, and NO.
DT density gradation number 224 to 255 (in this embodiment, virtual density gradation number 256 to 2
88 is added. ).

Then, the difference data ΔDT in each section is based on the intermediate position image data (eg, (32 + 96) / 2 in NO.1) located at the intermediate point of each section, and the image data DT and the intermediate position image data Are expressed with ± polarity.

In this way, the correction using the difference data ΔDT having ± polarity improves the density uniformity when reproducing a uniform density over a wide area, as compared with the correction using difference data having only + polarity or − polarity, for example. Is preferred.

Based on such a principle, the above-described error diffusion circuit 80 is configured, for example, as shown in FIG.

In the figure, reference numeral 81 denotes an adder.
The 8-bit image data DT from the buffer 70 is input to one of the input terminals. Reference numeral 82 denotes a latch circuit that temporarily stores output data from the adder 81 and then outputs the data. The output data of the latch circuit 82 is input to one input terminal of the adder 83. Further, reference numeral 84 denotes a latch circuit for temporarily storing the output data of the adder 83 and then outputting the data. The output data of the latch circuit 84 is sent to each of the comparators 71 to 74 shown in FIG. I have.

Reference numeral 85 denotes a threshold pattern setting circuit for setting each threshold when dividing the number of density gradations of the image data DT, and is fixed in advance to a predetermined pattern in this embodiment. Reference numeral 86 designates, as input data, the image data DT from the latch circuit 84, the threshold data TH from the threshold pattern setting circuit 85, and the address data ADT shown in FIG. (Corresponds to difference data A, B, C shown in Fig. 14)
The difference data ΔDT from the difference value generation circuit 86 is stored in the FIFO 87 for one line, and the difference data of the correction pixel for each pixel of interest is collected by the digital filter 88. Is to be included. The digital filter 88 performs a predetermined operation using the difference data A, B, and C of the correction pixel, and calculates k1A
+ K2B + k3C is output, and the correction data is input to the other input terminal of the adder 81.

Further, reference numeral 89 denotes image data DT from the latch circuit 84.
A lookup table (hereinafter abbreviated as LUT) for generating correction data k4D of a pixel immediately before the pixel of interest using the threshold data TH from the threshold pattern setting circuit 85 as input data. The data k4D is input to one input terminal of the adder 83.

In such an error diffusion circuit 80,
As shown in FIG. 17, the threshold pattern setting circuit 85 includes six threshold setting switches 91 to 96 for setting a predetermined threshold value. Each of the threshold setting switches 91 to 96 has, for example, TH0 = −3.
The respective threshold values TH are set in advance, such as 2, TH1 = 32, TH2 = 96, TH3 = 160, TH4 = 224, and TH5 = 288.

The difference value generation circuit 86 is also configured as shown in FIG.

In the figure, reference numerals 101 to 105 denote adders for adding threshold data (for example, TH0 and TH1, TH3 and TH4) mutually adjacent to the threshold setting switches 91 to 96, and reference numerals 106 to 110 denote the above adders. Dividers for dividing the added data from 101 to 105 by 1/2, 111 to 115 are latch circuits for latching the divided data from the dividers 106 to 110 at the time when the select signal is input to the OC port. .

Reference numeral 116 denotes a decoder in which one of the output ports Q0 to Q4 is selected as a select signal in accordance with the address data ADT, and the signal from each output port Q0 to Q4 is the OC signal of each of the latch circuits 111 to 115. Input to the port. The contents of the decoder 116 are shown in Table 4 below.

Reference numeral 117 denotes a subtractor for subtracting any one of the selected latch circuits 111 to 115 from the number of density gradations of the input image data DT. The subtracter 117 outputs 7-bit difference data ΔDT and 1 The bit polarity data m is output.

In such a difference value generation circuit 86, the threshold pattern setting circuit 85, the adders 101 to 105
The dividers 106 to 110 are provided with the intermediate position image data MD in the respective divided areas NO.0 to NO.4 of the density gradation number of the image data DT.
T, and on the other hand, the latch circuits 111 to 11
5 is selected corresponding to the address data ADT,
The selected latch circuit stores the corresponding intermediate position image data MD.
After latching T, it is sent to the subtractor 117, and this subtractor 117
Outputs the difference data ΔDT between the input image data DT and the intermediate position image data MDT together with the polarity data m.

The digital filter 88 used in this embodiment is
FIG. 18 shows the details of FIG.

In the figure, reference numerals 121 to 123 denote FIFOs shown in FIG.
Reference numeral 124 denotes a three-stage latch circuit for sequentially latching the differential data ΔDT sequentially read out from 87 in pixel units. Reference numeral 124 denotes a correction coefficient k1 for the output data of the first-stage latch circuit 121.
Is a coefficient multiplier that performs an operation of multiplying the output data of the second-stage latch circuit 122 by the correction coefficient k2, and 126 is a correction that is performed on the output data of the third-stage latch circuit 123. A coefficient multiplier that performs an operation to multiply the coefficient k3,
127 is an adder for adding the output data of each of the coefficient multipliers 124 to 126.

Such a digital filter 88 stores the differential data of the previous three pixels in the three-stage latch circuits 121 to 123.
A, B, and C (see FIG. 14) are latched, and the respective difference data A, B, and C and the respective correction coefficients k1, k are calculated by coefficient multipliers 124 to 126.
After multiplying by 2, k3, the adder 127 adds them, and outputs k1A + k2B + k3C.

Furthermore, the content of the LUT 89 is based on the difference data ΔDT (the
14 (corresponding to D in FIG. 14) and a correction coefficient k4 multiplied by the difference correction data k4D together with the polarity data thereof so as to be readable.

Therefore, according to the error diffusion circuit according to this embodiment, when the input image data X of the target pixel is input to one input terminal of the adder 81 as shown in FIG.
The first correction difference data [k1A + k2B + k3C] obtained by multiplying the difference data of three pixels one line before (corresponding to A, B, and C in FIG. 14) by the correction coefficients k1, k2, and k3 is output from the digital filter 88. Then, it is input to the other input terminal of the adder 81. On the other hand, the LUT 89 outputs second correction difference data [k4D] obtained by multiplying the difference data (corresponding to D in FIG. 14) of the pixel immediately before the target pixel by the correction coefficient k4.

In this state, in the adder 81, X + (k1A + k
2B + k3C), and this data is stored in the latch circuit 8.
At the stage where the second correction difference data [k4D] is added to one input terminal of the adder 83 via the second circuit 83, the corrected image data X ′,
That is, X + ΔX, (however, ΔX: k1A + k2B + k3C + k4D)
Is latched, and the corrected image data X 'is sent to the comparators 71 to 74.

In this embodiment, the threshold patterns input to the comparators 71 to 74, specifically, TH1 to TH4 are uniquely set.
As shown in the figure, the threshold pattern may be variably set.

In the figure, for example, a threshold setting circuit 130 (corresponding to the threshold setting switch 92 in FIG. 17) for setting a threshold TH1 includes a first threshold setting switch 131 for setting a first threshold, and a second threshold A second threshold setting switch 132 for setting, a selector 133 for selecting threshold data set by the first and second threshold setting switches 131 and 132, and a V clock signal divided by 2 to select the selector 133 It is composed of a flip-flop 134 created as a signal,
The selected threshold value TH1 is supplied to the adders 101 and 102, respectively.

As described above, if the two systems of thresholds are generated alternately, it is possible to forcibly cause the dot error and the dot to be in a fixed direction and suppress the generation of the unique pattern (texture) due to the error diffusion.

Next, the multi-level modulation circuit 56 used in this embodiment will be described.

FIG. 20 is a block diagram showing details of the multi-level modulation circuit 56.

In the figure, reference numeral 141 denotes an interface for taking in a 3-bit image density code SC into the multi-level modulation circuit. The image density code SC taken in the interface 141 is synchronized with the V clock signal VCK. Latch circuit 142
Is to be latched. The image density code SC from the latch circuit 142 is supplied to a selection code b (specifically, b (BK),
b (GY3), b (GY2), b (GY1), b (W)). On the other hand, reference numeral 144 denotes the V clock signal V
A gray generator that generates a modulation signal with a pulse width corresponding to the halftone image density code by using the phase shift of the pulse signal based on CK, and supports the modulation signals GY1 to GY3 from the gray generator 44 and the maximum image density code The modulation signal W corresponding to the zero image density code and the modulation signal W corresponding to the zero image density code are input to the selector 145, and the selector 145 selects and operates one of the modulation signals according to the selection code b of the decoder 143. The modulated signal is generated as an image density signal SD.

Table 5 below shows the contents of the decoder 143 used in this embodiment.

FIG. 21 shows details of the gray generator 144 used in this embodiment.

In the figure, reference numeral 150 denotes a frequency divider that divides the V clock signal VCK by half, reference numeral 151 denotes a delay line that delays the pulse signal from the frequency divider 150 by a plurality of predetermined delay times, 152 is a temperature-stable chip composed of a delay line having the same configuration as the delay line 151, and 153 to 1
56 is a CMOS gate for waveform shaping, and 157 to 159 are EOR gates.

In this embodiment, the delay line 151 is
As shown in FIG. 2, an inverter input tap 160 and a plurality of delay elements 161 to 166 connected in series to the inverter input tap 160 (in this embodiment, the delay amount of each delay element is set to a predetermined value in advance. ), And inverter output taps 167 to 172 that are drawn from the terminal portions of the delay elements 161 to 166. The input tap position is IN and the output tap position is TP (specifically, TP1 through TP
6).

In this embodiment, the delay line
Using three output taps TP2 to TP4 of 151, modulation signals of three pulse widths corresponding to halftone image density codes SC (1) to SC (3) are generated. In the embodiment, TP1 is used.

Next, a basic operation of the gray generator according to this embodiment will be described with reference to a timing chart shown in FIG.

Now, when the V clock signal VCK as the reference clock passes through the frequency divider 150, the V clock signal divided by 1/2 becomes a pulse signal based on the reference clock (corresponding to VCK / 2).
And is output from TP1 of the temperature stable chip 152 with a delay by the delay amount of the delay element 161 (DELAY0 in this embodiment).

On the other hand, when the pulse signal VCK / 2 is input to the delay line 151, the delay element 16
A pulse signal delayed by the delay amount of 1 and 162 (the delay amount of the delay element 162 is DELAY1 in this embodiment) is output, and the total delay amount of the delay elements 161 to 163 (the delay element in this embodiment) is output from TP3. DELAY2 for total delay of 162 and 163
TP4), and a pulse signal delayed by TP4 by the total delay amount of delay elements 161 to 164 (in this embodiment, the total delay amount of delay elements 162 to 164 is DELAY3) is output. Is done.

The pulse signal passing through the temperature stabilizing chip 152 and the pulse signal from each tap TP2 to TP4 of the delay line 151 are input to EOR gates 157 to 159 after passing through CMOS gates 153 to 156, respectively. Then, each EOR gate 1
The modulation signals GY1, GY2, GY3 from 57 to 159 are respectively
It is output as a signal having a pulse width corresponding to DELAY1 to DELAY3.

FIG. 24 shows a selector 145 used in this embodiment.
The details are shown below.

In the figure, reference numerals 173 to 177 denote modulation signals GY1 to GY3 from the gray generator 144, a modulation signal BK corresponding to the maximum image density code, and a modulation signal W corresponding to the zero image density code at one input terminal, respectively. While being input, selection codes b (specifically, b (BK), b (GY3), b (GY2), b (GY1), b
(W)) is an AND gate input to each of the other input terminals, and 178 is an OR gate for inputting the output from each AND gate. Only the AND gate corresponding to the high-level selection code is opened, and The modulated signal that has passed through the AND gate is output from the OR gate 178 as an image density signal SD.

In such a multi-level modulation circuit 56, each of the delay lines 151 to
DELAY3 is set as follows.

In general, the input image data
The relationship between the density gradation number N of the DT and the recorded image density J is obtained as a non-linear development characteristic curve Y shown by a solid line in FIG.

Under such circumstances, as shown by a virtual line in FIG. 25, if the relationship between the image density code SC and the recorded image density is corrected to a linear development characteristic curve Y ', the image density code SC is corrected. It is considered that the density difference of the recorded image density J with respect to (0) to SC (4) can be set at substantially equal intervals, and accordingly, it is considered that the tone reproducibility of the recorded image can be improved. .

From such a viewpoint, the image density codes SC (1), SC (2), SC on the corrected development characteristic curve Y '
By examining the recorded image density corresponding to (3), it is understood that the density corresponds to Y1, Y2, Y3 on the actual development characteristic curve Y. Therefore, the image density code SC (1),
When modulating the pulse width of the image density signal SD corresponding to SC (2), SC (3), the recording image density corresponding to Y1, Y2, Y3 of the development characteristic curve Y may be obtained.

Therefore, it is necessary to modulate the pulse width of the image density signal SD with the ratio α of the density gradation number of the input image data corresponding to Y1 to Y3 of the development characteristic curve Y to the maximum density gradation number. , The DELAY to DELAY3 is the ratio α
It is set according to.

Next, the operation of the laser printer according to this embodiment will be described.

In FIG. 5, when multi-gradation input image data DT is input to the screen generator 30, the input image data
An image density code SC corresponding to the number of density gradations of DT is output. The image density code SC is set corresponding to the number of sub-pixels PS when one pixel P is divided into four, as shown in FIG.

Thereafter, the image density code SC is taken into the multi-level modulation circuit 56 via the FIFO 40. Then, the image density code S
C is the selection code b at the decoder 143 part of the multi-level modulation circuit 56
(Specifically, b (BK), b (GY3), b (GY2), b (GY1), b
(W)), and when this is input to the selector 145, the modulated signals BK, GY3, GY2, G corresponding to the selection code b
One of Y1 and W is selected and output as an image density signal SD. The image density signals SD (1) to SD at this time
The pulse width of (3) corresponds to DELAY1 to DELAY3.

The image density signal SD output in this way is sent to the laser driver 57 to control the drive of the laser 10, as shown in FIG.

In the course of such an image recording operation, the relationship between the image density signals SD (0) to SD (4) and the recorded image density was examined and found. As shown by the imaginary line in FIG. It was confirmed that the development density characteristics were more linear as compared with This is because the modulation pulse codes C1 to C6 are used in the first embodiment when modulating the pulse width of the image density signal SD. Although the accuracy of the tone reproducibility is slightly lowered, this embodiment does not have the restrictions as in the first embodiment, and supports that the accuracy of pulse width modulation can be further improved.

Further, in this embodiment, unlike the first embodiment, it is not necessary to operate the shift register 65 at high speed with the high-frequency shift clock SCK, so that a high-frequency oscillator becomes unnecessary.
In addition, it is not always necessary to employ the ECL configuration as the multi-level modulation circuit 56.

Also, in this embodiment, the frequency divider 150
As shown in the figure, the V clock signal XCK is frequency-divided by 1/2 to generate a pulse signal VCK / 2 over the entire range of one pixel P. For this reason, as in the above embodiment, when extracting DELAY1 to DELAY3 from the delay line 151, the EOR gate 157 or
This is a simple circuit configuration using 159.

More specifically, for example, as shown in FIG.
If the clock signal VCK itself is used as a modulation reference pulse signal, a pulse signal delayed by DELAY from the delay line 151 and a modulation reference pulse signal are input to an EOR gate.
In the OR output, a pulse signal indicated by a two-dot chain line is also generated in addition to the pulse signal indicated by the solid line in the range of one pixel P, so that only the pulse signal corresponding to the DELAY cannot be extracted. In this case, It is necessary to extract a pulse signal corresponding to the delay with a logic circuit configuration other than the EOR gate shown in the embodiment.

Further, in this embodiment, the temperature stable chip 152 having the same configuration as the delay line 151 is used for the following reason.

For example, as shown in FIG. 29, when the modulation reference pulse signal VCK / 2 based on the V clock signal VCK passes through the delay line 151, the state changes from a state shown by a solid line to a state shown by a virtual line according to the temperature change. Even if it changes, the temperature stable chip 152 causes the same temperature change as the delay line 151, so that the modulation reference pulse signal VCK / 2 itself is shown by a virtual line from the state shown by a solid line when passing through the temperature stable chip 152. The state changes with substantially the same amount of displacement δ.
Therefore, even if the output pulse signal fluctuates due to the temperature change of the delay line 151, the modulation reference pulse signal VCK / 2 and the output pulse signal of the delay line 151 fluctuate while maintaining the relative positional relationship. , And the output pulse width of the EOR gate to which both are inputted is kept constant without being affected by the temperature change.

Furthermore, in this embodiment, since the CMOS gates 153 to 156 are used as the waveform shaping means, the fluctuation of the threshold position due to the temperature change is small. Therefore, as shown in FIG. 30, the threshold position (shown by a dashed line in the figure) may fluctuate, for example, when shaping the rising and falling portions of the output pulse signal of the delay line. Therefore, the pulse width of the output signal of the CMOS gate is kept stable.

In this embodiment, the delay amounts of the delay elements 161 to 166 of the delay line 151 are appropriately set in advance. For example, as shown in FIG. 31, commercially available delay lines 181 to 183, for example, The output taps O1 to O5 have a delay amount of 10 nsec. And the output lines O1 to O3 have a delay amount of 15 nsec. And the delay lines 182 and 183 have a uniform delay line. Delay amount of 10,15,20,25… 45 (nse
c.) It becomes possible to finely adjust the drawer tap
By appropriately selecting L1 to L8, a desired delay amount can be obtained.

Further, in this embodiment, the above-described gray generator 144 is used to unequally divide the pulse width of the image density signal SD.
However, even when the pulse width of the image density signal SD is equally divided, it can be applied by setting the delay amount of the delay line 151 equal.

Third Embodiment The laser printer according to the third embodiment is a further improvement of the second embodiment. The laser printer according to the second embodiment performs an optimum image reproduction according to a reproduction image mode (character mode or photo mode). However, a multi-level modulation circuit 56 different from that of the second embodiment is provided.

FIG. 32 is a block diagram showing details of the multi-level modulation circuit 56 according to this embodiment.

In the figure, reference numeral 191 denotes an interface for taking in the 3-bit image density code SC into the multi-level modulation circuit. The image density code SC taken in the interface 191 is synchronized with the V clock signal VCK. Latch circuit 192
Is to be latched. The image density code SC from the latch circuit 192 is supplied to a selection code b (specifically, b (BK), b) by a decoder 193 comprising P-ROM (having the same contents as in the second embodiment). (GY
3), b (GY2), b (GY1), b (W)).

On the other hand, reference numeral 194 denotes a modulation signal having a pulse width corresponding to a halftone image density code by using a phase shift of a pulse signal based on the V clock signal VCK and a two-system pattern (specifically, Left and right gray generators that are generated in
The left modulation signals LGY1 to LGY3 of the pattern spreading from the left and the right modulation signals RGY1 to RGY3 of the pattern spreading from the right from the left and right gray generator 194 are input to the left and right selection block 195. Reference numeral 196 denotes a mode select signal indicating either the character mode or the photograph mode.
A left / right switching signal generator that appropriately generates 1,0 left / right switching signals LRS according to the MS. The left / right switching signal LRS is sent to the left / right selection block 195. The left / right selection block 195 outputs the left modulation signal according to the left / right switching signal LRS.
LGY1 to LGY3 or right modulation signals RGY1 to RGY3 are selected and output, and either the left modulation signal or the right modulation signal is transmitted as modulation signals GY1 to GY3. Further, the modulation signals GY1 to GY3 from the left / right selection block 195, the modulation signal BK corresponding to the maximum image density code, and the modulation signal W corresponding to the zero image density code are input to the selector 197. One of the modulation signals is selectively operated by the selection code b of 193, and the selected modulation signal is generated as the image density signal SD.

FIG. 33 shows details of the left and right gray generators 194 used in this embodiment.

In the figure, reference numeral 201 denotes a frequency divider that divides the V clock signal VCK by half, and reference numerals 202 and 203 first delay the pulse signal from the frequency divider 201 by a plurality of predetermined delay times. And a second delay line, 204 is a temperature-stable chip composed of a delay line having the same configuration as the delay lines 202, 203, 205 to 211 are CMOS gates for waveform shaping, 212 to 214 are EOR gates, and 215 to 217 are AND gates. It is.

In this embodiment, the first and second delay lines 20
Reference numerals 2 and 203 denote delay lines 1 used in Example 2.
The output from the frequency divider 201 is input to the input tap IN of the first delay line 202, and the output taps TP2 to TP
The output from 4 is input to one terminal of the EOR gates 212 to 214 via the CMOS gates 206 to 208. On the other hand, the output from the output tap TP6 of the first delay line 202 is input to the input tap IN of the second delay line 203,
Output taps TP3 to TP5 of this second delay line 203
Is input to one input terminal of AND gates 215 to 217 via CMOS gates 209 to 211.
The output from the output tap TP1 of the temperature stabilizing chip 204 is input to the other input terminals of the EOR gates 212 to 214 and the AND gates 215 to 217 via the CMOS gate 205, respectively.

In such a circuit configuration, the output of the EOR gates 212 to 214 is given as left modulation signals LGY1 to LGY3, and the output of the AND gates 215 to 217 is right modulation signal.
It is provided as RGY3, RGY2, RGY1.

FIG. 34 shows details of the left / right selection block 195 and left / right switching signal generator 196 used in this embodiment.

In the figure, a left / right selection block 195 includes AND gates 221 to 226 to which the left modulation signals LGY3, LGY2, LGY1 and the right modulation signals RGY3, RGY2, RGY1 from the left / right gray generator 194 are input to one input terminal. Or gate 22
7 to 229 and an inverter 230 to which an output from the left / right switching signal generator 196 is input. The output from the left / right switching signal generator 196 is input to the other input terminal of the AND gates 221 to 223, and the output of the inverter 230 is input to the other input terminal of the AND gates 224 to 226. The outputs of the AND gates 221 and 224 are taken out as a modulation signal GY3 through an OR gate 227, the outputs of the AND gates 222 and 225 are taken out as a modulation signal GY2 through an OR gate 228, and the outputs of the AND gates 223 and 226 are taken out. Is extracted as a modulation signal GY1 through

The left / right switching signal generator 196 includes a flip-flop (hereinafter abbreviated as FF) 231 for dividing the V clock signal VCK by half, an output of the FF 241 and a mode select signal.
And a NAND gate 232 to which the MS is input.

Since the configuration of the selector 197 is the same as that employed in the second embodiment, a detailed description thereof will be omitted here.

Next, the operation of the multi-level modulation circuit 56 of the laser printer according to this embodiment will be described with reference to timing charts shown in FIGS.

Now, when the V clock signal VCK as the reference clock passes through the frequency divider 201, the V clock signal divided into 1/2 is a pulse signal based on the reference clock (corresponding to VCK / 2).
And is output from the TP1 of the temperature stable chip 204 with a delay of a predetermined delay amount (DELAY0 in this embodiment).

On the other hand, the pulse signal VCK / 2 is
, The output tap T of the first delay line 202
From P2, TP3, TP4, a predetermined delay amount (DELAY0 in this embodiment)
, Which are delayed by DELAY1, DELAY2, and DELAY3). Also, the second delay line
First delay line from 203 output taps TP3, TP4, TP5
A predetermined delay amount obtained by adding a delay amount to each output tap of the second delay line 203 to a delay amount between the input tap IN and the output tap TP5 of 202 (in this embodiment, DELAY0 and DELAY0 respectively).
Pulse signals delayed by 4, DELAY5 and DELAY6).

In this case, the EOR gates 212 to 214 output left modulation signals LGY1 to LGY3 having pulse widths corresponding to the DELAY1 to DELAY3. On the other hand, from the AND gates 215 to 217, D
Right modulation signal R with pulse width less ELAY4 to DELAY6
GY3, RGY2, RGY1 are output.

Here, it is assumed that the mode select signal MS indicates a character mode (in this embodiment, character mode: mode select signal MS = 0, photograph mode: mode select signal MS = 1).

At this time, as shown in FIG. 36 (a), the left / right switching signal LRS from the left / right switching signal generator 196 is always “1”, and the left modulation signals LGY1 to LGY3 remain unchanged from the modulation signals GY1 to GY3.
It is output as Y3 and input to the selector 197. Then, the selector 197 generates an image density signal SD one pixel at a time in accordance with the selection code from the decoder 193, sends it to the laser driver 57, and drives the laser 10.

In this driving operation process, the lighting operation of the laser 10 is a pattern (so-called sawtooth wave pattern) in which each pixel is always lit sequentially from the left as shown in FIG. , A line is formed, the resolution is increased by that amount, and fine lines such as characters are reproduced well.

On the other hand, assuming that the mode select signal MS indicates the photograph mode, the left / right switching signal LRS from the left / right switching signal generator 196 indicates "1" and "0" as shown in FIG. The output is alternately performed in each cycle of the V clock signal VCK (each pixel P unit), and the left modulation signals LGY1 to LGY3 are output.
And the right modulation signals RGY1 to RGY3 are alternately selected as modulation signals GY1 to GY3 for each pixel P and input to the selector 197. Then, the selector 197 generates an image density signal SD one pixel at a time in accordance with the selection code from the decoder 193, sends it to the laser driver 57, and drives the laser 10. Incidentally, in the multi-level modulation circuit 56 according to this embodiment,
The right modulation signals RGY1 and RGY2 are generated only for every two pixels, but in the photographic mode, no particular inconvenience occurs because they are used alternately with the left modulation signals LGY1 to LGY3.

In such a driving operation process, as shown in FIG. 37 (b), the lighting operation of the laser 10 turns on one of the two adjacent pixels P in order from the left, and turns on the other two pixels P in order from the right. Since this is a lighting pattern (a so-called triangular wave pattern), one line is formed by two pixels P, and the resolution is lower than that of the sawtooth wave pattern, but conversely, the gradation expression is improved, A halftone image such as a photograph is reproduced well.

Embodiment 4 FIG. 38 shows the case where the present invention is applied to a so-called one-pass two-color laser printer (for example, red and black in this embodiment).

In the figure, reference numeral 240 denotes, for example, a positively charged photoconductor, 2
41 is a charging corotron for pre-charging the photoreceptor 240, 242 is a ROS used in this embodiment, 243 is a bias type first developing device using, for example, a positive red toner, and 244 is a negative black toner, for example. The bias type second developing device used, 245 is a pre-transfer corotron for aligning the polarity of the toner image on the photoconductor 240, and 246 is a photoconductor 24 on the recording sheet 247.
A transfer corotron 248 for transferring the toner image on the photoconductor 240, a discharging corotron 248 for removing the recording sheet 247 electrostatically attached to the photoconductor 240 side, a cleaner 249 for removing residual toner on the photoconductor 240, and a photoconductor 250 An eraser lamp 251 for removing the residual charge on the body 240 is a fixing device for fixing the toner image on the recording sheet 247 after the transfer process.

FIG. 39 shows details of ROS242 used in this embodiment.

In the figure, reference numeral 261 denotes a semiconductor laser for forming an image of the first color, 262 denotes a semiconductor laser for forming an image of the second color, 263 denotes a polygon mirror that reflects beams Bm from both lasers 261 and 262 at different angles, and 264 denotes a polygon mirror. The polygon motor, 265 is an fθ lens, 266 is a mirror for guiding the beam Bm from the first color laser 261 to the first exposure unit E1 located in front of the first developing device 243 of the photoconductor 240, and 267 is a second color laser Mirrors 268 and 269 that guide the beam Bm from 262 to the second exposure unit E2 located after the first developing device 243 of the photoconductor 240 detect the scanning start positions of the first and second color laser beams, respectively.
SOS sensor.

The drive control system of the ROS242 is configured as follows.

In FIG. 38, reference numeral 270 denotes an image processing unit for outputting the first color (red) and second color (black) multi-tone image data RG, BG, and 271 and 272 separately process the respective image data RG, BG And an image density code S corresponding to each image data.
First and second screen generators 273 for generating CR and SCB, 273 are FIF0 for temporarily storing and outputting the image density code SC1 from the first screen generator 271, and 274 are image densities from the second screen generator 272. The gap memory 275 stores the code SC2 for a scanning time corresponding to the gap Gp between the first exposure unit E1 and the second exposure unit E2 and outputs the code SC2. The gap memory 275 drives and controls the laser 261 and the polygon motor 264 of the first color. One ROS controller, 276 is a second ROS controller that drives and controls the second color laser 262, 27
7 and 278 are respective laser drivers, and 279 is a motor driver of the polygon motor 264.

In this embodiment, the first and second screen generators 271, 272 are configured in the same manner as in the second embodiment,
The first ROS controller 275 basically has the elements shown in FIG. 5, while the second ROS controller 276 has the first controller except for the polygon motor controller.
It is configured almost the same as the 275. The multi-level modulation circuit of each of the ROS controllers 275 and 276 is configured in the same manner as in the second embodiment, but the multi-level modulation circuit of the first ROS controller 275 has the development characteristic curve YR of the first color shown in FIG. The multi-value modulation circuit of the second ROS controller 276 is configured to correct the development characteristic curve YB of the second color in FIG. 40 to be linear. The second ROS
In the multi-level modulation circuit of the controller 276, the first embodiment
Unlike the cases 2 and 3, since the non-exposed portion is an image portion, the output of the OR gate 178 needs to be inverted by the inverter 280 as the image density signal SD, for example, as shown by a virtual line in FIG.

Therefore, according to this embodiment, the image processing unit 270
Are converted into image density codes SCR and SCB, respectively, and then converted via the FIFO 273 or the gap memory 274 into the first and second ROS controllers 275 and 275.
Sent to 276.

At this time, first, the first ROS controller 275
By driving the polygon motor 1 and the polygon motor 264, a latent image Z1 having an exposed portion as an image portion as shown in FIG. Then, when the latent image Z1 is developed by the first developing device 243 under the first developing bias VB1, a first toner image T1 is formed as shown in FIG.

Thereafter, the second ROS controller 276 drives the laser 262, and a latent image Z2 in which a non-exposed portion becomes an image portion as shown in FIG. 41 (b) is formed in the second exposed portion E2 of the photoconductor 240. You.
When the latent image Z2 is developed by the second developing device 244 under the second developing bias VB2, a second toner image T2 is formed as shown in FIG.

Then, the toner images T1 and T2 are made uniform in polarity by the transfer pre-processing contron 245, then transferred to the recording sheet 247 by the transfer contron 246, and then fixed by the fixing device 251.

In the course of such a printing operation, when the gradation reproducibility of the print image on the print sheet 247 was examined, it was confirmed that both colors were extremely good.

[Effect of the Invention] As described above, according to the image recording apparatus of the first aspect, when performing the beam on / off control of the beam scanning unit, the image density code corresponding to the number of sub-pixels accompanying the pixel division. Is generated, the pulse width of the image density signal based on the image density code is modulated in order to correct the nonlinear development characteristic curve to a linear one.
While simplifying the apparatus configuration and reducing the cost, it is possible not only to reproduce a recorded image conforming to the development accuracy, but also to maintain extremely good gradation reproducibility of the recorded image.

According to the image recording apparatus of the present invention, when the image density code is generated, the density gradation number of the target pixel is corrected in consideration of the influence of the peripheral pixel data. It can be generated with high accuracy.

Furthermore, according to the image recording apparatus of the third aspect, when the image density code is generated, the two system thresholds are alternately switched, so that the error arrangement of the dots is forcibly set in a fixed direction, Generation of a unique pattern (texture) when the error diffusion method is employed can be effectively suppressed.

Furthermore, according to the image recording apparatus of the fourth aspect, it is possible to relatively easily configure the multi-level modulation means using existing circuit components.

Further, in the image forming apparatus according to the fourth aspect, when the reference pulse for setting the pulse width of the image density signal has a high frequency, the number of bits of the conversion pulse code is inevitably reduced. Since a large number of settings are required, the shift clock to the shift register must be transmitted at a high frequency, which inevitably causes a problem that the multilevel modulation means must have an expensive ECL configuration. According to the image recording apparatus of the fifth aspect, since the pulse width of the image density signal is arbitrarily set based on the reference clock, a high frequency shift clock is used as in the type of the fourth aspect. There is no need to generate the signal, and the multilevel modulation means having the TTL configuration can be manufactured at low cost as the multilevel modulation means.

According to the image recording apparatus of the present invention, it is possible to easily extract the phase shift of the pulse signal based on the reference clock when setting the pulse width of the image density signal. According to the image recording apparatus, the configuration of the delay unit can be simplified.

According to the image recording apparatus of the eighth aspect,
As the pulse signal based on the reference clock, a signal obtained by dividing the reference clock by half by the frequency dividing means is used, so that an image density signal having a modulated pulse width corresponding to the phase shift is generated from the pulse signal. In doing so, the pulse signal and the phase-shifted pulse signal can be processed by the EOR circuit, and the configuration of the arithmetic means of the multi-level modulation means can be simplified accordingly.

Further, when a delay line is used as a delay unit, which is one component of the multi-level modulation unit, as in the image recording apparatus according to the seventh aspect, the output signal of the delay line may fluctuate with a change in temperature. However, according to the image recording apparatus of the ninth aspect, the pulse signal based on the reference clock is input to the delay line having the same configuration as the delay line as the delay means. Even if the output signal of the delay line as the delay means fluctuates due to a temperature change, the amount of the fluctuation will be relatively equal, and accordingly, the pulse width error of the image density signal due to the temperature change should be reduced. Can be.

According to the image recording apparatus of claim 10, since the output signal from the delay means is shaped by the CMOS gate, it is possible to generate the image density signal in a state where the influence of the temperature change is effectively suppressed. Can be.

Furthermore, according to the image recording apparatus of the present invention, if a modulation pattern of a pulse width corresponding to a character image or a photographic image is set in advance, a gradation expression suitable for the recorded contents (characters or photographs) is provided. Can be easily performed.

According to the image recording apparatus of claim 12, a plurality of latent images are formed by a common or individual beam scanning unit, and each latent image is developed differently by a plurality of developing means using different developers. In this type, the beam scanning unit is drive-controlled so that the polarity of each development characteristic is corrected, so that the tone reproducibility of a recorded image based on each developer can be kept extremely good. The image quality of the system can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a schematic configuration of an image recording apparatus according to the present invention, FIGS. 2 (a) and 2 (b) are explanatory diagrams showing an operation of a density code generating means shown in FIG. 1, and FIG. FIG. 4B is an explanatory view showing the operation of the multi-level modulation means shown in FIG. 1, FIG. 4 is a perspective view showing the entire configuration of the ROS unit used in the image recording apparatus according to the first embodiment, and FIG. FIG. 6 is a block diagram illustrating a schematic configuration of an image recording apparatus according to the first embodiment. FIG. 6 is an explanatory diagram illustrating a circuit configuration of a screen generator used in the first embodiment. FIG. 7 is a multi-level modulation circuit used in the first embodiment. FIG. 8 is a timing chart showing the basic operation of the multi-level modulation circuit shown in FIG. 7, FIG. 9 is an explanatory view showing a method of setting data stored in the decoder shown in FIG. 7,
FIG. 10 is an explanatory diagram showing an operation state of the image recording device according to the first embodiment, FIG. 11 is an explanatory diagram showing an image forming process on a photoconductor of the image recording device according to the first embodiment, and FIG. FIG. 13 is a graph showing a relationship between an image density signal and a recorded image density according to the first embodiment. FIG. 13 is an explanatory diagram showing a circuit configuration of a screen generator used in the image recording apparatus according to the second embodiment.
13 is an explanatory diagram showing the operating principle of the error diffusion circuit of FIG. 13, FIG. 15 is an explanatory diagram showing the method of obtaining the value of the difference data and its polarity of FIG. 14, and FIG. 16 is the error diffusion of FIG. FIG. 17 is a block diagram showing details of the circuit, FIG. 17 is an explanatory diagram showing details of the difference value generating circuit of FIG. 16, FIG. 18 is an explanatory diagram showing details of the digital filter of FIG. 16, and FIG.
FIG. 20 is an explanatory view showing a modification of the screen generator according to the second embodiment. FIG. 20 is a block diagram showing details of a multi-level modulation circuit of the image recording apparatus according to the second embodiment. FIG. 21 is a gray generator shown in FIG. FIG. 22 is an explanatory diagram showing the configuration of the delay line used in FIG. 21, FIG. 23 is a timing chart showing the operation of the gray generator of FIG. 21, and FIG. 24 is a diagram of FIG. FIG. 25 is an explanatory diagram showing details of a selector used in the second embodiment, FIG. 25 is an explanatory diagram showing a method of setting a delay amount in a delay line of a gray generator used in the second embodiment, and FIG. 26 is an image recording device according to the second embodiment. FIG. 27 is an explanatory diagram showing an operation state, FIG. 27 is a graph showing a relationship between an image density signal and a recorded image density in the image recording apparatus according to the second embodiment, and FIG. 28 is a frequency division of a gray generator used in the second embodiment. The function of the vessel Illustration, Figure 29 is an explanatory view showing the function of the delay line for stable operation of the gray generator used in the second embodiment shown, FIG. 30 Example 2
FIG. 31 is an explanatory view showing a function of a waveform shaping gate of a gray generator used in Embodiment 2. FIG. 31 is an explanatory view showing a modification of a delay line as delay means used in Embodiment 2, and FIG.
FIG. 33 is a block diagram illustrating a multi-level modulation circuit of the image recording apparatus according to the third embodiment. FIG. 33 is a block diagram illustrating details of the left and right gray generators according to the third embodiment. FIG. 35 is a block diagram showing details of the block and the left / right switching signal generator. FIG. 35 is a timing chart showing the operating state of the left and right gray generators according to the third embodiment. FIGS. 37 (a) and 37 (b) are timing charts showing operation states of the selection block and the left / right switching signal generator. FIGS. The figure is a schematic diagram showing an image recording apparatus according to the fourth embodiment, FIG. 39 is an explanatory diagram showing details of the ROS unit used in the fourth embodiment, and FIG. 40 is the configuration of a multi-level modulation circuit used in the fourth embodiment Explanatory diagram showing the principle FIGS. 41 (a) and 41 (b) are explanatory views showing an image forming process on a photoreceptor of the image recording apparatus of Embodiment 4, FIG. 42 is a schematic view showing an example of a conventional image recording apparatus, and FIG. (A) and (b) are timing charts showing the image recording process, FIG. 44 is an explanatory diagram showing the image recording principle used in another conventional image recording apparatus, and FIG. 45 is the image recording shown in FIG. FIG. 4 is a graph showing a relationship between an image density signal used in the apparatus and a recorded image density. [Explanation of Symbols] DT: Multi-tone input image data SC: Image density code SD: Image density signal 1 ... Beam scanning unit 2 ... Photoconductor 3 ... Developing means 4 ... Density code generating means 5 .... Multi-level modulation means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-214078 (JP, A) JP-A-61-199374 (JP, A) JP-A-63-151211 (JP, A) JP-A-62-1 188563 (JP, A) JP-A-63-67076 (JP, A) JP-A-2-145366 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1 / 23-1 / 31 H04N 1/40-1/409 H04N 1/46 H04N 1/60

Claims (12)

(57) [Claims] 1. A photosensitive member by turning on / off a beam of a beam scanning unit (1) based on a pulse-like image density signal (SD) corresponding to multi-gradation input image data (DT) for each pixel. In the image recording apparatus for developing the latent image formed on the photoreceptor (2) by the developing means (3) after the beam scanning of (2), the density gradation number of the input image data (DT) of each pixel. Density code generation means (4) for generating density information of input image data (DT) as an image density code (SC) corresponding to the number of sub-pixels (M) associated with pixel division by dividing (N) by a predetermined threshold value; ), And after the image density code (SC) is generated by the density code generation means (4), the density gradation number (N) of the input image data (DT) and the recorded image density that has been visualized A non-linear development characteristic curve (Y) showing the relationship An image recording apparatus comprising: a multi-level modulation unit (5) for modulating a pulse width of an image density signal (SD) based on the image density code (SC) so as to correct the linearity. 2. The apparatus according to claim 1, wherein said density code generating means (4) includes a data correcting means for correcting the number of density gradations of the target pixel, and a target pixel corrected by said data correcting means. Code setting means for dividing the number of density gradations by a predetermined threshold value to obtain an image density code (SD), wherein the data correction means includes at least a target pixel and a front line corresponding to pixels located before and after the target pixel. An image recording apparatus characterized in that difference data between pixel data and a threshold value is added to current data of a target pixel with a predetermined weight. 3. The apparatus according to claim 1, wherein said density code generation means includes code setting means in which two system thresholds are set to be switchable. An image recording apparatus characterized by the following. 4. The multi-level modulation means (5) according to claim 1, wherein the multi-level modulation means (5) converts the image density code (SD) into a modulation pulse code having a predetermined number of bits larger than the number of sub-pixels (M). A shift register for temporarily storing a modulation pulse code from the decoder and serially outputting the modulated pulse code; a modulation pulse of an image density signal (SD) corresponding to the modulation pulse code from the shift register An image recording apparatus, wherein a width is set. 5. The multi-level modulation means (5) according to any one of claims 1 to 3, wherein said multi-level modulation means (5) converts a signal to a selection code corresponding to an image density code (SC), and a pulse signal based on a reference clock. Using the phase shift of
A gray generator for generating a modulation signal having a pulse width corresponding to a halftone image density code, a halftone modulation signal from the gray generator, a maximum density modulation signal corresponding to the image density code indicating the maximum image density, and an image indicating zero density An image recording apparatus, comprising: a selector to which a density zero modulation signal corresponding to a density code is input and one of the modulation signals is selected based on a selection code from the decoder. 6. The gray generator according to claim 5, wherein the gray generator delays a pulse signal based on the reference clock by a predetermined amount, and modulates a pulse width corresponding to the delay time by the delay unit. An image recording apparatus comprising: an arithmetic unit for generating a signal. 7. An image recording apparatus according to claim 6, wherein a delay line provided with a plurality of output taps having different delay amounts is used as the delay means. 8. An image according to claim 6, wherein the pulse signal based on the reference clock is obtained by dividing the reference clock by half by the frequency dividing means. Recording device. 9. A delay signal according to claim 7, wherein the pulse signal based on the reference clock is input to a delay line having the same configuration as the delay line as the delay means. An image recording apparatus, wherein the calculating means generates a modulation signal based on a relative difference between the two. 10. An image recording apparatus according to claim 6, wherein an output signal from said delay means is inputted to said arithmetic means through a CMOS gate for waveform shaping. 11. The multi-level modulation means (5) according to claim 1, wherein said multi-level modulation means (5) switches a pulse width modulation pattern according to a mode selection signal indicating one of a character mode and a photograph mode. An image recording apparatus comprising pattern switching means. 12. Having a plurality of developing means (3) using at least different developers and forming a plurality of latent images by a common or individual beam scanning unit (1),
2. The multi-level modulation means (5) according to claim 1, wherein each latent image is individually developed by a corresponding development means (3). An image recording apparatus comprising a plurality of gray generators.