JP3132218B2 - Layout method for semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of laying out a semiconductor integrated circuit device, particularly a semiconductor integrated circuit device having features in circuit arrangement and wiring.

[0002]

2. Description of the Related Art A conventional layout method for a semiconductor integrated circuit device will be described below with reference to the drawings.

FIG. 3 is a diagram showing a layout of a conventional semiconductor integrated circuit device. In FIG. 3, 1 is each rectangular block formed on a semiconductor substrate, and 2 is the rectangular block 1.
3 is a rectangular area (hereinafter referred to as a block terminal) manually or automatically set in each of the rectangular blocks 1, and 6 is a wiring prohibited area set inside each of the rectangular blocks 1. Fault data, 7 is a wiring automatically generated by computer processing to connect the respective block terminals 3 between the adjacent rectangular blocks 1, and 8 is a wiring 7 connecting the respective block terminals 3 within a range satisfying a design rule. Is not possible, it means that there is no wiring indicating the connection relationship between the block terminals.

The operation will be described below with reference to a mask layout diagram obtained by the semiconductor integrated circuit device configured as described above.

[0005] A plurality of rectangular blocks 1 are arranged on a semiconductor substrate. The rectangular blocks 1 are arranged adjacent to each other with reference to the outer frame 2 of the rectangular blocks 1. At this time, the block terminal 3 and the fault data 6 exist inside the outer frame 2 of the rectangular block 1 so as not to violate the design rule. When the connection between the adjacent rectangular blocks 1 is performed, the obstacle data 6 is not recognized from the block terminals 3 in one of the rectangular blocks 1, and the obstacle data 6 is pulled out to the outer frame 2 of the rectangular block 1. Means has been taken to avoid recognition of the data 6 and to connect it to the block terminal 3 in the adjacent rectangular block 1 (wiring 7).

[0006]

However, in the conventional layout method of a semiconductor integrated circuit device, when connection between adjacent rectangular blocks 1 is performed, wiring processing is performed between the block terminals 3 so that the same potential as that of the block terminals is required. The data is also recognized as the failure 6, and the wiring processing is performed while avoiding the failure. For this reason, the wiring length of the wiring 7 for connecting the rectangular blocks 1 tends to be long, and it is impossible to generate the wiring 7 within a range that satisfies the design rule, and the possibility of generating the non-wiring 8 is large. There was a problem of becoming. In addition, since the position of the block terminal largely depends on the wiring result 7, there is a problem that it takes time to set the block terminal 3 manually.

[0007]

To solve the above-mentioned conventional problems, a layout method of a semiconductor integrated circuit device according to the present invention has the following configuration. That is,
In a process of connecting a plurality of rectangular blocks formed on a semiconductor substrate, wiring data in a rectangular block having the same potential as a rectangular region set manually or automatically in each rectangular block is searched for and connected. A rectangular area closest to the counterpart rectangular block to be a block terminal, and connecting between blocks while avoiding recognizing a wiring prohibited area set in each block between the block terminals obtained in the above step. Is performed.

[0008]

According to the layout method of the semiconductor integrated circuit device according to the present invention, the length of the wiring for connecting the rectangular blocks is minimized without depending on the rectangular area manually or automatically set in the rectangular blocks. And the occurrence of non-wiring is minimized.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a layout of a semiconductor integrated circuit device according to this embodiment. In FIG. 1, 1 is a plurality of rectangular blocks formed on a semiconductor substrate, 2 is an outer frame defining the outline of the rectangular block 1, and 3 is a rectangular area (manually or automatically set in each rectangular block 1). 4 is a block terminal, 5 is wiring data in the rectangular block 1 having the same potential as the initial block terminal 3, and 6 is a wiring prohibited area set inside each rectangular block 1. Certain fault data 7 is wiring automatically generated by computer processing to connect the initial block terminals 3 between the adjacent rectangular blocks 1.

FIG. 2 is a diagram showing the inside of the rectangular block 1. All component numbers of the semiconductor integrated circuit device used in FIG. 2 are the same as those in FIG.

The operation will be described below with reference to a mask layout diagram obtained by the semiconductor integrated circuit device configured as described above.

A plurality of rectangular blocks 1 are arranged on a semiconductor substrate. The rectangular blocks 1 are arranged adjacent to each other with reference to the outer frame 2 of the rectangular blocks 1. Here, each rectangular block 1
As shown in FIG. 2, an outer frame 2 that defines the outline of the rectangular block 1, an initial block terminal 3 set inside the rectangular block, and a failure that becomes a wiring-prohibited area including the elements constituting the rectangular block and the existing wiring. The data and the information are configured and registered in the automatic layout device. The data in the rectangular block 1 exists inside the outer frame 2 of the rectangular block 1 so as not to violate the design rule even when two rectangular blocks are arranged adjacent to each other.

A wiring having the same potential as the initial block terminal 3 is searched from the wiring 7 inside the rectangular block 1 and re-registered as wiring data 5 having the same potential as the initial block terminal 3 in the automatic layout apparatus. Next, from among the re-registered wiring data 5, rectangular data closest to the mating rectangular block to be connected is set as the block terminal 4. Next, connection between adjacent rectangular blocks 1 is performed. At this time, the process is performed not using the initial block terminal 3 but using the block terminal 4 obtained by the above processing. Recognition and avoidance of the failure data 6 from the block terminal 4 in one rectangular block 1
To the outer frame 2 of the adjacent rectangular block 1 to avoid recognition of the failure data 6 inside the adjacent rectangular block 1.
(Wiring 7).

As described above, according to the present embodiment, the wiring data in the rectangular block having the same potential as the initial block terminal 3 in each rectangular block is searched for, and is closest to the partner rectangular block to be connected. When the connection between the adjacent rectangular blocks 1 is performed by the step of using the rectangular area as the block terminal, the rectangular block 1 does not depend on the initial block terminal 3.
The length of the wiring 7 for making connection between them can be minimized, and the occurrence of the non-wiring 8 can also be minimized.

In the embodiment shown in FIG. 1, the connection between the rectangular blocks 1 adjacent on the left and right is described, but the present invention is also applicable to the rectangular blocks 1 adjacent on the upper and lower sides.

[0017]

According to the present invention, wiring data in a rectangular block having the same potential as that of a rectangular area set manually or automatically in each rectangular block is searched for, and one of the rectangular blocks to be connected is searched for. When the connection between the adjacent rectangular blocks is performed by the step of using the nearest rectangular area as a block terminal, the length of the wiring 7 for connecting the rectangular blocks is determined independently of the rectangular area set manually or automatically. An object of the present invention is to realize an excellent layout method for a semiconductor integrated circuit device which can be minimized and the occurrence of unwiring can be minimized.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a layout diagram showing a structure in a rectangular block according to the present invention;

FIG. 3 is a layout diagram of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 rectangular block 2 outer frame of rectangular block 3 rectangular area manually or automatically set inside rectangular block 4 block terminal 5 wiring data 6 fault data 7 wiring (automatically generated by computer processing to connect between block terminals 8 Unrouted (if the route cannot be created within the range that satisfies the design rules)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (1)

(57) [Claims] In a process of connecting a plurality of rectangular blocks formed on a semiconductor substrate, wiring data in a rectangular block having the same potential as a rectangular region set manually or automatically in each rectangular block is stored. A step of searching and connecting the rectangular area closest to the other-side rectangular block to be connected to a block terminal, and avoiding recognition of a wiring prohibited area set in each block between the block terminals obtained in the above step A method of laying out a semiconductor integrated circuit device, comprising a step of performing inter-block connection while performing the connection.