JP3127253B2 - SOI semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed SOI
The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 12 is a sectional view showing a structure of a conventional SOI type semiconductor device. In the figure, 21 is a single crystal semiconductor substrate, 22 is a first conductivity type, for example, an insulating film for electrically insulating the p-type active layer 23 and the semiconductor substrate 21 from each other, and 35 is a second conductivity type. For example, an n-type source region, 36 is an n-type drain region as the second conductivity type, for example, 30 is a gate electrode, 34 is an insulating film on the side wall of the gate electrode 30, and 37 is an insulating film for electrically insulating wirings. film,
38 is a source electrode and 39 is a drain electrode.

In this type of semiconductor device, the impurity concentration of the active layer 23 is designed so that the thickness of the depletion layer that can be expanded from the gate electrode 30 side is greater than the thickness t ₁ of the active layer 23, and the SOI type is used. The structure is such that the entire region of the active layer 23 is depleted when the semiconductor device operates.

The reason for such a configuration is that the reduction of the effective electric field strength in the active layer 23 suppresses the mobility deterioration of the inversion layer carrier immediately below the gate insulating film 28, thereby increasing the drain current. This is because an increase in the drain current due to an increase in the inversion layer carriers corresponding to a decrease in the charge amount of the depletion layer in the active layer 23 can be realized.

Further, in the SOI type semiconductor device having this structure, since the inside of the active layer 23 is depleted by the gate electric field, the intrusion of the drain electric field from the drain junction to the active layer 23 can be suppressed, and the short channel of the threshold voltage can be suppressed. The effect can be suppressed. Further, the buried insulating film 2 immediately below the drain region 36
The parasitic capacitance can be reduced by increasing the thickness t ₃ of FIG. Therefore, this type of SOI semiconductor device can be expected to achieve both high integration and high-speed operation of the SOI semiconductor device by miniaturization of dimensions, and its future prospects have attracted attention in recent years.

[0006] In FIG. 12, the source region 35 and the drain region 36 are compared with the thickness t ₁ of the active layer 23.
The thickness t ₂ of the silicon layer is increased. This is because when the thickness of the source region 35 and the drain region 36 is reduced along with the thickness of the active layer 23, the parasitic resistance of the source region 35 and the drain region 36 increases, and the driving current of the SOI semiconductor device decreases. Therefore, in order to avoid this, the active layer 23
Only the thinner.

In the structure of the above-described conventional SOI semiconductor device, the cross section taken along the line X ₁ -X _{2 in} FIG. 12 shows that according to the conventional manufacturing method, as shown in FIG. It is formed. First, the reason why the side surface of the silicon active layer 23 is configured to be substantially perpendicular to the upper surface of the buried insulating film 22 will be described with reference to FIG. In FIG. 14, 21a is a semiconductor substrate, 22a is an insulating film, 23a is a silicon active layer, 28a is a gate insulating film, and 30a is a gate electrode. In the figure, the angle between the side surface of the end of the silicon active layer 23a and the insulating film 22a is an acute angle of 90 degrees or less when viewed from the silicon active layer 23a side. In this case, the corner portion B ₂ of the silicon active layer 23a, the electric field strength becomes stronger due to the gate electrode 30a than the corner portion B ₁ and the flat portion B _3, of the silicon active layer 23a, the flat portion B to conduct the originally current It is well known that the conduction occurs before ₃ and is observed as a leakage current of the semiconductor device.

On the other hand, in FIG. 13B, the corner A ₁
And in the corner portion A ₂ is substantially equal gate field strength, it is known that does not significantly electric field strength becomes higher as compared further with the flat portion A _3. Therefore, in the structure of FIG. 13A, it is easy to prevent generation of a leakage current.

[0009]

However, in the SOI type semiconductor device thus constructed, the end of the silicon active layer 23 is insulated from the silicon active layer 23 as shown in the enlarged view of FIG. The gate insulating film 28 in a region P that is a boundary with the film 22 becomes thinner. For this reason, there is a problem that the withstand voltage of the insulating film in this portion is reduced and the yield is also reduced. Further, when the silicon layer is etched perpendicularly to the insulating film as shown in FIG. 12 to perform element isolation, when the silicon layer has a large thickness t ₂ , the insulating film 37 can flatten this step. However, when forming a metal wiring, there is a problem that an etching residue is generated in a stepped portion, which is likely to cause a short circuit between the wirings and a disconnection. As described above, this type of SOI semiconductor device has the above-mentioned problem at the same time while having some great features.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and has as its object to solve fatal problems such as a decrease in breakdown voltage of a gate insulating film, a decrease in yield, a short circuit between wires, and a disconnection. It is an object of the present invention to provide an SOI semiconductor device capable of realizing a large-scale integrated circuit with a high yield and a manufacturing method thereof.

[0011]

In order to achieve the above object, an SOI semiconductor device according to the present invention has a first feature.
An edge film, formed on the first insulating film (2), and
Source region (15) and drain region (16) and this
Between these two regions and
And an active layer (3) having a small thickness.
Semiconductor eye having a side wall orthogonal to the first insulating film (2)
Lands (15,3,16) and this semiconductor island
A second insulating film (8) covering (15, 3, 16);
Formed on sidewalls of the semiconductor islands (15, 3, 16)
The third insulating film (9) and the active layer (3).
Gate electrode formed on the second insulating film (8)
(10) formed on the side wall of the gate electrode (10).
The fourth insulating film (14) and the third insulating film (9).
The residue (1) adhered during the formation of the gate electrode (13)
2) and formed so as to cover the residue (12).
A fifth insulating film (14) and the semiconductor island (1);
5,3,16) and the structure comprising the insulating film.
A sixth insulating film (17), and the sixth and second insulating films
Through contact holes opened in the films (17, 8)
And a source electrically connected to the source region (15).
Electrode (18) and the sixth and second insulating films (1).
Via contact holes opened in 7, 8)
A drain electrode electrically connected to the drain region (16);
Pole (19) and the S according to the present invention.
The method of manufacturing an OI type semiconductor device includes the steps of:
Forming a semiconductor layer (3) on the semiconductor layer;
(3) a step of forming a concave portion, and the step of forming the concave portion;
By anisotropically etching the semiconductor layer (3),
The edge has a side wall orthogonal to the first insulating film (2).
Step of forming semiconductor islands (15, 3, 16)
And on the surface of this semiconductor island (15, 3, 16)
Forming a second insulating film (20);
Third insulating film on sidewalls of islands (15, 3, 16)
Forming (9) and the second insulation in the recess
Forming a gate electrode (10) on the film (20);
A fourth insulating film (14) on a side wall of the gate electrode (10);
And forming a fifth on the third insulating film (9).
Forming an insulating film (14) of the gate electrode;
Using the semiconductor island (15,
Introducing an impurity into (3, 16);
A structure comprising lands (15, 3, 16) and the insulating film
Covering the structure with a sixth insulating film (17);
And the second insulating film (17, 20) has the source region
(15) and the drain region (16).
Opening contact holes, respectively;
The source electrode (18) and the drain electrode
Forming a pole (19).

[0012]

According to the present invention, the gate oxide film can be prevented from deteriorating by coating a thin portion of the gate oxide film on the side wall of the active layer, and the inclination of the side surface of the active layer can be reduced to flatten the semiconductor device. Since it is possible to adopt a configuration that facilitates the formation of the wiring and thus facilitates the formation of the wiring, it is possible to realize both an increase in the scale of the integrated circuit and an improvement in the yield.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing the structure of an n-channel semiconductor device as one embodiment of an SOI semiconductor device according to the present invention. In FIG. 1, reference numeral 1 denotes a single crystal semiconductor substrate made of, for example, silicon; and 2, an insulating layer made of, for example, a silicon oxide film for electrically insulating a semiconductor substrate 1 from a p-type active layer 3 of a first conductivity type. 8, a gate insulating film made of, for example, a silicon oxide film; 9, an insulating film made of, for example, a silicon nitride film having properties different from those of the silicon oxide film; 10, a gate electrode made of polycrystalline silicon; 12, a silicon layer; A silicon oxide film on the gate electrode 10, an insulating film 14 made of, for example, a silicon nitride film having a property different from that of the silicon oxide film, an n-type source region 15,
16 is an n-type drain region, 17 is an insulating film for insulating between wirings, 18 is a source electrode, and 19 is a drain electrode. In this case, the thickness t ₃ of the active layer ₃ depends on the thickness of the gate insulating film 8.
It is designed to be thinner than the thickness of the depletion layer that can spread from immediately below.

Next, the operation of the SOI semiconductor device thus configured will be described with reference to FIG. As shown in FIG. 2, a gate oxide film 8 is provided on the active layer 3, and an insulating film 9 made of a silicon nitride film is provided on a side wall of the active layer 3. It does not directly contact the thinned region P of the gate insulating film 8 as shown in b). Therefore, even when a high voltage is applied to the gate electrode 10, the electric field intensity does not locally increase, and the gate breakdown voltage of the semiconductor device can be dramatically improved. Insulating film 9 and insulating film 1
4 greatly reduces the step at the end of the active layer 3 and forms the insulating film 17.
This greatly improves the difficulty of forming the electrode wiring after the formation.

FIGS. 3 to 11 are sectional views showing the steps of an embodiment of a method for manufacturing an SOI semiconductor device according to the present invention. In these figures, first, as shown in FIG. 3, a semiconductor substrate having a silicon active layer 3 on an insulating film 2 in which, for example, a silicon oxide film is embedded in a single crystal semiconductor substrate 1 made of silicon is prepared.

Next, as shown in FIG. 4, for example, a silicon oxide film 4 is formed on the main surface side of the semiconductor substrate, and an oxidation resistant insulating film 5 of, for example, a silicon nitride film is deposited on the silicon oxide film 4. .

Next, as shown in FIG. 5, a resist is applied to the main surface side of the semiconductor substrate and then exposed to form a resist groove pattern having a predetermined size. Thereafter, using this resist as a mask, the insulating film 5 is etched by anisotropic plasma etching such as ECR stream etching, and the silicon oxide film 4 is further etched by hydrofluoric acid to expose the silicon active layer 3, Thereafter, the semiconductor substrate is exposed to an oxidizing atmosphere to form a silicon oxide film 6 having a predetermined thickness.

Next, as shown in FIG. 6, the insulating film 5 is removed with, for example, phosphoric acid, and then the silicon oxide film 6 and the silicon oxide film 4 are removed with, for example, hydrofluoric acid to expose the active layer 3. Thereafter, for example, a silicon oxide film 7 is formed on the surface of the active layer 3, a resist is applied on the silicon oxide film 7 and exposed, and the silicon oxide film 7 is coated with, for example, hydrogen fluoride in accordance with predetermined dimensions of the semiconductor device. The semiconductor active layer 3 is etched by an acid and subsequently the silicon active layer 3 is etched by an anisotropic plasma etching method to form a semiconductor element region. Subsequently, a predetermined amount of impurities of the first conductivity type for setting a threshold voltage in the active layer 3 is formed by, for example, ion implantation.
Introduce.

Next, as shown in FIG. 7, after removing the silicon oxide film 7, the semiconductor substrate is oxidized to form a gate oxide film 20 on the active layer 3. Subsequently, an insulating film 9 made of, for example, a silicon nitride film having a property different from that of the silicon oxide film is deposited on the main surface side of the semiconductor substrate.

Next, as shown in FIG. 8, the insulating film 9 on the main surface side of the semiconductor substrate is etched by an anisotropic plasma etching method to leave the insulating film 9 only on the side wall of the active layer 3. Thereafter, a silicon layer 10a used as a gate electrode is deposited on the main surface side of the semiconductor substrate.

Next, as shown in FIG. 9, the gate electrode 10 is formed by processing the silicon layer 10a to a predetermined size by anisotropic plasma etching. In this case, the silicon layer 10a may be left on the side wall of the active layer 3 as the silicon layer 12. Thereafter, the side surface of the gate electrode 10 is oxidized to form a silicon oxide film 13, and thereafter, an insulating film 14 made of, for example, a silicon nitride film having a property different from that of the silicon oxide film is deposited on the main surface side of the semiconductor substrate.

[0022] Then leave the insulating film 14 by anisotropic plasma etching method as shown in FIG. 1 0 as the insulating film 14 on the side walls of the gate electrode 10 is etched. At this time, the insulating film 14 is also left over the silicon layer 12 existing on the side wall of the active layer 3. Thereafter, in order to form a source region and a drain region, an n-type impurity is introduced by, for example, an ion implantation method, and the source region 15 and the drain region 1 are formed.
6 is formed.

[0023] Finally, after depositing an insulating film 17 on the main surface side of the semiconductor substrate as shown in FIG. 1 1, the source electrode 18 and drain electrode 19 by a contact hole.

In the step of FIG. 6, the oxide film 7 may not be used. Further, the ion implantation of the impurity for setting the threshold voltage may be performed immediately after forming the insulating film 9 in the step of FIG. In this case, after removing the gate oxide film 20, a gate oxide film is formed on the active layer 3 again.

[0025]

As described above, according to the present invention,
The following excellent effects can be obtained. Since the side surface of the active layer is configured to be substantially perpendicular to the buried oxide film to electrically isolate the semiconductor devices from each other, a step caused by the configuration is covered with an insulating film thicker than the gate oxide film. , The gate breakdown voltage can be prevented from deteriorating. In order to electrically isolate the semiconductor devices from each other, a step caused by etching the side surface of the active layer so as to be substantially perpendicular to the buried oxide film is first covered with an insulating film, and a gate generated later in the step region is formed. The silicon etching residue is automatically covered with the insulating film in the step of forming the insulating film on the side surface of the gate electrode, so that the silicon residue can be prevented from contacting other conductors. In order to electrically separate the semiconductor devices, the step created by etching the side surface of the active layer so as to be almost perpendicular to the buried oxide film is covered at a gentle angle using a thick insulating film. A problematic disconnection can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a configuration according to an embodiment of an SOI semiconductor device according to the present invention.

2 is a cross-sectional view of a Y ₁ -Y _2-wire SOI semiconductor device illustrated in FIG.

FIG. 3 is a cross-sectional view illustrating a step of an embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a step of an embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 5 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 6 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 7 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view illustrating a step of an embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 9 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 10 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 11 is a sectional view of a step for explaining one embodiment of a method for manufacturing an SOI semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view illustrating a configuration of a conventional SOI semiconductor device.

13A is a sectional view taken along line X ₁ -X ₂ in FIG.
(B) is an enlarged sectional view of a B part of (a).

FIG. 14 is a diagram illustrating an example of a cross-sectional structure of a conventional SOI semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal semiconductor substrate 2 Insulating film 3 Active layer 4 Insulating film 5 Insulating film 6 Silicon oxide film 7 Silicon oxide film 8 Gate insulating film 9 Insulating film 10 Gate electrode 10a Silicon layer 12 Silicon layer 13 Silicon oxide film 14 Insulating film 15n Source region 16 n-type drain region 17 insulating film 18 source electrode 19 drain electrode 20 gate oxide film

Claims (2)

(57) [Claims] And 1. A first insulating film is formed on the first insulating film, and, Oyo source region
Between the drain region and the drain region
Having an active layer thinner than these two regions,
And a peripheral portion having a side wall orthogonal to the first insulating film.
A semiconductor island, a second insulating film covering the semiconductor island, and a third insulating film formed on a side wall of the semiconductor island
And formed on the second insulating film so as to face the active layer.
A gate electrode, a fourth insulating film formed on a side wall of the gate electrode, and a film which adheres to the third insulating film when the gate electrode is manufactured.
And a fifth insulating film formed so as to cover the residue, the semiconductor island and the insulating film.
A sixth insulating film to be covered, and a contact hole opened in the sixth and second insulating films.
Via a tool electrically connected to the source region.
Source electrode and a contact hole opened in the sixth and second insulating films.
Electrically connected to the drain region through a
An SOI semiconductor device comprising a drain electrode . 2. A process for forming a semiconductor layer on a first insulating film.
A degree, a step of forming a recess in the semiconductor layer, anisotropically etching the semiconductor layer formed of the recess
Thereby, the side wall orthogonal to the first insulating film is formed on the peripheral portion.
Forming a semiconductor island having a semiconductor island, and forming a second insulating film on the surface of the semiconductor island
A step to form a third insulating film on a side wall of the semiconductor island
A step, to form a gate electrode on the second insulating film in said recess
Together that a step, to form a fourth insulating film on the sidewall of the gate electrode
Forming a fifth insulating film on the third insulating film
The semiconductor island using the gate electrode as a mask.
Introducing a step of introducing impurities, and a configuration comprising the semiconductor island and the insulating film.
A step of coating with a sixth insulating film; and forming the source region and the second insulating film on the sixth and second insulating films.
A contact hole facing the drain region,
Opening a source electrode and a drain in each of the contact holes.
Forming an electrode.
Of manufacturing a semiconductor device.