JP3125733B2 - DRAM with register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM refresh, and more particularly, to a DRAM with a register provided for refresh.

[0002]

2. Description of the Related Art Conventionally, this kind of dynamic random access memory device (hereinafter referred to as DRAM) has
In order to hold the internal data, a signal must be input to all row addresses (hereinafter referred to as row addresses) for a certain period of time, and the internal data must be rewritten (refresh operation).

In the conventional embodiment shown in FIG. 3, a refresh request generator 10 generates a request for a DRAM refresh operation at regular intervals, and a refresh counter 2
Notify 0. When the request for the refresh operation is received by the refresh counter unit 20, the row address for refreshing the DRAM is counted up and the row address is notified to the decoder unit 40. In addition, the usual R
When an EAD / WRITE access request occurs, the access request receiving unit 30 is notified. The access request receiving unit 30 notifies the row decoder unit 40 of the notified access request.

The row decoder section 40 performs a refresh operation of the notified row address or READ of an access request.
Requests the DRAM 50 to execute a / WRITE operation.

[0005]

The above-mentioned conventional DRA
The refresh operation of M is performed by a normal read / write operation.
Is performed separately from the access request. But DRAM
When a READ / WRITE access request is made, a row address is always accessed, and then a refresh operation is performed to access a column address (column address).

The internal data is held by the refresh operation only once in the same row address in a certain time, but the READ operation or W in the same row address is performed in the certain time.
In some cases, the RITE operation is performed, and as a result, the refresh operation consumes wasteful power and wastes time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DRAM having a register corresponding to a row address in a DRAM for solving the above-mentioned drawback, recording an access history and stopping the refresh operation when a refresh operation is requested at the same row address. To provide.

[0008]

According to a first aspect of the present invention, there is provided a DRAM with a register, comprising: a refresh request generating unit for generating a refresh request to the DRAM at predetermined time intervals;
A refresh counter unit for counting up a row address for refreshing M;
An access request receiving unit that receives an access request of an ITE instruction, the access request receiving unit, and the refresh
Row deco notified of address and request from counter
The RE and over the reader unit, for each row address of the previous Symbol DRAM
AD instruction or the WRITE instruction or the refresh
A row register register static recording the execution history when the shoe operation is executed, is configured with, the
The row decoder unit receives the READ instruction or WRITE
Row register corresponding to the row address of the instruction access request
Display the execution history of the
Execute, and when a refresh operation request is issued,
Refers to the execution history of the row register corresponding to the
When the row history is displayed, the execution
Release history display and skip the refresh operation request
And the execution history of the corresponding row register is displayed.
If not, the execution history is displayed and the refresh
Executing a call operation request.

[0009]

Further, a DRA with a register according to the second invention is provided.
M, the refresh counter in the first invention stores the row address initial values for refreshing the DRAM, counts up the row address when the previous SL refresh request is notified, the count A
The row address and refresh operation display
The specified refresh operation request is passed to the row decoder section.
And it is made of knowledge to Rukoto.

[0011]

Further, a DRA with a register according to the third invention is provided.
M is the first invention, wherein the access request receiving unit is:
Shi accepted when WRITE instruction to write data to the held write no READ command or the DRAM read data to the DRAM occurs this READ command or W
It is configured by notifying an access request of a RITE instruction to the row decoder unit.

Further, a DRA with a register according to the fourth invention is provided.
M is the first invention, wherein the row register is the D
The execution history is displayed in a row register corresponding to all the row addresses of the RAM and corresponding to the row address executed when the READ instruction or the WRITE instruction or the refresh operation is executed.

Further, a DRA with a register according to the fifth invention.
M, the row decoder part in the invention of the first or 4 checks whether the refresh operation displayed on the notified request, when the edentulous RE AD instruction or WRITE
Performs the operation corresponding to the instruction , and refreshes if there is
The operation corresponding to the operation request is performed.

[0015]

[0016]

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. FIG. 2 is a flowchart showing an example of the operation according to the embodiment of the present invention.

Referring to FIG. 1, the present embodiment employs DR
A refresh request generator 1 for generating an AM refresh request at regular intervals, a refresh counter 2 for counting up a row address to be refreshed,
The access request receiving unit 3 for receiving an access request of an EAD instruction or a WRITE instruction, a static-type row register 6 provided in the DRAM 5 for recording an execution history for each row address of the DRAM, and the row register 6 at the time of a refresh request are referred to. And a row decoder unit 4 for deciding whether or not to execute.

The refresh request generator 1 sets a time interval for refreshing the DRAM in advance, generates a refresh request at this time interval, and notifies the refresh counter 2 of the refresh request. The refresh counter unit 2 stores a row address for refreshing the DRAM, counts up the stored row address by 1 when a refresh request is notified, and sends a refresh operation request indicating refresh operation to the row address to the row decoder unit 4. Notify. The access request receiving unit 3
An access request of a READ instruction or a WRITE instruction, which is a normal operation, is accepted, and this access request is notified to the row decoder unit 4. The row register 6 performs a refresh operation, a READ operation, or a WRITE operation for each row address.
When the E operation is executed, the execution history is stored.

When the access request of the READ instruction or the WRITE instruction is notified, the row decoder unit 4 turns on the row register 6 corresponding to the row address to be executed, and then executes the access request. When a refresh operation is requested, the row register 6 corresponding to the row address to be refreshed is referred to. When the row register 6 is ON, the row register 6 is set to OFF and the refresh operation request is skipped. Corresponding row register 6
Is OFF, the row register 6 is set to ON and then a fresh operation is performed. When a refresh operation request is issued, the row register 6 corresponding to the row address to be refreshed is referred to. When the row register 6 is OFF,
The row register 6 is set to ON to execute the refresh operation.

Next, the operation of this embodiment will be described with reference to FIG. A read / write access request or a refresh request is acquired (S1). If the acquired request is a READ / WRITE access request, the access request is notified (S3), and the process of S6 is performed. If the acquired request is a refresh request, the process of S4 is performed (S3).
2).

The row address corresponding to the preset row register 6 of the DRAM 5 is counted up (S
4) The refresh operation request in which the counted row address and the refresh operation display are set is notified (S5), and the process of S6 is performed.

It is checked whether a refresh operation display is set in the notified request, and if the refresh operation display is set (refresh operation request), S9 is performed.
If the refresh operation display is not set (READ / WRITE access request), the process goes to S7.
(S6).

The row register 6 corresponding to the row address of the access request of READ / WRITE is set to ON and R
After executing the access request of EAD / WRITE, the process returns to S1 (S7, S8).

Referring to the row register 6 corresponding to the row address of the refresh operation request, it is checked whether it is ON (indicating that there is an execution history) or OFF (indicating that there is no execution history). Is performed and if it is ON, the process of S10 is performed (S9).

The row register 6 corresponding to the row address of the refresh operation request is set to ON, and after executing the refresh operation request, the process returns to S1 (S10, S11).

The row register 6 corresponding to the row address of the refresh operation request is set to OFF, the execution of the refresh operation request is skipped, and the process returns to S1 (S1).
2).

[0029]

As described above, the present invention provides a DRA
By providing a row register in the DRAM that retains the history of accessing the M row address within a certain period of time, the row address that has been subjected to the normal READ / WRITE operation is not subjected to the refresh operation. The effect of eliminating the power consumption for refresh and the unnecessary RE
This has the effect of reducing the weight of the AD / WRITE operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an example of an operation according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of an embodiment of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 refresh request generation unit 2 refresh counter unit 3 access request reception unit 4 row decoder unit 5 DRAM 6 row register 10 refresh request generation unit 20 refresh counter unit 30 access request reception unit 40 row decoder unit 50 DRAM

Continuation of the front page (56) References JP-A-4-26988 (JP, A) JP-A-8-31170 (JP, A) JP-A-7-211067 (JP, A) JP-A-7-57460 (JP, A) JP-A-6-12867 (JP, A) JP-A-4-53085 (JP, A) JP-A-3-102696 (JP, A) JP-A-9-282873 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/34

Claims (5)

(57) [Claims] 1. A DRAM with a register for reducing the number of refresh operations executed in units of row addresses to hold internal data of the DRAM, comprising: a refresh request generator for generating a refresh request to the DRAM at regular intervals; , a refresh counter for counting up a row address to be refreshed the DRAM, an access request receiving unit that receives an access request of the READ command or WRITE command, the a
Access request receiving unit and the refresh counter unit
A row decoder which is notified of the address and the request, the READ command or per row address before Symbol <br/> DRAM
The WRITE instruction or the refresh operation is executed
Been when a static wax register to record the execution history, the row decoder unit, the READ
Instruction or WRITE instruction access request row address
Display the execution history of the row register corresponding to the
Execute these access requests and execute the refresh operation request.
The row register corresponding to the requested row address.
Refer to the execution history, and when the execution history is displayed,
Cancels the display of the execution history of the row register and
Memory operation request, and skips the corresponding row register.
When the execution history is not displayed, the execution history is displayed.
A DRAM with a register that executes the refresh operation request after a delay. 2. The refresh counter according to claim 1 , wherein
The row address of the initial value for refreshing the RAM is
Stored when the refresh request is notified.
Count up the address and before counting up
Riff with row address and refresh operation display set
Notifying the row decoder unit of a refresh operation request
2. The DRAM with a register according to claim 1, wherein: 3. The access request receiving unit according to claim 2, wherein
Shi accepted when WRITE instruction to write data to write no READ command or the DRAM read data held in the M occurs claims and notifies an access request of the READ command or WRITE command to the row decoder portion Item 2. A DRAM with a register according to Item 1. 4. The row register corresponds to all row addresses of the DRAM and the read instruction or the WR
2. The DRAM with registers according to claim 1, wherein an execution history is displayed in a row register corresponding to an ITE instruction or a row address executed when the refresh operation is executed. 5. The information processing apparatus according to claim 1, wherein the row decoder unit receives the notified request.
Check if there is a refresh operation display of
Said operation corresponding to a READ instruction or a WRITE instruction
And if yes, respond to the refresh operation request.
5. The method according to claim 1, wherein the operation is performed.
DRAM with register.