JP3123255B2 - Active matrix substrate manufacturing method - Google Patents
Active matrix substrate manufacturing methodInfo
- Publication number
- JP3123255B2 JP3123255B2 JP25990192A JP25990192A JP3123255B2 JP 3123255 B2 JP3123255 B2 JP 3123255B2 JP 25990192 A JP25990192 A JP 25990192A JP 25990192 A JP25990192 A JP 25990192A JP 3123255 B2 JP3123255 B2 JP 3123255B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- transparent conductive
- film
- conductive film
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、透明導電膜とＡｌ系合
金薄膜が同一平面上にパターン形成されるような特にア
クティブマトリックス基板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an active matrix substrate, in which a transparent conductive film and an Al-based alloy thin film are formed on the same plane.
【０００２】[0002]
【従来の技術】透明絶縁基板上に、複数本のゲート線と
それと直交する複数本のソース線を配し、各交点にスイ
ッチング素子と画素電極を配置するアクティブマトリッ
クス基板において、画素電極として、ＩＴＯのような透
明導電膜、ソース線として、Ａｌ系合金薄膜を用いるこ
とが非常に多い。これは、ＩＴＯがシート抵抗が低く透
過率が高く、又、Ａｌは、容易にパターニングできる上
に低抵抗で密着性が高いためである。2. Description of the Related Art In an active matrix substrate in which a plurality of gate lines and a plurality of source lines orthogonal thereto are arranged on a transparent insulating substrate, and a switching element and a pixel electrode are arranged at each intersection, ITO is used as a pixel electrode. Al-based alloy thin films are very often used as transparent conductive films and source lines as described above. This is because ITO has low sheet resistance and high transmittance, and Al can be easily patterned and has low resistance and high adhesion.
【０００３】図３は、従来のアクティブマトリックス基
板の作製方法を図示したものである。（ａ）は、透明絶
縁性基板１上にゲート電極２、ゲート絶縁膜３、チャン
ネル領域４、ソース領域５、ドレイン領域６を形成し層
間絶縁膜７にコンタクトホールを開口したのち、ＩＴＯ
からなる透明導電膜８を堆積し、画素電極パターンを形
成したものである。（ｂ）はＡｌ−Ｓｉ合金薄膜９をそ
の上にスパッタにより堆積したものである。Ａｌ−Ｓｉ
は耐酸性が乏しく、ＩＴＯのウェットエッチ液に容易に
とけるため、ＩＴＯのパターン形成をＡｌ−Ｓｉのパタ
ーン形成より先に行なう必要がある。したがって、Ａｌ
−Ｓｉ薄膜はＩＴＯパターン上に堆積される構造にな
る。（ｃ）は、上述したＡｌ−Ｓｉ薄膜のソース線１３
をパターン形成するためにポジレジスト１０を現像した
直後の様子を示している。ＩＴＯのパターンエッジ１１
とドレインコンタクトホール１２では、Ａｌ−Ｓｉの被
ふく性が悪いため、アルカリ性のポジ現像液が浸み込
み、ＩＴＯが異常に高スピードでエッチングされる現象
が発生する。これは、ＩＴＯとＡｌ−Ｓｉが接触してい
るＩＴＯパターンに見られるもので、ポジ現像液により
電解腐食しているものと考えられる。したがって浸み込
みが発生するとどんどん広がってエッチングが進み、Ｉ
ＴＯのパターン欠損が発生する。（ｄ）図のような場合
には、ドレインコンタクトホール部のＩＴＯの欠落によ
り導通がとれなくなることもある。FIG. 3 illustrates a method of manufacturing a conventional active matrix substrate. 1A shows a case where a gate electrode 2, a gate insulating film 3, a channel region 4, a source region 5, and a drain region 6 are formed on a transparent insulating substrate 1, a contact hole is opened in an interlayer insulating film 7, and then ITO is formed.
The pixel electrode pattern is formed by depositing a transparent conductive film 8 made of. (B) shows an Al-Si alloy thin film 9 deposited thereon by sputtering. Al-Si
Is poor in acid resistance and easily melts in an ITO wet etchant, so that it is necessary to form an ITO pattern before forming an Al-Si pattern. Therefore, Al
-Si thin film has a structure deposited on the ITO pattern. (C) shows the source line 13 of the Al-Si thin film described above.
Shows a state immediately after the development of the positive resist 10 in order to form a pattern. Pattern edge 11 of ITO
In the drain contact hole 12, Al-Si is poorly covered, so that an alkaline positive developing solution infiltrates, and a phenomenon occurs in which ITO is abnormally etched at a high speed. This is seen in the ITO pattern in which ITO and Al-Si are in contact, and is considered to be electrolytically corroded by the positive developer. Therefore, when the infiltration occurs, the etching spreads more and more, and the etching proceeds.
TO pattern loss occurs. (D) In the case as shown in the figure, conduction may not be obtained due to lack of ITO in the drain contact hole.
【０００４】[0004]
【発明が解決しようとする課題】以上述べたように、透
明導電膜とＡｌ系合金が接触し、Ａｌにパターンづけを
行なう場合には、ポジレジストを用いて現像を行なうと
現像液により透明導電膜が電蝕されてパターン欠損が発
生するため、ネガレジストを用いてパターニングを行な
って来た。このため露光時のハレーションにより、ソー
ス線−画素間を十分広げたり、周辺に駆動回路を内蔵す
る場合にはＡｌ−Ａｌ間を十分広げる必要があり微細化
が困難で、高精細のパネルを実現することはできなかっ
た。As described above, when the transparent conductive film and the Al-based alloy are in contact with each other and patterning is performed on Al, development using a positive resist and development of a transparent conductive film Since the film is electrolytically eroded and a pattern defect occurs, patterning has been performed using a negative resist. For this reason, due to halation at the time of exposure, it is necessary to sufficiently widen the space between the source line and the pixel, or if the driving circuit is built in the periphery, it is necessary to sufficiently widen the space between Al and Al. I couldn't.
【０００５】従って本発明の目的は、ポジレジストを用
いても透明導電膜の電蝕がなく微細化がはかれ、高精細
のパネルを実現する製造方法を提供するものである。Accordingly, an object of the present invention is to provide a manufacturing method which realizes a high-definition panel in which a transparent conductive film can be miniaturized without electrolytic corrosion even when a positive resist is used.
【０００６】[0006]
【課題を解決するための手段】本発明のアクティブマト
リクス基板の製造方法は、 基板にスイッチング素子
と、前記スイッチング素子に接続されたソース線及び透
明導電膜とを有するアクティブマトリクス基板の製造方
法において、前記基板上に透明導電膜と前記透明導電膜
上に絶縁性薄膜を連続で形成し、ポジレジストパターン
を用いて前記透明導電膜上に前記絶縁性薄膜が残るよう
に前記絶縁性薄膜及び前記透明導電膜をパターニングし
て画素電極を形成し、前記ソース線となる薄膜を前記絶
縁性薄膜に接するように形成し、ポジレジストパターン
を用いて前記ソース線となる薄膜をパターニングしてソ
ース線を形成する工程とを有することを特徴とする。According to the present invention, there is provided a method of manufacturing an active matrix substrate having a switching element, a source line connected to the switching element, and a transparent conductive film. A transparent conductive film is formed on the substrate, and an insulating thin film is continuously formed on the transparent conductive film, and the insulating thin film and the transparent film are formed using a positive resist pattern so that the insulating thin film remains on the transparent conductive film. A conductive film is patterned to form a pixel electrode, a thin film to be the source line is formed so as to be in contact with the insulating thin film, and a thin film to be the source line is patterned using a positive resist pattern to form a source line And a step of performing
【０００７】[0007]
【作用】本発明は透明導電膜のポジレジスト現像液から
の電蝕をさけるために、透明導電膜とＡｌ系合金薄膜の
間に絶縁性薄膜（例えば、窒化膜、レジストなど）を介
在させ、両膜を絶縁分離するものである。According to the present invention, an insulating thin film (for example, a nitride film or a resist) is interposed between the transparent conductive film and the Al-based alloy thin film in order to prevent electrolytic corrosion of the transparent conductive film from the positive resist developer. This is to insulate and separate both films.
【０００８】[0008]
【実施例】本発明の第１の実施例を図１を用いて説明す
る。（ａ）は、透明導電膜８とＡｌ系合金薄膜とを絶縁
分離する絶縁性薄膜１４を連続で堆積したものである。
例えば、ＣＶＤのＳｉＮ、ＳｉＯ2を１０００Å程度堆
積する。（ｂ）は、ポジレジストパターン１５を用い
て、連続的にエッチングし、画素電極をパターン形成し
たものである。（ａ）、（ｂ）においては、連続デポ、
連続エッジでなく、透明導電膜デポ後パターニング、次
に絶縁性薄膜デポ後パターニングというように分けて行
なってもよいし、同一パターンとせずに絶縁性薄膜のパ
ターンを少々広くしても同じことである。（ｃ）は、前
記レジストを除去したのち、Ａｌ系合金薄膜１６をスパ
ッタ法により堆積し、ソース線１３形成用ポジレジスト
１７の現像直後の様子を示すものである。図３とは異な
り、透明導電膜８とＡｌ系合金薄膜１６の間には、絶縁
性薄膜が介在し、絶縁分離されているため、Ａｌ系合金
薄膜の被ふく性の悪い、画素パターンのエッジ１１と、
ドレインコンタクトホール部１２でポジ現像液の浸み込
みが起っても透明導電膜８の電蝕は発生しない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. (A) is obtained by continuously depositing an insulating thin film 14 for insulating and separating the transparent conductive film 8 and the Al-based alloy thin film.
For example, SiN or SiO 2 of CVD is deposited at about 1000 °. (B) is a pattern in which the pixel electrode is patterned by continuous etching using the positive resist pattern 15. In (a) and (b), a continuous depot,
Instead of continuous edges, patterning after the transparent conductive film deposition, then patterning after the insulating thin film deposition may be performed separately. is there. (C) shows the state immediately after the Al-based alloy thin film 16 is deposited by the sputtering method after the removal of the resist, and the positive resist 17 for forming the source line 13 is developed. Unlike FIG. 3, an insulating thin film is interposed between the transparent conductive film 8 and the Al-based alloy thin film 16 and is separated from the transparent conductive film 8 and the Al-based alloy thin film 16. 11 and
Even if the positive developer penetrates into the drain contact hole portion 12, no electrolytic corrosion of the transparent conductive film 8 occurs.
【０００９】（ｄ）は、ポジレジストをはくりした最終
状態の様子で、画素電極上の絶縁性薄膜は、残しておけ
ば、液晶への印加電圧の直流成分をカットする保護膜に
もなりうる。(D) shows a final state in which the positive resist is stripped, and the insulating thin film on the pixel electrode is also used as a protective film for cutting a DC component of a voltage applied to the liquid crystal, if it is left. sell.
【００１０】透明導電膜は、ＩＴＯ膜が普通であるが、
より安定なＳｎＯ2 にも効果がある。Ａｌ系合金は、通
常シリコン薄膜との接続抵抗を良くするためにＡｌ−Ｓ
ｉさらには、緻密で平坦性がよいＡｌ−Ｓｉ−Ｃｕを用
いても同様である。絶縁性薄膜１４は、下地層間絶縁膜
７とは異なる方が、透明電極上の絶縁膜を取り除きたい
場合は都合がよい。特に、層間絶縁膜７としてＳｉＯ
2 、絶縁性薄膜１４としてＳｉＮを用いれば、Ａｌ−Ｓ
ｉのエッチング後のＣＦ4 ガスによるドライエッチでの
Ｓｉの粉取り工程で一度にＳｉＮも除去できる。The transparent conductive film is usually an ITO film.
The more stable SnO 2 is also effective. Al-based alloys are usually made of Al-S to improve the connection resistance with the silicon thin film.
i Furthermore, the same applies to the case of using Al—Si—Cu which is dense and has good flatness. The insulating thin film 14 is different from the underlying interlayer insulating film 7, and it is convenient to remove the insulating film on the transparent electrode. In particular, as the interlayer insulating film 7, SiO
2. If SiN is used as the insulating thin film 14, Al-S
SiN can be removed at a time in a Si powder removal step by dry etching with CF 4 gas after i etching.
【００１１】図２は本発明の第２の実施例を示すもので
ある。本図は絶縁性薄膜としてレジストを用いた場合を
示すものである。FIG. 2 shows a second embodiment of the present invention. This figure shows a case where a resist is used as an insulating thin film.
【００１２】（ａ）は、透明導電膜８にポジレジスト１
８にて画素電極パターンを形成したものである。（ｂ）
は、前記ポジレジストをはくりせずに、適度な乾燥と前
処理後にＡｌ系合金薄膜１６を堆積したものである。レ
ジストは、ネガレジストよりもポジレジストの方が膨潤
によるパターンだれが少なく、Ａｌ系合金スパッタ後で
もレジストに“しわ”がよらず好ましい。（ｃ）は、ソ
ース線１３形成用ポジレジスト１９を現像し、Ａｌエッ
チ直後の様子を示すものである。（ｄ）は、レジストを
はくりした最終状態の様子で、画素電極上レジスト１８
とソース線上レジスト１９が同時にはくりできる。図２
は、図１に比べ絶縁性薄膜１４を堆積することなく、従
来の工程数を増加しない長所がある。FIG. 1A shows that a positive resist 1 is applied to a transparent conductive film 8.
8, a pixel electrode pattern is formed. (B)
Is an Al-based alloy thin film 16 deposited after appropriate drying and pretreatment without removing the positive resist. As for the resist, a positive resist has less pattern dripping due to swelling than a negative resist, and is preferable because the resist does not "wrinkle" even after Al-based alloy sputtering. (C) shows a state immediately after the Al resist has been developed by developing the positive resist 19 for forming the source line 13. (D) is a final state after the resist is removed, and the resist 18 on the pixel electrode is removed.
And the resist 19 on the source line can be stripped at the same time. FIG.
1 has an advantage that the number of steps is not increased compared to FIG. 1 without depositing the insulating thin film 14.
【００１３】本発明は、以下に述べる如き顕著な効果を
奏することができる。 （ａ）ソース線となる薄膜と透明導電膜との間に絶縁性
薄膜を介在させることにより、ソース線のパターン形成
がポジレジスト系でも透明導電膜の電蝕によるパターン
欠落がなくソース線のパターニングが可能である。The present invention has the following remarkable effects. (A) By interposing an insulating thin film between the thin film serving as the source line and the transparent conductive film, even if the source line pattern is formed in a positive resist system, there is no pattern loss due to electrolytic corrosion of the transparent conductive film, and the source line is patterned. Is possible.
【００１４】実施例２においては、従来と工程数も増え
ないという長所がある。The second embodiment has an advantage that the number of steps is not increased as compared with the prior art.
【００１５】[0015]
【図１】本発明の第１の実施例を示す工程図。FIG. 1 is a process chart showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す工程図。FIG. 2 is a process chart showing a second embodiment of the present invention.
【図３】従来例を示す工程図。FIG. 3 is a process chart showing a conventional example.
１ 透明絶縁基板 ２ ゲート電極 ３ ゲート絶縁膜 ４ チャンネル領域 ５ ソース領域 ６ ドレイン領域 ７ 層間絶縁膜 ８ 透明導電膜 ９，１６ Ａｌ合金薄膜 １０，１７，１９ ソース線形成用ポジレジスト １１ 画素電極エッジ １２ ドレインコンタクトホール １３ ソース線 １４ 絶縁性薄膜 １５，１８ 画素電極形成レジスト DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Gate electrode 3 Gate insulating film 4 Channel region 5 Source region 6 Drain region 7 Interlayer insulating film 8 Transparent conductive film 9, 16 Al alloy thin film 10, 17, 19 Source line forming positive resist 11 Pixel electrode edge 12 Drain contact hole 13 Source line 14 Insulating thin film 15, 18 Pixel electrode forming resist
Claims (1)
ッチング素子に接続されたソース線及び透明導電膜とを
有するアクティブマトリクス基板の製造方法において、 前記基板上に透明導電膜と前記透明導電膜上に絶縁性薄
膜を連続で形成し、ポジレジストパターンを用いて前記
透明導電膜上に前記絶縁性薄膜が残るように前記絶縁性
薄膜及び前記透明導電膜をパターニングして画素電極を
形成し、前記ソース線となる薄膜を前記絶縁性薄膜に接
するように形成し、ポジレジストパターンを用いて前記
ソース線となる薄膜をパターニングしてソース線を形成
する工程とを有することを特徴とするアクティブマトリ
クス基板の製造方法。1. A method for manufacturing an active matrix substrate having a switching element on a substrate, and a source line and a transparent conductive film connected to the switching element, wherein a transparent conductive film is formed on the substrate and an insulating film is formed on the transparent conductive film. Forming a pixel electrode by continuously forming a conductive thin film and patterning the insulating thin film and the transparent conductive film so that the insulating thin film remains on the transparent conductive film using a positive resist pattern; Forming a thin film to be in contact with the insulating thin film, and patterning the thin film to be the source line using a positive resist pattern to form a source line. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25990192A JP3123255B2 (en) | 1992-09-29 | 1992-09-29 | Active matrix substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25990192A JP3123255B2 (en) | 1992-09-29 | 1992-09-29 | Active matrix substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06110083A JPH06110083A (en) | 1994-04-22 |
| JP3123255B2 true JP3123255B2 (en) | 2001-01-09 |
Family
ID=17340514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25990192A Expired - Lifetime JP3123255B2 (en) | 1992-09-29 | 1992-09-29 | Active matrix substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3123255B2 (en) |
-
1992
- 1992-09-29 JP JP25990192A patent/JP3123255B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06110083A (en) | 1994-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2010147494A (en) | Thin-film transistor and method for manufacturing the same | |
| JPH055898A (en) | Thin-film element forming panel | |
| JP4674926B2 (en) | Liquid crystal display panel and manufacturing method thereof | |
| US4451554A (en) | Method of forming thin-film pattern | |
| KR100660811B1 (en) | method of fabricating electro line for liquid crystal display | |
| JP2002237594A (en) | Thin-film transistor, method for manufacturing thin-film transistor and the thin-film transistor device | |
| JP3123255B2 (en) | Active matrix substrate manufacturing method | |
| JP3200639B2 (en) | Method for manufacturing thin film transistor panel | |
| JPH04171767A (en) | Thin film transistor and manufacture thereof | |
| KR19990042670A (en) | Manufacturing method of liquid crystal display device | |
| JP2000011863A (en) | MANUFACTURE OF Cr/Cu/Cr WIRING STRUCTURE, MANUFACTURE OF PLASMA DISPLAY PANEL USING THE BODY AND IMAGE DISPLAY DEVICE USING THE STRUCTURE | |
| JP3076483B2 (en) | Method for manufacturing metal wiring board and method for manufacturing thin film diode array | |
| JPH1096937A (en) | Liquid crystal display element and its production | |
| JPH0618912A (en) | Liquid crystal display device and its production | |
| JP3270920B2 (en) | Manufacturing method of liquid crystal display device | |
| JP2004294804A (en) | Method for manufacturing display device, liquid crystal display device and method for patterning metal film | |
| JPH06326130A (en) | Flattening method and flattened element | |
| JPH07176525A (en) | Forming method of low-resistance wiring | |
| JPH03240027A (en) | Display device | |
| JPS614233A (en) | Etching method of transparent electrically conductive film | |
| JPH02130551A (en) | Thin film pattern and production thereof as well as matrix circuit board formed by using this pattern and image display device | |
| KR0141772B1 (en) | Method of forming via hole | |
| JPH0695574B2 (en) | Method of manufacturing thin film field effect transistor | |
| JPS61145530A (en) | Manufacture of thin-film transistor array | |
| JP2921503B2 (en) | Manufacturing method of electrical contact |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081027 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091027 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101027 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101027 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111027 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121027 Year of fee payment: 12 |
|
| EXPY | Cancellation because of completion of term |