JP3123066B2 - Drive circuit for brushless motor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial application fields B. Summary of the invention C. Conventional technology D. Problems to be solved by the invention E. Means to solve the problems F. Function G. Embodiment G _1. Configuration of embodiment ( Figure 1 - Figure 5) G _2. operation and effect (Figure 6) H. fIELD the present invention on the effects A. industrial invention examples using sensors, for the rotor magnet position detection Do not switch the current flowing to the motor coil by the back electromotive voltage generated in the motor coil.
The present invention relates to a brushless motor drive circuit for driving a brushless motor without a sensor.

B. Effects of the Invention The present invention relates to a sensorless drive brushless motor drive circuit, in which a signal inverting at a zero crossing point of a back electromotive voltage generated in a motor coil and an inverted signal of this signal are each a two-level section. By using clocks of different frequencies, up-counting and down-counting or down-counting and up-counting are performed continuously, and the timing of switching the current flowing through the motor coil is created from the count result, thereby digitizing the drive circuit. This facilitates integration and reduces variations in characteristics.

C. Conventional technology A direct current (DC) brushless motor uses a magnet for the rotor, arranges a multi-phase motor coil on the stator, sequentially switches the current flowing through the motor coil, generates a rotating magnetic field, and generates a rotating magnetic field. It is to rotate. At this time, a brushless motor that generates a timing signal by detecting the position of a rotor magnet using a position detection sensor such as a Hall element as a means for generating a timing signal for switching a current (drive current) flowing through a motor coil is generally used. Conventionally, a sensorless drive brushless motor that generates a timing signal for switching the drive current by using a back electromotive voltage generated in a motor coil without using a sensor such as a Hall element is conventionally known.

In such a sensorless drive brushless motor, a timing signal for switching a drive current flowing through the motor coil is created using a zero cross point (zero cross point) of a back electromotive voltage generated in the motor coil due to rotation of the rotor. However, between the zero cross point and the switching point of the drive current flowing through the motor coil, the latter is basically delayed by 30 electrical degrees. When generating the timing signal delayed by 30 degrees, an analog delay circuit is generally used. However, since the delay time is fixed, when the rotation speed changes by variable speed driving or the like, the delay amount in electrical angle changes. There is a disadvantage. For this reason, the present applicants have previously disclosed in Japanese Patent Application No. 63-199312 a sensorless brushless motor in which the drive current of a motor coil can be switched at a timing delayed by a predetermined electrical angle regardless of the rotational speed. A drive circuit was proposed.

The drive circuit of the brushless motor disclosed in Japanese Patent Application No. 63-199312 uses two analog integrators to detect a signal that reverses every 60 electrical degrees at the zero cross point of the back electromotive voltage generated in the drive coil. This signal and the inverted signal of this signal are each integrated by the above-mentioned integrator, and the integrated signals are compared with each other to obtain a signal which is inverted at an intermediate point between adjacent zero cross points, and an edge of this signal is detected. By doing so, a drive current switching timing signal delayed by a predetermined electrical angle regardless of the rotation speed is generated.

D. Problems to be Solved by the Invention However, the drive circuit of the brushless motor in the above-described conventional technique uses two integrators, delays the zero cross point by an electrical angle of 30 degrees by an analog method, and drives the motor coil. Since the switching points of the currents are combined, there are disadvantages such as a difference in the timing of energization due to variations in the characteristics of the two integrators and the necessity of two capacitors as external components when integrated.

The present invention has been made in order to solve the above-mentioned drawbacks, and has as its object to provide a sensorless drive brushless motor drive circuit that has less characteristic variation, is easy to integrate, and can cope with variable speed. I do.

E. Means for Solving the Problems In order to achieve the above object, the configuration of the drive circuit of the brushless motor according to the present invention is such that the current flowing through a plurality of motor coils on the stator side is switched by a predetermined timing signal to switch the rotor. A driving circuit for a brushless motor to be rotated, a means for detecting a signal inverted at a zero cross point of a back electromotive voltage generated in each of the motor coils, and generating a first clock signal and a second clock signal having a higher frequency than the first clock signal. Means for performing the up-counting from one predetermined value to another predetermined value with the first clock signal first in a section of one signal level state of the signal inverted at the zero crossing point, and then the other signal level state In the section, the down-counting is performed by the second clock signal until the value returns from the another predetermined value to the certain predetermined value, or is inverted at the zero cross point. First, in the section of one of the signal level states, the first timed signal counts down from one predetermined value to another predetermined value, and then in the section of the other signal level state, the second timed signal A first up-down counter for performing an up-count from the another predetermined value to the certain predetermined value, and a signal level state of one of a signal obtained by inverting a signal inverted at the zero cross point. Up-counting is performed from a certain predetermined value to another predetermined value by the first clock signal, and then down counting is performed by the second clock signal from the another predetermined value to the certain predetermined value in the other signal level state section. The first count signal is used to count down from a predetermined value to another value at the beginning of a signal level state of one of the inverted signals of the signal inverted at the zero crossing point. A second up / down counter for performing up to a constant value and subsequently performing an up-count with the second clock signal from the another predetermined value to the certain predetermined value in the other signal level state section; From the time when the count result of the up / down counter returns to the certain predetermined value and the time when the count result of the second up / down counter returns to the certain predetermined value, the current flows to the plurality of stator-side motor coils. Means for generating a timing signal for switching the current.

F. Function The present invention detects a signal that is inverted at a zero crossing point of a back electromotive voltage generated in a motor coil, and determines a signal in two sections of a high level and a low level of this signal and an inverted signal of the signal. By performing a count-up from a value and a count-down to a predetermined value or a count-down from a predetermined value and a count-up to a predetermined value with different clocks, a signal that is inverted at an intermediate point between adjacent zero-cross points is obtained from the count results. By generating a drive current switching timing signal delayed by a predetermined electrical angle irrespective of the rotation speed from this signal, the motor drive circuit can be digitized to facilitate integration and reduce variations in characteristics. .

G. Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

G _1. Configuration of Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
This embodiment is an example in which the present invention is applied to a brushless motor having a three-phase magnetic circuit configuration. In the configuration of the present embodiment, L _U , L
_V and _LW are three-phase stator-side motor coils star-connected, and are connected to a drive current switching circuit 15 described later. 1, 2 and 3 of each phase coil L _U, L _V, counter-electromotive voltage E _U generated in L _W, E _V, the E _W, their respective and common potential (COM)
And a comparator for converting the signals into signals d, e, and f that are inverted at the zero cross point for each phase. These signals
d, e, f are input to the exclusive OR (EXOR) circuit 4, KakugyakuOkoshi voltage E _U, E _V, the signal g is generated to reverse at the zero cross point of the E _W.

An inverter 5 inverts the signal g.
Is a delay circuit configured with an up / down counter and digitally delaying either the rising or falling of the input signal by 30 electrical degrees. The signal g is a U / D instructing the up / down count of the delay circuit 6.
The signal -g, which is connected to the terminal and inverted by the inverter 5, is connected to the U / D terminal of the delay circuit 7. Reference numeral 8 denotes an oscillator for generating a clock signal, and 9 denotes a half of the clock signal.
This is a 1/2 frequency divider that generates a clock signal having a frequency of 1/2 by dividing the frequency (hereinafter, referred to as a 1/2 clock signal). The 1/2 clock signal is used as a first clock signal, and the clock signal of the oscillator 8 is used as a second clock signal.
Clock terminal and 1/2 clock terminal. The signals j and k delayed by the delay circuits 6 and 7 are sent out from a zero output (Zero) terminal, respectively connected to the input of the OR circuit 10, and the logical sum of the signals j and k is obtained. counter-electromotive voltage E _U, E _V, signal l which changes at a point which is delayed by an electrical angle of 30 degrees is made from the zero crossing point of E _W.

11, 12, and 13 connect output signals d, e, and f of comparators 1, 2, and 3 to data input (D) terminals, respectively, and output clocks (CK)
This is a D flip-flop that connects the signal 1 to a terminal and creates timing signals a, b, and c for switching the drive current of each phase. 14 is each D flip-flop 11, 12,
13 timing signals a, b,
c, the signals p, q, r, s, which drive the bases of the transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ constituting the drive current switching circuit 15
This is a 120-degree logic circuit that creates t and u. Drive current switching circuit 15, which is connected to the servo power supply V _S emitters in common
The pnp transistors Q ₁ , Q ₂ , Q ₃ and the npn transistors Q ₄ , Q ₅ , Q ₆ whose emitters are commonly connected to the ground are Q ₁ , Q ₄
The collectors are connected by a pair of Q ₂ , Q ₅ and Q ₃ , Q ₆ , and the above-mentioned motor coils L _U , L _V , L _W are connected to respective connection points.

FIG. 2 is a circuit configuration diagram of a delay circuit which is a main part of the present embodiment. Since both delay circuits 6 and 7 in FIG. The configuration is shown. 6a is an 8-bit up / down counter, which counts a clock signal input to the clock (CK) terminal in response to an instruction input of one of an up (UP) terminal and a down (DOWN) terminal, and carries a signal or a count value of zero. Is output from the carry output (-Carry) terminal or the zero output (-Zero) terminal. 1 / 2clo is connected to the CK terminal of the counter 6a.
The input to the ck terminal and the input to the clock input terminal are NAND (NAN
D) Gates 6b, 6c and negative logic input OR (OR) gate (however,
This is a select circuit composed of 6d (which has the same circuit configuration as that of the NAND gate). For this switching, the U / D terminal is connected to the gate input of the NAND gate 6b on the 1/2 clock terminal input side, and the NAND gate 6c on the clock terminal input side
The U / D terminal is connected to the gate input of the inverter via a signal inverting inverter 6e. On the other hand, the U / D terminal is connected to the UP terminal of the counter 6a via an AND (AND) gate 6f, and the U / D terminal is connected to the inverter 6g and the AND (AND) gate 6h to the DOWN terminal of the counter 6a. Connected via. A
The gate input of the ND gate 6f is the negative input OR (OR) gate 6.
The output of the RS flip-flop consisting of i, 6j is connected.
The setting of the RS flip-flop is performed by the low level input of the U / D terminal, and the reset is performed by the carry signal from the up / down counter 6a. Thus, when the U / D terminal is at a high level, the counter 6a performs an up-count operation up to a full count by a clock signal. However, usually, the frequency of the clock signal is set so that the operation proceeds from the up-counting operation to the next down-counting operation before the full count is reached. Further, the -Zero terminal of the counter 6a is connected to the gate input of the other AND gate 6h,
As a result, the low level input of the U / D terminal
Performs a down-count from a count value in the up-count operation to a count value of zero with a 1/2 clock signal.

FIG. 3 shows the 8-bit up / down counter of FIG.
FIG. 6b is a circuit configuration diagram of 6a. The up / down counter 6a is composed of eight JK flip-flops provided for each bit.
61a to 61h, and AND gates 62a to 62g and AND gates for each JK input of each JK flip-flop 61b to 61h
OR gates for 63a-63g and their respective outputs
A UP / DOWN switching circuit composed of 64a to 64g, a NAND (NAND) gate 65 for outputting a count value zero signal to the -Zero terminal, and a NAND (NAND) gate 66 for outputting a carry signal to the -Carry terminal Consisting of The clock (CK) terminal of the counter 6a is the clock (CK) of each JK flip-flop.
The UP terminal is connected as a gate input of the AND gates 63a to 63g, and the DOWN terminal is connected as a gate input of the AND gates 62a to 62g.

FIG. 4 is a circuit configuration diagram of the three-input exclusive OR circuit 4 of FIG. The exclusive OR circuit 4 has a two-input exclusive OR gate 41 and another two-input exclusive OR gate 42 connected to one of the two inputs. Two inputs of the exclusive OR gate 42 and the other input of the exclusive OR gate 41 are the signals d, e, f of the exclusive OR circuit 4.
And the output of the exclusive OR gate 41 is the signal g of the exclusive OR circuit 4.
Output terminal.

FIG. 5 is a circuit configuration diagram of the 120-degree logic circuit 14 of FIG. This 120-degree logic circuit 14 has a motor coil L
_In order to energize _U , L _V , and L _W in both directions of three phases, an electrical angle 120 degrees delayed from the zero cross point of the back electromotive voltage of each phase by an electrical angle of 120 degrees
Drive current switching circuit 1 in response to timing signals a, b, c
Signal p to be input to the bases of the transistors Q ₁ to Q ₆ of 5, q,
Create r, s, t, u. In the configuration of the 120-degree logic circuit 14, 14a, 14b, and 14c are inverters and timing signals a and
b and c are input respectively to generate inverted signals -a, -b and -c. Reference numerals 14d, 14e, and 14f denote 2-input NAND gates, which output a signal p from a logical product-(a · (−b)), a signal q from a logical product − (b · (−c)), Product-(c
A signal r is created from (−a)). Reference numerals 14g, 14h, and 14i denote AND gates, which output the signal s from the logical product (−c) · a, the signal t from the logical product (−b) · c, and the logical product (−
a) Generate a signal u from b.

G _2. Operation and Function of Embodiment The operation and function of the embodiment configured as described above will be described.

FIG. 6 is a timing chart showing the operation of this embodiment.
First, the motor coil L _U, L _V, L _W to produce back electromotive voltage E _U, E _V, E _W
Are input to the comparators 1, 2, and 3, and are converted into signals d, e, and f that are inverted at the zero-cross point. Each motor coil L _U ,
L _V and L _W are provided by a 120-degree logic circuit 14 having timing signals a, b and c as inputs and a drive current switching circuit 15 including transistors Q _{1 to} Q ₆ whose on / off is controlled by the output thereof. Although the drive current flows at a certain timing after receiving the power supply from the servo power supply V _{S, the} current is not supplied near the zero cross point, so that a signal that is accurately inverted at the zero cross point of the reverse voltage is obtained. In order to efficiently rotate a rotor-side magnet (not shown), it is necessary to supply a drive current to a portion having a large amount of magnetic flux, that is, a portion having a high back electromotive voltage. FIG. 6 shows a case in which three-phase bidirectional 120-degree (electric angle) energization is performed. In this case, it is necessary to supply a drive current in a 120-degree width section delayed by 30 degrees in electric angle from the zero-cross point. Timing signals a, b, and c that are delayed by 30 electrical degrees from the zero-cross point are required.

Therefore, first, signals d, e, and f, which are inverted at the zero crossing points of the back electromotive voltages E _U , E _V , and E _W of each phase, are input to the exclusive OR circuit 4, and the respective back electromotive voltages E _U , E _V , A signal g inverted at the zero cross point of E _W is obtained. This signal g is digitally expressed as an electrical angle.
The signal is input to the U / D terminal of the delay circuit 6 that delays by 30 degrees, and the inverted signal −g is input to the U / D terminal of another delay circuit 7. In the delay circuits 6 and 7, when the signal g or -g is at a high level (hereinafter, referred to as H), the count is incremented based on the 1/2 clock signal, and subsequently, the signal g or -g is at a low level (hereinafter, L). ), The countdown is performed based on the clock signal input from the clock terminal from the count value counted up above, and the count is stopped when the count reaches zero. In the above, the 1/2 clock signal is obtained by dividing the clock signal by 1/2, so that the countdown operation is performed at twice the frequency of the countup operation. I will return. That is, the count value zero signal output j, k of each of the delay circuits 6, 7 (goes to H when the count value is zero).
Becomes H after a half of the time required for the count-up has elapsed after the count-up. Here, the interval from the adjacent zero-cross point, that is, the zero-cross point of the back electromotive voltage of a certain phase to the zero-cross point of another phase is an electrical angle in the case of three phases.
Since the angle is 60 degrees, one inversion side of the signals g and -g can be delayed by 30 degrees by the signals j and k.

When the logical sum of such signals j and k is obtained by the OR circuit 10,
The logical sum output l is a signal that varies at a point delayed 30 electrical degrees from the zero cross point of KakugyakuOkoshi voltage _{E U, E V, E W} . This signal 1 is supplied to the clocks (CK) of the D flip-flops 11, 12, and 13.
When applied to the terminals, the signals d, e, and f, which change at the zero-cross point for each phase, are held with an electrical angle delay of 30 degrees. , b, c can be obtained. The timing signals a, b, and c are converted by the 120-degree logic circuit 14 into drive current switching signals, that is, the transistors Q ₁ , Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₆ Are converted into control signals p, q, r, s, t, u to be inputted to the base of the
The drive current supplied to the motor coils L _U , L _V , and L _W by receiving power supply from the servo power supply V _S via the switch is switched. Although the spinning rotor by the driving current, the rotation speed of the control servo system (not shown), for example, detects the rotational speed from the signals g, a feedback control so that the target speed by increasing or decreasing the servo power V _S It is done by that.

As described above, the present embodiment uses an up-down counter as a means for generating a signal delayed by 30 electrical degrees from the zero-cross point of the back electromotive voltage of each phase, and is realized by a digital circuit. There are features. Therefore, when compared with the case of realizing by analog means such as an integrator,
The delay of 30 degrees is no longer affected by variations in circuit elements, and variations in characteristics are reduced. In addition, since it is composed only of a digital circuit, integration becomes easy, and when integrated, external parts such as a capacitor are unnecessary, so that the number of parts is reduced, and the circuit can be downsized. Also, when the speed of the brushless motor changes, only the count value at the time of counting up changes, and the time ratio of returning to zero at the time of counting up and counting down does not change to 2: 1, so that it is always exactly 30 degrees. A delayed timing signal is obtained, and it is possible to cope with a variable speed without adjustment.

In the up / down counter 6a of the above-described embodiment, the count was first performed, and then the countdown was performed.However, the countdown was first performed by the 1/2 clock signal, and then the count was performed until the clock signal returned to zero. It is clear that the same result can be obtained by performing the above. In addition, in the countdown or countup performed continuously based on the clock signal, if an offset is provided in the zero detection, the delay angle can be reduced for a fixed time, and the current delay due to the inductance component of the motor coil can be easily corrected. Can be done. Further, in the above embodiment, a three-phase two-way brushless motor is taken as an example. However, the present invention can be applied to other types of brushless motors such as a four-phase motor. As described above, the present invention can be variously applied according to the gist and can take various embodiments.

H. Effects of the Invention As is clear from the above description, according to the drive circuit of the brushless motor of the present invention, the timing signal for switching the motor coil current delayed by a predetermined electrical angle is digitally generated. External components such as capacitors are eliminated, so that integration is facilitated, variations in characteristics are reduced, and current delay correction due to the inductance component of the motor coil is facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a delay circuit which is a main part of the above embodiment, FIG. 3 is a circuit configuration diagram of an up / down counter of the delay circuit,
FIG. 4 is a circuit diagram of the exclusive OR circuit of the above embodiment, FIG. 5 is a circuit diagram of a 120-degree logic circuit of the above embodiment, and FIG. 6 is a timing chart showing the operation of the above embodiment. 1,2,3 ... Comparator, 4 ... Exclusive OR circuit, 5 ... Inverter, 6,7 ... Delay circuit, 6a ... Up / down counter, 8 ... Oscillator, 9 ... 1/2 frequency divider , 10 ... OR circuit, 11, 12, 13 ... D flip-flop, 14 ... 120 degree logic circuit, 15 ... drive current switching circuit, L _U , L _V , L _W ... motor coil, E _U , E _V , E _W …… Back electromotive voltage.

Claims (1)

(57) [Claims] In a brushless motor driving circuit for rotating a rotor by switching a current flowing through a plurality of motor coils on a stator side by a predetermined timing signal, the current is reversed at a zero cross point of a back electromotive voltage generated in each motor coil. Means for detecting a signal, means for generating a first timekeeping signal and a second timekeeping signal having a higher frequency than the first timekeeping signal, The up-counting is performed from one predetermined value to another predetermined value by the timed signal of 1, and the down-counting is performed by the second timed signal from the another predetermined value to the certain predetermined value in the section of the other signal level state. Or the first timed signal counts down at a certain point in the section of one signal level state of the signal inverted at the zero crossing point. A first up / down counter that performs from the value to another predetermined value and then performs an up-count with the second clock signal from the another predetermined value to the certain predetermined value in the other signal level state section; First, in the section of one signal level state of the signal obtained by inverting the signal inverted at the zero crossing point, the first clock signal first counts up from one predetermined value to another predetermined value, and then the other signal level In the state section, the second clock signal is used to count down from the another predetermined value to the certain predetermined value, or the signal level of one of the signals obtained by inverting the signal inverted at the zero-cross point. At the beginning of the section, the down-counting is performed from one predetermined value to another predetermined value by the first clock signal, and then the up-counting is performed by the second clock signal during the other signal level state. A second up / down counter for performing a return from another predetermined value to the certain predetermined value; a time point when the first up / down counter returns to the certain predetermined value as a count result; Means for generating a timing signal for switching a current flowing through the plurality of motor coils on the stator side from a point in time when the counter returns to the certain predetermined value as a count result of the counter.