JP3122108B2 - Video signal encoding method and apparatus therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial application field B Outline of the invention C Conventional technology (FIGS. 9 to 11) D Problems to be solved by the invention (FIG. 10) E Means for solving the problems (FIG. 1 and FIG. 8) F function (FIGS. 1 and 8) G embodiment (G1) Overall configuration of image information transmission system (FIGS. 1 to 5) (G2) Inter-frame / intra-frame coding control (1st embodiment) Figure,
(FIGS. 6 and 7) (G3) Forced refresh processing according to the embodiment (FIG. 1, FIG.
(FIGS. 3 and 8) (G4) Other Embodiments H Effect of the Invention A Industrial Field of the Invention The present invention relates to a video signal encoding method and apparatus, and in particular, to a video signal encoding system which encodes a video signal with high efficiency. This is suitable for application when performing conversion processing.

B. Summary of the Invention In the video signal encoding method and apparatus, the present invention partially generates a block for forcibly performing intra-frame encoding processing for each frame by using a random number at random. An unsightly change in image quality can be visually suppressed.

C Conventional Techniques Conventionally, in videophone systems and conference telephone systems, relatively strict restrictions have been placed on transmission capacity by efficiently encoding video signals consisting of moving images into intra-frame encoded data and inter-frame encoded data. A video signal transmission system for transmitting a moving image video signal through a certain transmission filter has been proposed (JP-A-63-1183).

That is, for example, as shown in FIG.
_{= T 1, t 2, t} 3 each image PC1 constituting the video at ......, P
When transmitting C2, PC3, etc., the transmission efficiency is improved by compressing the image data to be transmitted using the point that the video signal has a characteristic that the autocorrelation is large as time passes. The intra-frame encoding process performs a compression process on the images PC1, PC2, PC3,..., For example, by comparing pixel data with a predetermined reference value to obtain a difference. , PC2, PC3,... Are transmitted using compressed autocorrelation between pixel data in the same frame.

In addition, the inter-frame encoding process obtains image data PC12, PC23,..., Which are differences of pixel data between adjacent images PC1, PC2, PC2, PC3,. This for the initial image PC1 at the time t = t ₁ transmitting with intraframe coded processed image data.

Thus, the images PC1, PC2, PC3,... Can be highly efficiently coded into digital data having a significantly smaller data amount than when all the image data is transmitted, and transmitted to the transmission path.

Such a video signal encoding process is executed in the image data generating apparatus 1 having the configuration shown in FIG.

The image data generator 1 processes the input video signal VD in the pre-processing circuit 2 to perform one-field dropping processing and one-field line thinning processing, and then converts the luminance signal and the chroma signal into 16 pixels (in the horizontal direction). The data is converted into transmission unit block data (referred to as macroblock) data S11 composed of data of × 16 pixels (in the vertical direction) and supplied to the image data encoding circuit 3.

The image data encoding circuit 3 receives the predicted current frame data S12 formed in the prediction encoding circuit 4 and calculates the difference from the macroblock data S11 to generate inter-frame encoded data (this is inter-frame encoded data). (Referred to as an encoding mode) or the difference between the macroblock data S11 and the reference value data to form intra-frame encoded data, which is supplied to the transform encoding circuit 5 as difference data S13.

The transform coding circuit 5 is composed of a discrete cosine transform circuit. The transform coding data S14 obtained by performing high-efficiency coding by orthogonally transforming the difference data S13 is supplied to the quantizing circuit 6 so as to obtain quantized image data. Send S15.

Thus, the quantized image data obtained from the quantization circuit 6
S15 is again subjected to high-efficiency encoding processing in the re-transform encoding circuit 7 including the variable-length encoding circuit, and then supplied to the transmission buffer memory 8 as transmission image data S16.

In addition, the quantized image data S15 is subjected to inverse quantization and inverse transform coding in the predictive coding circuit 4 to be decoded into differential data, and then to correct the unpredicted frame data using the differential data. Thus, new pre-prediction frame data is stored, and prediction is performed by motion-compensating the pre-prediction frame data stored in the prediction encoding circuit 4 with motion detection data formed based on the macroblock data S11. The current frame data can be formed and supplied to the image data encoding circuit 3, whereby the difference between the macroblock data S11 of the frame to be currently transmitted (that is, the current frame) and the predicted current frame data S12 is calculated as difference data. It is made to get as S13.

10 in the configuration of Figure, when transmitting the moving image as described above for FIG. 9, when the first image data of the image PC1 at the time t ₁ of FIG. 9 (A) is given as a macro Bro poke data S11, the image data The encoding circuit 3 enters the intra-frame encoding mode and supplies it to the transform encoding circuit 5 as differential data S13 subjected to intra-frame encoding processing, thereby passing through the quantization circuit 6 and the re-transform encoding circuit 7. Then, the transmission image data S16 is supplied to the transmission buffer memory 8.

At the same time, the quantized image data S15 obtained at the output terminal of the quantizing circuit 6 is subjected to predictive encoding processing in the predictive encoding circuit 4, whereby the unpredicted frame representing the transmitted image data S16 transmitted to the transmission buffer memory 8 is transmitted. data is held before the frame memory, when the macro Bro poke data S11 representing an image PC2 Subsequently at time t ₂ is supplied to the image data coding circuit 3, the predicted current frame data S12
And supplied to the image data encoding circuit 3.

Thus the image data coding circuit 3 at time t = t ₂
Supplies the differential data S13 subjected to the inter-frame encoding processing to the transform encoding circuit 5, whereby differential data representing a change in the image between the frames is supplied to the transmission buffer memory 8 as transmission image data S16, and When the quantized image data S15 is supplied to the prediction encoding circuit 4, the prediction encoding circuit 4 forms and stores the pre-prediction frame data.

By repeating the same operation thereafter, while the image data encoding circuit 3 executes the inter-frame encoding process, only the difference data representing the change of the image between the previous frame and the current frame is transmitted to the transmission buffer memory 8. Will be sequentially transmitted.

The transmission buffer memory 8 stores the transmission image data S16 sent out in this manner, and sequentially stores the stored transmission image data S16 at a predetermined data transmission speed determined by the transmission capacity of the transmission line 9 as transmission data D _TRANS. And transmit it to the transmission line 9.

At the same time, the transmission buffer memory 8 detects the amount of remaining data, feeds back the remaining data S17 that changes according to the remaining data amount to the quantization circuit 6, and performs quantization step size according to the remaining data S17. By adjusting the amount of data generated as the transmission image data S16, the transmission buffer memory 8 can maintain a proper amount of data (a data amount that does not cause overflow or underflow) in the transmission buffer memory 8. It has been done.

When the remaining amount of data in the transmission buffer memory 8 has increased to the allowable upper limit, the quantization step STPS (FIG. 11) of the quantization circuit 6 is increased by the remaining amount data S17. The amount of transmission image data S16 is reduced by causing the quantization circuit 6 to perform coarse quantization.

Conversely, when the remaining amount of data in the transmission buffer memory 8 has decreased to the allowable lower limit, the remaining amount data S17 controls the quantization step STPS of the quantization circuit 6 so that the step size becomes smaller. Thus, the amount of data generation of the transmission image data S16 is increased by causing the quantization circuit 6 to execute fine quantization.

D. Problems to be Solved by the Invention As described above, the conventional image data generating apparatus 1 _achieves the highest efficiency while matching the data transmission speed of the transmission data D _{TRANS to} the transmission condition limited based on the transmission capacity of the transmission line 9. A transmission buffer memory 8 is provided as means for transmitting significant image information, and quantization is performed according to the remaining data amount of the transmission buffer memory 8 so that the remaining data amount of the transmission buffer memory 8 does not always overflow or underflow. The quantization step size of the circuit 6 is controlled. However, if the quantization step size is not changed, the image quality of the transmission data D _TRANS becomes obstructive when the frame data before prediction stored in the prediction encoding circuit 4 is forcibly refreshed. There is a possibility that it will change.

In the forced refresh process, once image data that has been subjected to intra-frame encoding processing is transmitted as transmission data D _TRANS , if image data that has undergone inter-frame encoding processing is continuously transmitted over a long period of time based on this, during this period, In order to prevent a situation in which the image quality of a decoded image is deteriorated and cannot be recovered on the receiving side when a transmission error occurs even for one bit, the image data encoding circuit 3 is provided at predetermined intervals. By forcibly switching the mode to the intra-frame encoding mode, the intra-frame encoded data serving as a reference for decoding image data on the receiving side is transmitted data D.
_{In addition} to transmitting as _TRANS , the pre-prediction frame data stored in the prediction encoding circuit 4 is refreshed (this operation is called a forced refresh mode) (Japanese Patent Laid-Open No. 61-131986).

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and proposes a video signal encoding method and a video signal encoding method capable of executing forced refresh processing while visually suppressing unsightly changes in image quality. It is.

E. Means for Solving the Problem In order to solve the problem, according to the present invention, an image of one frame constituted by the video signal VD _IN is divided into a predetermined number of blocks each having a predetermined number of pixels, and the divided image is divided. In the video signal encoding method for converting the video signal VD _IN into the transmission image data S14 by selecting the intra-frame encoding process or the inter-frame encoding process for each block comprising Block video data S25
And the motion vector of the pre-prediction frame is detected, motion compensation for the motion vector is performed on the pre-prediction frame, the predicted current frame data S24 is output, and video data S25 of a predetermined number of blocks are output. Data S24
And a predetermined number of blocks of video data S25 are input to output operation data S31 for calculating the weight between the predicted current frame data S24 and the predetermined number of blocks of video data S25, and an intra-frame encoding mode. In the case of the inter-frame encoding processing mode, the output data S26 between the video data S25 and the predicted current frame data S24 is output S. Based on the operation data S31, the video data S25 of a predetermined number of blocks are output. Calculates the weight of the difference data from the predicted current frame data S24, selects either the intra-frame coding mode or the inter-frame coding mode based on the calculated value, and sets a counter value indicating the refresh order in each block. And the counter value is incremented each time the encoding process is performed for each block, so that the counter value becomes a predetermined value. When there was summer, and selects an encoding processing mode as video data S25 in the block are processed in the intraframe coding processing mode, it clears the counter value.

F function By randomly selecting a block MB to be intra-frame coded by using a random number for each frame FRM, the block MB to be intra-frame coded is selected.
Can be visually impaired, whereby the unsightly change in image quality that occurs partially can be made inconspicuous.

G Example Hereinafter, an example in which the present invention is applied to a videophone will be described in detail with reference to the drawings.

(G1) Overall Configuration of Image Information Transmission System In FIGS. 1 and 2, the image information transmission system 21 is composed of an encoder 21A and a decoder 21B, and the encoder 21A converts an input video signal VD _IN into an input circuit unit 22. After the pre-processing, the analog / digital conversion circuit 23 sends the transmission unit block data composed of pixel data of 16 × 16 pixels, that is, the input image data S21 composed of the pixel data of the macroblock MB, to the pixel data processing system SYM1, At each processing stage of the pixel data processing system SYM1, processing information data corresponding to the data to be processed is sequentially transmitted via the header data processing system SYM2 at a timing when the pixel data is processed in units of macroblocks MB. Thus, the pixel data and the header data are respectively transferred to the pixel data processing system SYM1 and the header data. Processing is performed in the data processing system SYM2 according to the pipeline method.

In the case of this embodiment, the macroblock data sequentially transmitted as the input image data S21 is extracted from the frame image data FRM by a method as shown in FIG.

The first input video signal VD _IN is QCIF image size (176 x 144
Pixels), one frame image data FRM
Is divided into two (in the horizontal direction) × 3 (in the vertical direction) block groups GOB as shown in FIG. 3 (A1), and each block group GOB is divided into 11 as shown in FIG. 3 (B). (Horizontally) x 3 (vertically) macroblocks
Each macro block MB includes luminance signal data Y ₀₀ for 16 × 16 pixels as shown in FIG. 3 (C).
To Y ₁₁ comprising a color signal data C _b and C _r consisting of the color signal data corresponding to all the pixel data of the (each 8 × consisting of 8 pixels of the luminance signal data) and the luminance signal data Y ₀₀ to Y ₁₁ .

On the other hand, when the input video signal VD _IN has a CIF image size (252 × 288 pixels), two pieces of frame image data FRM (horizontal direction) as shown in FIG. ) × 6 (in the vertical direction) block groups GOB, and each block group GOB is composed of 11 (in the horizontal direction) × 3 (in the vertical direction) macros as shown in FIG. 3 (B). Each macro block MB is made to include a block MB.
As shown in FIG. 3C, all of the luminance signal data Y _{00 to} Y ₁₁ (each composed of 8 × 8 pixel luminance signal data) and the luminance signal data Y _{00 to} Y ₁₁ for 16 × 16 pixels are used. It comprises color signal data _Cb and _Cr composed of color signal data corresponding to pixel data.

Thus, the input image data S21 transmitted for each macroblock MB is given to the motion compensation circuit 25,
5 is a motion detection control signal given from a motion compensation control unit 26 provided for the header data processing system SYM2.
In response to S22, the pre-prediction frame data S23 of the pre-prediction frame memory 27 is compared with the input image data S21 to detect the motion vector data MVD (x) and MVD (y), and to the motion compensation control unit 26 for the first. Is supplied as data of the header data HD1 (FIG. 4), and the motion compensation circuit body 25A performs motion compensation for the motion vector data MVD (x) and MVD (y) on the frame data S23 before prediction. The current frame data S24 is formed and supplied to the image data encoding circuit 28 together with the current frame data S25 composed of the input image data S21 to be currently processed.

Here, as shown in FIG. 4, the motion compensation control unit 26 includes, for each macroblock currently being processed as the first header data HD1, the transmission frame number data TR Counter indicating the transmission order of the frame image data FRM, Block group number data GOB address representing the block group GOB (FIGS. 3 (A1) and (A2)) and macro block number data MBa representing the macro block MB among them.
pixel data processing system by adding ddress
The macroblock MB transmitted to each processing stage of the SYM1 is displayed, and the flag data FL indicating the processing or processing format of the macroblock MB to be processed is displayed.
AGS and motion vector data MVD of the macro block MB
(X) and MVD (y) and difference data Σ | A−B | representing the evaluation value.

The flag data FLAGS has a maximum of 1 as shown in FIG.
A flag for a word (16 bits) can be set, and a motion compensation control flag MC on / off indicating whether or not the processing target macroblock MB should be processed in the motion compensation mode is set in the 0th bit. You.

The first bit of the flag data FLAGS contains an interframe / intraframe indicating whether the processing target macroblock MB should be processed in the interframe coding mode or the intraframe coding mode. Flag Inter /
Intra is set.

In the second bit of the flag data FLAGS, a filter flag Filter on / off indicating whether or not to use the loop filter 25B of the motion compensation circuit 25 is set.

The third bit of the flag data FLAGS also blow included in the process target macroblock poke data Y ₀₀ -C _r
A transmission flag Coded / Not-coded indicating whether or not (FIG. 3 (C)) should be transmitted can be set.

In the fourth bit of the flag data FLAGS, a drop frame flag indicating whether or not the target macroblock MB is dropped can be set.

Further, in the fifth bit of the flag data FLAGS, a forced refresh flag Refresh on / off indicating whether or not to perform a forced refresh of the macroblock MB to be processed can be set.

Further, a macro block power evaluation flag MBP appreciate can be set in the sixth bit of the flag data FLAGS.

The difference data Σ | A−B | is the difference between the macroblock data A to be currently processed in the current frame data S25 and the macroblock data B compensated by the motion vector for detection in the frame data S23 before prediction. , Which can be used to evaluate the detected motion vector.

The image data encoding circuit 28 outputs the current frame data S2 given from the motion compensation circuit 25 in the intra-frame encoding mode.
5 is supplied as it is to the transform coding circuit 29 as difference data S26, and in contrast, in the inter-frame coding mode, the pixel data of the current frame data S25 and the predicted current frame data S
The difference data S 26, which is a difference from the 24 pixel data, is supplied to the transform encoding circuit 29.

The image data encoding circuit 28 is included in the header data processing system SYM2.
An inter-frame / intra-frame encoding control unit 30 is provided so as to correspond to the image data. Based on the header data HD1 supplied from the motion compensation control unit 26 and the arithmetic data S31 supplied from the image data encoding circuit 28, the An inter / intra flag Inter / Intra (FIG. 5) for designating the encoding mode of the encoding circuit 28 and a filter flag Filter on / off (FIG. 5) for controlling the operation of the loop filter 25B of the motion compensation circuit 25. 5) is calculated and sent to the filter control unit 31 as second header data HD2.

As shown in FIG. 4, the second header data HD2 is composed of the transmission frame number data TR Co constituting the header data HD1.
The power data necessary for the filter control unit 31 to form the inter-frame / intra-frame coding mode switching signal S33 and the filter on / off signal S34 while taking over the unter ~ difference data {| A-B |
(A) ² (L) and Σ (A) ² (H), Σ (AB) ²
(L) and Σ (AB) ² (H), Σ (A-FB)
² (L) and Σ (A-FB) ² (H), Σ (A) are added in the inter-frame / intra-frame coding control unit 30.

Here, the power data Σ (A) ² (L) and Σ (A)
² (H) indicates the lower bit and the upper bit of the square sum of the macroblock pixel data A of the current frame data S25,
Power data Σ (AB) ² (L) and Σ (AB) ²
(H) shows the lower bits of the sum of squares of the difference AB between the macroblock pixel data A of the current frame data S25 and the macroblock pixel data B of the predicted current frame data S24 formed without passing through the loop filter 25B; Represents the high-order bits and represents power data Σ (A-FB) ² (L) and Σ (AF)
B) ² (H) is the macroblock pixel data A of the current frame data S25 and the macroblock pixel data FB of the predicted current frame data S24 formed via the loop filter 25B.
The power data 及 び (A) represents the sum of the macroblock pixel data A of the current frame data S25, and the size of the data to be processed is evaluated. Therefore, the data amount is expressed as a power value (the sum of squares is obtained as a value irrelevant to the sign).

The filter control unit 31 receives the second header data passed from the inter-frame / intra-frame coding control unit 30.
On the basis of HD2 and the remaining amount data S32 supplied from the transmission buffer memory 32, an inter-frame / intra-frame encoding mode switching signal S33 is sent to the image data encoding circuit 28, and the loop filter 25B is sent to the loop filter 25B. A filter on / off signal S34 is transmitted, and a filter flag Filter on / o indicating the content of the filter on / off signal S34 is provided.
ff is added to the second header data HD2 and passed to the threshold control unit 35 as the third header data HD3.

Here, the filter control unit 31 first activates the image data encoding circuit 28 when the amount of transmission data in the case of performing inter-frame encoding processing is larger than the amount of transmission data in the case of performing intra-frame encoding processing. Control to intra-frame encoding mode.

Secondly, the filter control unit 31 is configured such that in the state where the processing is performed in the inter-frame coding mode, the predicted current frame data S24 that has not undergone the processing is better than the predicted current frame data S24 that has been processed in the loop filter 25B. If the difference value is small, the filter on / off signal S34
The loop filter 25B is controlled so as not to perform the filtering operation.

Third, when the filter control unit 31 enters the forced refresh mode, the filter control unit 31 outputs the image data encoding circuit 28 by the inter-frame / intra-frame encoding mode switching signal S33.
To the intra-frame encoding mode.

Fourth, when the transmission buffer memory 32 has a possibility of overflowing based on the remaining amount data S32 supplied from the transmission buffer memory 32, the filter control unit 31 should detect this and perform frame drop processing. Third header data comprising a flag for instructing
HD3 is sent to the threshold control unit 35.

Thus, the image data encoding circuit 28
The difference data S26 encoded in a mode that minimizes the difference between S25 and the predicted current frame data S24 is supplied to the transform encoding circuit 29.

As shown in FIG. 4, the third header data HD3 is obtained from the transmission frame number data TR Counter from the header data HD2.
Together take over the ~ motion vector data MVD (x) and MVD (y), the filter flag Fil of 6 bits fraction in the filter control Yunitsuto 31 corresponding to Bro poke data Y ₀₀ -C _r
ter on / off is added.

Transform coding circuit 29 is made of a discrete cosine transform circuit, block the coefficient value after the discrete cosine transform of the six _{Y 00, Y 01, Y 10} , Y 11, C b, and a zigzag-scan for each C _r It is transmitted to the transmission block setting circuit 34 as transformed encoded data S35.

Transmission block setting circuit 34 six Bro poke is coming sent as converted coded data S35 data Y ₀₀ -C _r (3
(C)), from the first coefficient data to n
The sum of the squares is calculated, and the result of the calculation is passed to the threshold control unit 35 as power detection data S36.

At this time Sureshiyorudo control Yunitsuto 35 compares the power detection data S36 to a predetermined Sureshiyorudo each blow poke data Y ₀₀ -C _r, do not allow transmission of the blow stick data when power detection data S36 is smaller than the Sureshiyorudo, which The transmission permission / prohibition data CBPN of 6 bits indicating that the transmission is permitted when it is large is added to the third header data HD3 passed from the filter control unit 31, and the quantization control is performed as the fourth header data HD4. together passed to Yunitsuto 36, thereby delivering the blow poke data Y ₀₀ -C _r corresponding from the transmission block setting circuit 34 as transmission Bro poke patterned data S37 to the quantizer 37.

Here, the fourth header data HD4 is the transmission frame number data TR Coun of the header data HD3 as shown in FIG.
ter ~ Inherit the filter flag Filter on / off as it is, and block the threshold control unit 35.
Y ₀₀ -C _r the transmission availability flag CBPN of 6 bits fraction was generated corresponding is added.

Quantization control unit 36 is threshold control unit 35
A quantization step size control signal S38 is supplied to the quantization circuit 37 based on the fourth header data HD4 passed from the controller and the remaining amount data S32 sent from the transmission buffer memory 32, and thereby the quantization circuit 37 is macroblocked. The quantization processing is performed with a quantization step size adapted to the data included in the MB, and as a result, the quantized image data S39 obtained at the output terminal of the quantization circuit 37 is supplied to the variable length coding circuit.

At the same time, as shown in FIG. 4, the quantization control unit 36 converts the fifth header data HD5 into the header data HD4.
Bro poke data Y ₀₀ -C _r (FIG. 3 (C)) to the corresponding flag data FLAGS and the motion vector data MVD (x) and MVD (y) in this separated were arranged in series data on the basis of the Is formed and passed to the variable length coding circuit 38 and the inverse quantization circuit 40.

Here, the header data HD5 is, as shown in FIG.
Transmission frame number data TR Coun of the header data HD4
ter~ macroblock number as with taking over the data MB address, a quantization size data QNT in the quantization control Yunitsuto 36, Bro poke data Y ₀₀ -C flag data FLAGS for _r, the motion vector data MVD (x) and MV
D (y) is added.

The variable-length encoding circuit 38 subjects the header data HD5 and the quantized image data S39 to variable-length encoding and performs transmission image data S40.
And supplies it to the transmission buffer memory 32.

Variable-length coding circuit 38 during the variable-length coding the blow poke data Y ₀₀ -C _r, the corresponding flag data "frame dropping" on the basis of the FLAGS, or when the "not sent" is specified, the block The data is discarded without being transmitted as the transmission image data S40.

The transmission buffer memory 32 stores the transmission image data S40, reads out the transmission image data S40 at a predetermined transmission speed, combines the transmission image data S40 with the transmission audio data S41 transmitted from the audio data generator 42 in the multiplexer 41, and transmits the resultant data to the transmission line 43.

The inverse quantization circuit 40 inversely quantizes the quantized image data S39 sent from the quantization circuit 37 based on the header data HD5, and then supplies the inversely quantized data S42 to the inverse transform encoding circuit 43 to perform inverse quantization. After being converted into the converted coded data S43, it is supplied to the decoder circuit 44, and thus the coded difference data S44 representing the image information transmitted as the transmission image data S40 is supplied to the pre-prediction frame memory 27.

At this time, the pre-prediction frame memory 27 uses the coded difference data S44 to correct the pre-prediction frame data stored up to that time, and stores it as new pre-prediction frame data.

Thus, according to the encoder 21A having the configuration shown in FIG. 1, pixel data is pipelined in macroblock units in the pixel data processing system SYM1 based on the header information supplied from the header data processing system SYM2. By passing the header data in the header data processing system SYM2 so as to synchronize with this, the pixel data is added or deleted as necessary by adding or deleting the header data as necessary in each processing stage of the header data processing system SYM2. Adaptive processing is possible.

As shown in FIG. 2, the decoder 21B receives the transmission data transmitted from the encoder 21A via the transmission line 43, receives the transmission buffer memory 52 via the demultiplexer 51, and transmits the transmission audio data S51 to the audio data receiving device 53. To receive.

The image data received by the transmission buffer memory 52 is separated into received image data S52 and header data HD11 by a variable length inverse transform circuit 54, and is inversely quantized into inverse quantized data S53 by an inverse quantization circuit 55, and then an inverse transform coding circuit. Discrete inverse transform processing at 56 and inverse transform encoded data
It is converted back to S54.

The inverse transform encoded data S54 is supplied to the decoder circuit 57 together with the header data HD12 formed in the inverse quantization circuit 55, and is encoded as encoded differential data S55 by the frame memory 5.
Stored in 8.

Thus, the encoded difference data S55 is stored in the frame memory 58.
The decoded image data S56 is converted into an analog signal in a digital / analog conversion circuit 59, and then output from the output circuit section 60.
Is transmitted as an output video signal VD _OUT via the.

(G2) Inter-frame / intra-frame coding control The inter-frame / intra-frame coding control unit 30 performs inter-frame coding or intra-frame coding based on the weight of the image to be currently processed and the weight of the prediction error. The processing is to be selected.

That is, the pixel data at the (i, j) coordinates of the macroblock to be currently processed in the current frame data S25 is represented by A
Assuming that (i, j), the macroblock data A to be currently processed of the current frame data S25 represented by the power data Σ (A) is And power data Σ (A)
² (L), Σ (A) ² (H) The sum of squares A ² of the macroblock data is The pixel data at the (i, j) coordinates of the macroblock compensated by the motion vector data for detection MVD (x) and MVD (y) of the frame data S23 before prediction is represented by B (i, j, x, y), the power data Σ
(AB) ² (L), ² of the difference data between the macroblock data A and B represented by Σ (AB) ² (H)
The sum of squares (AB) ² is If the pixel data at the (i, j) coordinate of the macroblock of the predicted current frame data S24 formed via the loop filter 25B is represented by FB (i, j, x, y), the power data Σ (A-FB) ² (L), Σ (A-
FB) Macroblock data A represented by ² (H)
And square sum of difference data FB (A-FB) ² the following equation (However, when the motion compensation mode is not executed, x = y = 0).

Therefore, the weight VAROR of the image to be processed at present from the equations (1) and (2) is The weight VAR of the prediction error when the loop filter is not used is given by the following equation according to equation (3). And from equation (4), the weight FVAR of the prediction error when the loop filter is used is given by the following equation: Is represented by

Accordingly, the filter control unit 31 selects and specifies the inter-frame coding mode or the intra-frame coding mode based on the weight of the macroblock MB calculated in this way.

That is, when the motion compensation mode is not executed (when the loop filter is not used), as shown in FIG. 6, the weight VAROR of the image to be currently processed and the weight VAR of the prediction error when the loop filter is not used are used. When the determined area is in the shaded area Intra, the filter control unit 31 controls the image data encoding circuit 28 to be in the intra-frame encoding mode, and when it is in another area Inter, it is set to the inter-frame encoding mode. Control.

Thus, A (i,
j) -B (i, j, x, y) is encoded, and in the case of the intra-frame encoding mode, A (i, j) is encoded, so that image data can be transmitted efficiently.

On the other hand, when the motion compensation mode is executed (that is, when the loop filter is used), as shown in FIG. 7, the weight VAROR of the image to be currently processed and the weight FVAR of the prediction error when the loop filter is used are set. If the area determined by the control is in the shaded area Intra, the filter control unit 31 controls the image data encoding circuit 28 to the intra-frame encoding mode. Control mode.

Thus, A (i,
j) -FB (i, j, x, y) and motion vector data MV
By encoding D (x) and MVD (y) and encoding A (i, j) in the intra-frame encoding mode, image data can be transmitted efficiently.

Thus, the filter control unit 31 can execute the switching process between the inter-frame coding mode or the intra-frame coding mode based on the weight of the macroblock.

(G3) Forced refresh processing according to the embodiment The filter control unit 31 specifies the inter-frame coding mode or the intra-frame coding mode for each macroblock MB, and then executes the forced refresh processing for a predetermined macroblock MB.

That is, when encoding the image data having the image size of QCIF (FIG. 3 (A1)), as shown in FIG. 8, the filter control unit 31 corresponds to all the macroblocks MB of one frame image. As a result, 99 counters CNT are arranged, and each counter has 0 to 98
A predetermined refresh pattern is formed by randomly substituting a counter value indicating the refresh order up to the above using random numbers.

When the encoding operation is started in this state, when the value of the counter corresponding to each macroblock data is 97 or less when each macroblock data is input, the counter is incremented.

The value of the counter thus incremented becomes
At 98, the inter-frame / intra-frame flag of the flag data FLAGS of the macro block corresponding to the counter is designated as "0", and the macro block is forcibly processed in the intra-frame encoding mode. The value of the counter is cleared to 0.

Thus, one macro block per frame is forcibly switched to the intra-frame coding mode and encoded (ie, forced refresh), so that all macro blocks are refreshed when data for 99 frames is processed. .

Thus, by repeatedly executing the forced refresh, the screen is always refreshed when data for 99 frames is processed.

Accordingly, even when a transmission error occurs and the image quality of the decoded image is degraded on the decoder 21B side, even when the inter-frame coded image data continues to be transmitted for a long time, 99% The deterioration of the image quality is corrected by refreshing all the macroblocks while the image data for the frame is transmitted.

Here, in the macroblock MB that has been forcibly refreshed, quantization processing may be performed with a quantization step size that is significantly different from that of the surrounding macroblock. However, only the macroblock MB is forcibly refreshed randomly by forming the refresh pattern (FIG. 8) in the filter control unit 31 using random numbers. The unsightly change in image quality that occurs can be made inconspicuous.

Thus, forced refreshing can be performed while visually suppressing unsightly changes in image quality.

By the way, in the frame subjected to the frame drop processing, the forced refresh is not executed, and only the image data transmitted to the receiving side is surely refreshed, so that one frame is transmitted for every 99 frames of image data transmitted.
Macro blocks for the frame are surely refreshed.

(G4) Other Embodiments In the above-described embodiment, the case where the present invention is applied when encoding and transmitting an image having a QCIF image size has been described. However, the present invention is not limited to this. The present invention can be applied to the case of encoding an image having an image size (FIG. 3 (A2)).

In this case, four macro blocks may be associated with each of the refresh counters shown in FIG. 8, and four macro blocks may be forcibly refreshed per frame.

Further, in the above-described embodiment, the case where the forced refresh is performed using the refresh pattern shown in FIG. 8 has been described. However, the present invention is not limited to this, and various other refresh patterns arranged using random numbers may be used. Applicable.

Furthermore, in the above-described embodiment, the case where the present invention is applied to the image information transmission system that transmits the video signal together with the audio signal has been described. However, the present invention is not limited to this, and the video signal is subjected to high-efficiency encoding processing. It can be widely applied to transmission and the like.

H Advantageous Effects of the Invention As described above, according to the present invention, since the refresh pattern is formed using random numbers, each macro block can be forcibly refreshed at random, thereby partially occurring. An unsightly change in image quality can be visually suppressed.

[Brief description of the drawings]

1 and 2 are block diagrams showing an encoder and a decoder constituting an image information transmission system to which the video signal encoding method according to the present invention is applied, FIG. 3 is a schematic diagram showing a configuration of frame image data, and FIG. 4 is a block diagram showing the header data processing system shown in FIG. 1, FIG. 5 is a schematic diagram showing the configuration of the flag data shown in FIG. 4, and FIGS. 6 and 7 show the inter-frame / intra-frame encoding mode. FIG. 8 is a schematic diagram showing a refresh pattern of a macro block, FIG. 9 is a schematic diagram used to explain intra-frame / inter-frame encoding processing, and FIG. FIG. 11 is a block diagram showing an image data generating apparatus, and FIG. 11 is a curve diagram showing the quantization steps. 21 ... Image information transmission system, 21A ... Encoder, 21B
... A decoder, 25 a motion compensation circuit, 26 a motion compensation control unit, 27 a frame memory before prediction, 28 a picture data encoding circuit, 29 a transform encoding circuit, 30 an interframe / Intra-frame encoding control unit, 31 ... Filter control unit, 32 ... Transmission buffer memory, 34 ... Transmission block setting circuit, 35 ... Threshold control unit, 36 ... Quantization control unit, 37 ... Quantization circuit, 38
…… Variable length code enable circuit.

Claims (2)

(57) [Claims] 1. An image of one frame formed by a video signal is divided into a predetermined number of blocks each having a predetermined number of pixels, and each of the divided blocks is subjected to intra-frame encoding or inter-frame coding. A video signal encoding method for converting the video signal into transmission image data by selecting an encoding process and performing an encoding process, wherein the video data of the predetermined number of blocks and a motion vector of a frame before prediction are detected, and A first step of performing motion compensation for the motion vector on the pre-prediction frame and outputting the predicted current frame data, and outputting the video data of the predetermined number of blocks, and the prediction step output in the first step The current frame data and the video data of the predetermined number of blocks are input, and the predicted current frame data and the video of the predetermined number of blocks are input. Output the operation data for calculating the weight with the data, output the video data in the intra-frame encoding processing mode, and output the video data and the predicted current frame data in the inter-frame encoding processing mode. Calculating the weight of the difference data between the video data of the predetermined number of blocks and the predicted current frame data based on the calculation data output in the second step. Selecting either the intra-frame encoding mode or the inter-frame encoding mode based on the operation value, randomly forming a counter value indicating a refresh order in each of the blocks, and encoding each of the blocks. The counter value is incremented each time the conversion process is performed, and when the counter value reaches a predetermined value, And a third step of selecting the second step mode so that the video data of the lock is processed in the intra-frame encoding processing mode and clearing the counter value. Encoding method. 2. An image of one frame formed by a video signal is divided into a predetermined number of blocks each having a predetermined number of pixels, and each of the divided blocks is subjected to intra-frame coding or inter-frame coding. A video signal encoding apparatus for converting the video signal into transmission image data by selecting and encoding the encoding process, detecting the video data of the predetermined number of blocks and a motion vector of a frame before prediction, and Motion compensating means for performing motion compensation for a motion vector on the pre-prediction frame and outputting predicted current frame data, and outputting the predetermined number of blocks of video data; and the predicted current frame output from the motion compensating means. The data and the predetermined number of blocks of video data are input, and the predicted current frame data and the predetermined number of blocks of the video data are input. And output the video data in the intra-frame encoding mode, and output the video data and the predicted current frame data in the inter-frame encoding mode. Video encoding means for outputting difference data, and calculating the weight of difference data between the video data of the predetermined number of blocks and the predicted current frame data based on the operation data output from the video encoding means, Based on the calculated value, either the intra-frame encoding mode or the inter-frame encoding mode is selected to control the video encoding means, and a counter value indicating a refresh order is randomly assigned to each block. And the above counter value is incremented each time the encoding process is performed for each block. Control means for controlling the video coding means so that the video data of the block is processed in the intra-frame coding processing mode when the counter value reaches a predetermined value, and for clearing the counter value. A video signal encoding device characterized by the above-mentioned.