JP3168626B2 - Video signal high-efficiency coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal high-efficiency coding apparatus suitable for application to, for example, a so-called video conference system or moving picture telephone system.

[0002]

2. Description of the Related Art In recent years, there has been proposed a method of combining still image and moving image information in addition to audio information and transmitting the information to another place.

For example, in a video conference system or the like,
2. Description of the Related Art It has been made possible for a person who is in a distant place to have a conference by exchanging audio and video using so-called audio-visual (AV) equipment.

When voice information and image information are combined to communicate with each other at a distant place as in this video conference system, these voice and image information are each encoded and transmitted.

[0005] The encoding of this image information was performed in December 1990.
The H.264 video codec (coder, decoder) recommendation was adopted by the International Telegraph and Telephone Consultative Committee (CCITT), a subsidiary of the International Telecommunication Union (ITU), in January. H.261.

[0006] Moving image coding is applied to a standard television or high definition (H) signal source.
D) The use of television involves a range of applications involving signal transmission to remote locations, such as broadcasting and communication, and a range of local signal processing applications such as storage.

The above recommendation H. As a video format based on H.261, a common intermediate format (CIF: Common In) capable of resolving the difference in television system between regions (the whole world) and enabling communication between CODECs.
Terminate Format).

[0008] The resolution of the image by this CIF is 35 horizontal.
2, 288 dots vertically.

The structure of the image data to be transmitted has a hierarchical structure as shown in FIG.

That is, in the intermediate format CIF, one picture (each of 1 to 12 in the figure) has G
loop of Block (GOB) (1 in the figure)
One GOB is a macro block composed of luminance information Y and color information CB and CR, and one luminance information Y (1 to 4 in the figure) is a block of 8 × 8 pixels. Is done.

The source encoded output, that is, the quantization index of the transform coefficient, the motion vector information, the block type information, and the like are further compressed by variable-length encoding utilizing statistical properties and then multiplexed into one bit string. You.

[0012] Which of the six blocks constituting the above-mentioned macroblock is valid is encoded as a pattern.

The image data sent to the transmission path is provided with macroblock attribute information for each of the six blocks constituting the macroblock, a GOB header is attached for each of the macroblocks constituting the GOB, and further, these picture data. Is attached to a picture header for each GOB that constitutes the data string, and is used as a data string.

In transmitting the image data, the image information of the interpolation frame is formed on the transmission side and transmitted to the reception side.

Here, the transmission data DATA is composed of image data subjected to high-efficiency encoding processing as shown in FIGS. 9 and 10.

In this high efficiency coding, as shown in FIG. 9A, for example, at time t = t ₁ , t ₂ , t ₃ ..., Moving picture images PC1, PC2, PC3. In the transmission processing, the video signal has the feature that the autocorrelation is large, and the digital data to be transmitted is compressed to improve the transmission efficiency. And an inter-frame encoding process.

In the intra-frame encoding process, as shown in FIG. 9A, images PC1, PC2, PC3,... Are calculated by calculating the difference between pixel data adjacent one-dimensionally or two-dimensionally along the horizontal operation line direction. The compression processing as required is performed, and thus the transmission frame image data of the number of compressed bits is formed for the corner images PC1, PC2, PC3,.

As shown in FIG. 9B, in the inter-frame encoding process, images PC12 and PC23 representing the deviation between adjacent images PC1 and PC2, PC2 and PC3...
.., And vector data x ₀ , x ₁ , x ₂ , x _3, ... Representing the motion of the image, and differential data between adjacent images sequentially, and the initial image PC1 at time t = t ₁ .
Along with the image data (consisting of intra-frame encoded data).

Thus, the images PC1, PC2, PC3 ...
As compared with the case where all the pixel data are transmitted, the video signal can be efficiently encoded into digital data having a smaller number of bits and transmitted.

Then, as shown in FIG. 10, the image data to be transmitted is divided into blocks each having a predetermined number of frames (for example, 10 frames), and the block data... BL (N-1), BLN, BL (N + 1) ...
Are sequentially subjected to a high-efficiency encoding process, and then transmitted from the transmitting side to the transmission line in that order.

The block data BLN (N =... N−1,
..) Are the first frame data D1
Has intra-frame encoded processing data as
Interframe coding processing data is included as the tenth frame data D2 to D10.

Here, the intra-frame encoding process includes difference data for all pixels forming an image for one frame, as described with reference to FIG. 9A.
Frame image data representing one image is reproduced by sequentially adding the difference data of the frames.

On the other hand, the second to tenth frame data D2 to D10, which are inter-frame coded data, are shown in FIG.
As described in the above, only the changed pixel in the successive frame images is converted into motion vector data and difference data representing the difference between the inter-frame images.

Thus, in practice, the first frame data D1 constitutes transmission data having relatively low compression efficiency (thus having a large number of bits) by constituting data representing the differences of all pixels for one frame. For the second
The tenth to tenth frame data D2 to D10 constitute transmission data having a relatively high compression efficiency (and thus having a small number of bits) representing only movement between image data.

FIG. 6 shows a communication format common to all nations using the above-mentioned intermediate format CIF.

That is, as shown in FIG. 6, a video camera 31 with a specification of 625 scanning lines (for example, PAL system) at 50 Hz or a video camera with a specification of 525 scanning lines (for example, NTSC system) at 60 Hz. The image data picked up by 33 is converted by the converter 32 into image data in the above-described CIF format.

Then, the image data is encoded by the coder 35 and transmitted, and the image data encoded and transmitted by the coder 35 is decoded by the decoder 36 and transmitted to the CIF.
To image data of the format.

Further, the image data in the CIF format is converted into the original video signal by the converter 37 or 39, and the specification of 625 scanning lines (for example, P
A video signal converted by a television of the specification (for example, NTSC system) with 525 scanning lines at a television 38 or 60 Hz of the AL system (60 Hz) is projected.

In the above communication process, the H.264 standard is used. The specified range 261 is the range of the coder (encoder) 35 and the decoder (decoder) 36.

FIG. 7 shows an example of a video conference system. Hereinafter, an example of the video conference system will be described with reference to FIG.

In FIG. 7, reference numeral 41 denotes a terminal device, which can communicate with another terminal device 42 under the control of a remote control unit 44 via a network 43.

The configuration of the terminal device 41 (the configuration of the terminal device 42 is the same as the configuration of the terminal device 41 described below) will be described.

That is, at the time of transmission, the video signal supplied from the video input / output device 45 is supplied to the video codec 46,
This video codec 46 has an intermediate format (CIF)
After being subjected to filtering for noise removal and the like, the image data is supplied to a multimedia multiplexer / demultiplexer 53.

The device that supplies image data to the video input / output device 45 may be any device that outputs image data.

On the other hand, the audio signal from the audio input / output device 48 is also supplied to the audio codec 49, where the audio codec 49 performs an encoding process and the like and further delays the audio signal by a predetermined time. Supplied.

Information from the telematic device 51 is supplied to a multimedia multiplexer / demultiplexer 53.

Each data supplied to the multimedia multiplexer / demultiplexer 53 is subjected to multiplex processing by the multimedia multiplexer / demultiplexer 53 under the control of the system controller 52. 54
And is supplied to another terminal device 42 via the network 43.

On the other hand, when a transmission signal is received from another terminal device 42, the multiplexed signal is supplied to the multimedia multiplexing / demultiplexing device 53 via the network interface 54, and the multimedia multiplexing / demultiplexing device 53 performs the demultiplexing process. The video data is supplied to the video codec 46, the audio data is supplied to the audio codec 49 via the delay unit 50, and the data for the telematic device is supplied to the telematic device 51.

The encoded video data is converted into an original video signal by a video codec 46, and then supplied to, for example, a television or the like (not shown) via a video input / output device 45. The image is projected on the surface.

The encoded audio data is converted into an original audio signal by the audio codec 49, and then supplied to, for example, a speaker (not shown) via the audio input / output device 48, and output by the speaker or the like. Is done.

In such a video conference system,
The video codec 46 described above complies with the video recommendation H.264. 261.

As described above, the codec 46 encodes image data when transmitting image data and the like, decodes the encoded image data when receiving image data, and obtains the original image data. It is.

FIG. 5 is a block diagram of the transmitting side (coder) and the receiving side (decoder) of the image data, which will be described below.

For convenience of explanation, the codec of the transmitting terminal and the decoder of the receiving terminal are shown as codecs, and the decoder of the transmitting terminal and the coder of the receiving terminal are not shown. I do.

In FIG. 5, reference numeral 1 denotes an input terminal to which a video signal from the video input / output device described in FIG. 7 is supplied. The video signal from the input terminal 1 is converted into a digital video signal by the A / D converter 2. Motion detection and
It is supplied to the motion correction circuit 3.

The motion detection / motion correction circuit 3 performs the motion compensation inter-frame prediction based on the digital video signal from the A / D converter 2 and the image data of the immediately preceding frame from the frame memory 23 which will be described later. The processing is performed for 16 pixels, and as a result, only the motion information of the digital video signal is supplied to the determination circuit 4.

The decision circuit 4 determines, based on the overflow information from the buffer 8, whether to send the motion information from the motion detection / motion compensation circuit 3 in the inter mode or the intra mode.

As described above, the inter mode is a mode in which a difference between preceding and succeeding frames is extracted to obtain an inter-frame difference signal, and the intra mode is a mode in which a large amount of information is extracted from one frame and an intra-frame prediction signal is obtained. is there.

The data from the decision circuit 4 is supplied to an orthogonal transformation circuit 5.

The orthogonal transform circuit 5 orthogonally transforms the data from the decision circuit 4 with an 8 × 8 block size, and supplies the transformed data to the quantization circuit 6.

By the orthogonal transformation by the orthogonal transformation circuit 5,
The data (time axis data) from the decision circuit 4 is converted to frequency axis data having a small amount of information.

The quantization circuit 6 quantizes the transformed data from the orthogonal transformation circuit 5 based on the overflow information from the buffer 8 and supplies the quantized image data to the Huffman encoding circuit 7.

On the other hand, the image data quantized by the quantization circuit 6 is also supplied to an inverse quantization circuit 20, where the image data is inversely quantized, and then inversely transformed by an inverse orthogonal transform circuit 21. After being orthogonally transformed and decoded by a decoder (local decoder) 22, it is stored in a frame memory 23.

The image data from the frame memory 23 is supplied to the above-described motion detection / motion compensation circuit 3 after the distortion between the blocks is removed by the loop filter 24.

The Huffman encoding circuit 7 is the above-described quantization circuit.
For the image data from No. 6, encoding is performed by giving a short code corresponding to the number of "0".

The image data from the Huffman coding circuit 7 is supplied to an error correction coding circuit 9 via a buffer 8.

The error correction coding circuit 9 adds error correction to the image data from the buffer 8 to cope with noise in the transmission path (corresponding to the network 43 described in FIG. 7).

The image data from the error correction coding circuit 9 is supplied to a multiplexer 10 which variably encodes the image data and various other data and multiplexes the data into a code sequence having a predetermined data structure. I do.

The image data from the multiplexer 10 is supplied to the demultiplexer 11 on the receiving side.

After the data of the code string multiplexed by the demultiplexer 11 on the receiving side is converted into the original image data, it is supplied to the inverse Huffman coding circuit 13 through the error correction coding circuit 12.

The image data quantized by the inverse Huffman encoding circuit 13 is converted into image data which is supplied to an inverse quantization circuit 14 where the image data is inversely quantized by the inverse quantization circuit 14 to obtain image data on the frequency axis. It is said.

The image data on the frequency axis is supplied to the inverse orthogonal transform circuit 14, converted into image data on the time axis, further supplied to the decoder 16 and converted into the original image data.
Furthermore, after being temporarily stored in the frame memory 17, it is supplied to a DA converter 18 and converted into an analog video signal by the DA converter 18.

The analog video signal is supplied to the output terminal 1
The video signal is supplied to a television or the like (not shown) via the video output device 45 described with reference to FIG. 9 and FIG.

[0064]

By the way, in the above-mentioned video signal high efficiency coding apparatus, the judgment of the inter and intra of the block of the input video signal is made by the judgment circuit 4 before the orthogonal transformation circuit 5 performs the orthogonal transformation. Has gone by.

The judgment of the inter or intra performed by the judgment circuit 4 is controlled by the feedback of the remaining amount of the transmission buffer 8 because of the so-called frame drop.

On the other hand, the quantization circuit 6 at the subsequent stage of the orthogonal transformation circuit 5 is also controlled by the feedback of the remaining amount of the transmission buffer 8 described above.

The above two feedback systems are all performed through the system CPU.

Accordingly, these two control points are dispersed before and after the orthogonal transform circuit 5, and this has the disadvantage that control by buffering between control points becomes complicated.

In addition, since the interface with the system CPU is distributed in two places, the processing system becomes complicated and the hardware becomes expensive.

The present invention has been made in view of the above points, and provides a video signal high-efficiency coding apparatus capable of improving controllability by centralizing control, simplifying a processing system, and reducing hardware costs. It is something to propose.

[0071]

As shown in FIGS. 1 to 4, for example, a video signal high-efficiency encoding apparatus according to the present invention comprises a first orthogonal transform means 28 for orthogonally transforming a video signal in a frame; type second orthogonal transform means 33 orthogonally transforming the difference signal between frames of the orthogonally transformed image data by the first orthogonal transformation means 28 orthogonally transformed image data and the second orthogonal transformation means 33 , First orthogonal transform means 2
Orthogonally transformed image data is 8 and the second orthogonal transformation means 3
A selection unit 30 for selecting which of the image data subjected to the orthogonal transformation in step 3 is to be quantized and a selection unit 30 for selecting
Quantizing means 34 for quantizing the image data,
Encoding means for encoding the image data quantized in stage 34
Step 40 and the image data encoded by the encoding means 40
A storage unit 41 for storing the data;
Overflow information from means 41 and first orthogonal transformation
Image data orthogonally transformed by the means 28 and a second orthogonal transformation
Comparison of information amount with image data orthogonally transformed by means 33
The image data is selected based on the result .

[0072]

According to the present invention described above, orthogonal transform, quantization and quantization are performed.
From the storage means for storing the encoded image data.
Flow information, inter mode and intra mode
Comparison of the amount of information of image data that has been orthogonally transformed by
Based on the results, Inter mode or Intra mode
Since it is selected whether to quantize the orthogonally transformed image data due to the deviation, the feedback from the storage means
Control points can be concentrated on one,
The controllability can be improved by centralizing the control, the processing system can be simplified, and the hardware cost can be reduced.

[0073]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the video signal high efficiency coding apparatus according to the present invention will be described below in detail with reference to FIG.

In FIG. 1, portions corresponding to those in FIGS. 5 to 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numeral 25 denotes an input terminal to which an analog video signal is supplied from a device or the like which outputs an image. The video signal from the input terminal 25 is supplied to an analog-digital conversion circuit 26.

The analog-to-digital conversion circuit 26 has, for example, a CPU (not shown) therein, converts a video signal from the input terminal 1 into digital data, and converts the converted digital image data into a still image to be described later. Each memory 27a, 27 constituting the memory 27 in the mode
b, 27c and 27d, respectively.

This analog-digital conversion circuit 26
In the still image mode, image data for four frames is extracted by performing sampling with a sampling clock having four different phases (meaning that the phase of the sampling clock is shifted) for each frame of a moving image.

For example, the image data a sampled by the first sampling clock is used as an image identifier (I
D), the image data b sampled by the second sampling clock is written to the memory 27b with the image identifier attached thereto, and the image data c sampled by the third sampling clock is written to the memory 27b. And writes the image data d sampled at the fourth sampling clock to the memory 27d with an image identifier attached.

The image data a, b, c and d written in the memory 27 are sequentially read out and supplied to the orthogonal transformation circuit 28 as inter mode data (inter-frame difference signal).

The orthogonal transformation circuit 28 converts the image data read from the memory 27 or the intra-mode image data directly supplied from the analog-digital conversion circuit 26 into a block of 8 × 8 pixels explained in FIG. Is converted from time axis data to frequency axis data in units of .times..times..times..times..times..times..times..times..times..times.

On the other hand, the motion detection / motion compensation circuit 31 performs motion detection and motion compensation of the image data a, b, c and d written in the memory 27 or the image data directly supplied from the analog-digital conversion circuit 26. Supplied from the frame memory 38 through the loop filter 39.
Based on the image data of the previous frame, for example, 16 × 1
This is performed for six pixels.

The moving picture data or still picture data a, b, c and d from the motion detection / motion compensation circuit 31 and the image data immediately before the motion detection / motion compensation processing are applied to the subtraction circuit 32. Each is supplied and subjected to a subtraction process by the subtraction circuit 32.

The inter-frame difference signal obtained by the subtraction circuit 32 is supplied to an orthogonal transformation circuit 33, and is converted from time axis data to frequency data in the same manner as the above-described orthogonal transformation circuit 28. It is supplied to the other fixed contact 29b.

The determination circuit 30 determines the overflow information from the buffer (transmission buffer) 41 and the result obtained by an algorithm for determining whether to transmit image data in the inter or intra mode, which will be described later.
The movable contact 29c of the switch 29 is connected to the fixed contact 29a or 29b.

That is, when the buffer 41 overflows or when it is determined to transmit in the inter mode as a result obtained by the algorithm, the movable contact 2 of the switch 29
9c is connected to the fixed contact 29b, and the inter-mode image data is supplied to the quantization circuit 34. At other times or when it is determined that the image data is transmitted in the intra mode as a result obtained by the algorithm, the movable contact 29c of the switch 29 is
Are connected to the fixed contact 29a, and the image data in the intra mode is supplied to the quantization circuit 34.

The quantization circuit 34 quantizes the image data from the determination circuit 30 in units of macro blocks described in FIG. 8, and supplies the quantized image data in units of macro blocks to the Huffman encoding circuit 40. At the same time, the signal is also supplied to the inverse quantization circuit 35.

The inverse quantization circuit 35 inversely quantizes the image data in units of macroblocks from the quantization circuit 34, and supplies the inversely quantized image data to the inverse orthogonal transform circuit 36.

The inverse orthogonal transform circuit 36 converts the frequency axis image data from the inverse quantization circuit 35 into time axis image data, and supplies this image data to the decoder 37 .

The decoder 37 comprises an inverse orthogonal transform circuit 36
Is written into the frame memory 38.

The image data written in the frame memory 38 is supplied to the above-mentioned motion detection / motion compensation circuit 31 via a loop filter 39 for removing distortion components between blocks.

The quantized image data supplied to the Huffman encoding circuit 40 is supplied to an error correction encoding circuit 42 via a buffer 41.

The image data from the buffer 41 is subjected to error correction by the error correction encoding circuit 42.
Thereafter, it is supplied to the multiplexer 43, multiplexed with other information, and transmitted to the receiving side.

The demultiplexer 44 on the receiving side obtains image data from the data from the multiplexer 43 and supplies this image data (including the image identifier in the case of the still image mode) to the error correction encoding circuit 45.

The image data which has been subjected to the error correction processing in the error correction encoding circuit 45 is thereafter supplied to an inverse Huffman encoding circuit 46, and the inverse Huffman encoding circuit 4
6, the data is returned to the quantized data.
, And is converted into image data on the frequency axis by the inverse quantization circuit 47.

The image data is converted by the inverse orthogonal transform circuit 4
After being converted from the data on the frequency axis to the data on the time axis by 8, the data is supplied to the decoder 49.

After the image data is decoded by the decoder 49 and stored in the frame memory 50,
In the still image mode, the selector 51 writes the data into any of the memories 53a, 53b, 53c and 53d constituting the memory 53 based on the identification data attached to each still image data. ,
The signal is supplied to the DA converter 54 through the selector 51, and is output as an analog video signal through the output terminal 55 by the DA converter 54.

When the selector 51 is in the still image mode, the image data read from the frame memory 50 is read in accordance with a control signal from the detection circuit 52 in accordance with the identification data attached to the memory 53a, 53b, 53c.
And 53d.

The detection circuit 52 includes an inverse Huffman encoding circuit 4
6, the image data among the image data a, b, c, and d is detected based on the image identifier added to the image data, and the selector 51 is provided to the selector 51 in accordance with the detection result. Supply control signals.

In the case of the still image mode, the memory 53
The read image data a, b, c, and d are converted into an analog video signal by the DA converter 54 as one still image, and output from the output terminal 55 to an external device (for example, a television). .

Therefore, when this analog still image is projected on the screen of a monitor or the like, a still image having four times the number of pixels of the CIF image, that is, twice the resolution, is projected. Become.

Next, a communication flow in the above-described video signal high efficiency coding apparatus will be described with reference to FIG.

In FIG. 2, thin solid arrows indicate the flow of processing, dashed arrows with respective numbers indicate the flow of processing for performing repetition, and thick arrows indicate communication processing between circuits. Show the flow.

First, step 100 of the moving image mode 100
In a, instruction data and image data from the A / D converter 26 are supplied to the error correction encoding circuit 42.

At this time, bit 3 of the command signal is set to "0" (release off), and bit 2 is set to "0" (document camera off).

In step 100b, the error correction encoding circuit 42 transmits the moving image via the multiplexer 43 in accordance with the above-mentioned command signal, and outputs the completion signal to the A-
It is supplied to the D converter 26.

[0106] Here, the operation described above, i.e., A-D converter 26 is supplied to the error correction coding circuit 42 of the instruction data and image data according to well into the A-D converter 26 by the error correction encoding circuit 4 2 repeated supply of the completion signal, the transmission of moving image data is performed via the multiplexer 4 3.

Next, in step 200a, the system C
The PU requests the multiplexer 43 for a freeze picture.

In step 200b, the multiplexer 43 supplies a control signal for causing the decoder 37 to perform a freeze picture operation in response to a request from the system CPU.

At step 200c, the completion signal from the decoder 37 is supplied to the multiplexer 43, and the multiplexer 43 outputs a signal indicating this to the system C.
Supply to PU.

At step 200d, the system CPU enters the freeze picture mode.

Next, in step 300a, the system CPU enters the still image mode, and a control signal indicating this is supplied to the AD converter 26.

In step 300b, the A / D converter 26 supplies instruction data indicating a freeze request to the error correction encoding circuit 42 according to a control signal from the system CPU.

That is, bit 3 of this instruction data is set to "0".
(Release off), bit 2 is set to "0" (document camera off), and the codec is forced to generate an insignificant block.

In step 300c, the error correction encoding circuit 42 performs a picture freeze operation, and supplies a completion signal to the AD converter 26.

[0115] Therefore, the state is maintained in which the image is not updated while the connection is maintained.

Next, at step 400 a of the picture freeze mode 400, the A / D converter 26 supplies the instruction data to the error correction encoding circuit 42 and stores the still picture data in the memory 27.

In step 400b, the error correction encoding circuit 42 supplies a completion signal to the AD converter 26.

Then, these steps 400a and 400
b is repeated four times, and the memories 27a, 27b, 2
7c and 27d are stored in the memory 27 in this order.
a to 27d.

Next, step 50 of the still image mode 500
At 0a, the A / D converter 26 supplies the error correction encoding circuit 42 with instruction data for preparing for transmission of a still image.

That is, in the above-described step 500a,
The document camera signal (FIG. 3B), which is bit 2 of the command data, is set to “1” (document camera on) and bit 3 is set to “0” (release off) in synchronization with the vertical synchronization signal shown in FIG. 3A. ).

At step 500b, the error correction encoding circuit 42 supplies the A / D converter 26 with a completion signal indicating that preparation for still image transmission has been completed.

That is, in the above-described step 500b,
When the error correction coding circuit 42 supplies a completion signal to the A / D converter 26, the A / D converter 26 performs error correction coding on the trigger signal shown in FIG. 3C in synchronization with the vertical synchronization signal shown in FIG. It is supplied to the circuit 42.

Now, the transmission of the still picture data starts from here. In this example, the first still picture frame uses a plurality of moving picture frames from a coarse quantization step size to a fine quantization step size. Be transmitted progressively.

That is, only the first still picture frame is transmitted in the intra mode for one moving picture frame, and when the quantization step is reduced to the minimum, the next still picture frame is transmitted.

[0125] Similarly, the still image frame is transmitted as an inter frame using a plurality of moving image frames from a coarse step size to a fine step size.

By repeating such a method,
A plurality of still image data are transmitted.

Since the pixel immediately adjacent to the immediately preceding frame is adjacent to the second frame and the correlation between the pixels is strong, the second frame can be transmitted as an inter mode by orthogonally transforming and quantizing only the difference information. .

That is, when a trigger signal as shown in FIG. 3C is supplied to the error correction encoding circuit 42, the still image data of the first frame is read out from the memory 27a, and as shown in FIG. Transmitted by the multiplexer 43.

[0129] Next, in step 600a of the mode 600 to transmit the still image data in inter mode, the A-D converter 26, memory 27a, 2 7b, 27c,
Image data is sequentially read from 27d, and is sequentially supplied to the error correction encoding circuit 42.

In step 600b, the error correction encoding circuit 4 to which the image data is supplied from the AD converter 26
2 supplies a trigger signal to the A / D converter 26 as shown in FIG. 3C.

The memories 27a, 27b, 27c,
Still image data read from 27 d is transmitted by the multiplexer 43.

As shown in FIG. 3, the error correction coding circuit 4
Every time the trigger signal from FIG. 2 (FIG. 3C) becomes “1”, as shown in FIG. D, still image data of the first to fourth frames (only the first frame is transmitted in the intra mode first). ) Are sequentially transmitted in the inter mode.

This still picture data is stored in any memory 27a.
To the receiving side, that is, to the demultiplexer 44, with the identification data indicating whether the data is read from .about.27d added.

Then, as described with reference to FIG. 1, after this still image data is identified by the selector 51, the selector 51 determines which of the memories 53a, 53b, 53c and 53d corresponds to the still image data. or to be written, further, after 4 frames are written, is a single still image data, after being made into an analog still picture image signal by D-a converter 5 4, through the output terminal 55 output Is done.

Then, the analog still image signal is
For example, the image is projected on a screen of a monitor or the like connected to the output terminal 55.

The analog still picture image signal projected on the monitor screen (not shown) is composed of four frames of still picture image data as one still picture image signal. It has four times the number of pixels of a CIF image, that is, twice the resolution.

In this example, a still image having four times the number of pixels of the CIF image of the video recommendation H261 is obtained. A still image with twice the number of pixels can be obtained.

Next, in step 700a of the picture freeze mode 700, the error correction encoding circuit 42 supplies the A / D converter 26 with a completion signal indicating that the transmission of the still image data has been completed.

In step 700b, the A / D converter 26 supplies a completion signal to the system CPU and supplies instruction data to the error correction encoding circuit 42.

That is, the codec is forcibly output an insignificant block, and the transmission of the still image data is not performed while the connection is maintained.

At step 700c, when the system CPU is supplied with the completion signal from the A / D converter 26, the system CPU cancels the still image mode.

In step 800a of the moving image mode 800, the system CPU enters the moving image mode, and the system CPU supplies a control signal indicating this to the AD converter 26.

At step 800b, the A / D converter 26 supplies instruction data to the error correction encoding circuit 42 according to a control signal from the system CPU.

That is, the bit 3 of the instruction data is set to "1" (release on).

At step 800c, the error correction encoding circuit 42 enters the moving image mode according to the instruction data from the A / D converter 26, and supplies a completion signal to the A / D converter 26.

At step 800d, the command and the image data from the AD converter 26 are supplied to the error correction coding circuit 42, respectively.

That is, as shown in FIG. 3B, bit 2 of the instruction data is set to “0” (document camera off), and bit 3 is set to “0” (release off).

At step 800e, the error correction encoding circuit 42 supplies a completion signal to the A / D converter 26, and the image data can be transmitted through the multiplexer 43.

Next, step 900 of the moving image mode 900
In a, the system CPU supplies a control signal requesting cancellation of the freeze operation of the decoder 37 to the AD converter 26.

At step 900b, the AD converter 26 supplies the instruction data to the error correction coding circuit 42.

That is, bit 2 of the instruction data is set to "0" (document camera off), and bit 3 is set to "1" (release on).

At step 900c, the error correction coding circuit 42 is controlled according to the control signal from the AD converter 26.
Causes the freeze operation of the decoder 37 to stop,
A completion signal is supplied to the A / D converter 26.

At step 900d, the image data (moving image data) and the command data from the AD converter 26 are supplied to the error correction encoding circuit 42, respectively.

That is, bit 2 of the instruction data is set to “0” (document camera off), and bit 3 is set to “0” (release off).

At step 900e, the error correction coding circuit 42 supplies a completion signal to the A / D converter 26 and transmits image data (moving image data) through the multiplexer 43.

Next, determination of the above-mentioned inter and intra modes will be described.

That is, in this example, after the orthogonal transformation is performed, it is determined whether the image data is transmitted in the inter mode or the intra mode.

In this way, the frame drop and quantization circuit 3
4 can be integrated into one place, so that the circuit and the like are easily mounted, and the control is also ensured.

The algorithm for determining the inter or intra mode will be described. The calculation is performed for each of the above-mentioned macroblock units, for the coefficients of the four luminance blocks after the orthogonal transformation by the orthogonal transformation circuit 28.

Basically, since the sum of the squares or the absolute values of the AC components of the inter and intra components substantially corresponds to the code amount after variable length coding, the comparison is performed by comparing these.

If the luminance change of the entire block (DC component of the inter block) is smaller than a certain value, it is highly likely that this macro block is determined to be an insignificant block. Block.

This can be summarized as follows.

That is, the change in luminance over the entire macroblock can be expressed by the following equation (1).

[0164]

(Equation 1)

The AC of the inter and intra blocks
The cumulative addition of the absolute values of the components is expressed by the following equations (2) and (3), respectively.

[0166]

(Equation 2)

[0167]

(Equation 3)

Note that n is 63.

Then, according to the above-described equations 1, 2 and 3,
The algorithm for the determination is as shown in the flowchart of FIG.

Hereinafter, the determination algorithm will be described with reference to the flowchart of FIG.

First, at step 100, the inter DC
It is determined whether .ltoreq.256 (constant). If "YES", the flow shifts to the step 110; if "NO", the step 1 is determined.
Move to 20.

That is, the DC component of the inter mode is obtained for each macro block, and it is determined whether or not this is a constant 256 or less.

In step 110, the mode is set to the inter mode. That is, the image data to be transmitted is set to the inter mode.

That is, the determination circuit 30 described with reference to FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29b for the inter mode.

Thus, the inter-mode image data from the orthogonal transformation circuit 33 is transmitted through the switch 29, the quantization circuit 34, the Huffman encoding circuit 40, the transmission buffer 41, and the error correction encoding circuit 42 of the decision circuit 30. The signal is supplied to the multiplexer 43 and transmitted by the multiplexer 43.

In step 120, the inter ACsum
<Intra ACsum is determined, and if “YES”, the process shifts to the step 130; if “NO”, the process proceeds to a step 14
Move to 0.

That is, the AC component of the inter mode image data is obtained for each macroblock, and its absolute value, that is,
Similarly, the power weight is calculated. Similarly, the AC component of the image data in the intra mode is calculated in macroblock units, and the absolute value, that is, the power weight is calculated. It is determined whether it is smaller than.

At step 130, the mode is set to the inter mode. That is, the image data to be transmitted is set to the inter mode.

That is, here, the judgment circuit 30 described with reference to FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29b for the inter mode.

As a result, the inter-mode image data from the orthogonal transform circuit 33 is transmitted through the switch 29, the quantization circuit 34, the Huffman encoding circuit 40, the transmission buffer 41, and the error correction encoding circuit 42 of the decision circuit 30. The signal is supplied to the multiplexer 43 and transmitted by the multiplexer 43.

At step 140, the mode is set to the intra mode. That is, the image data to be transmitted is set to the intra mode.

That is, the determination circuit 30 described with reference to FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29a for the intra mode.

Thus, the image data in the intra mode from the orthogonal transform circuit 28 is transmitted through the switch 29, the quantizing circuit 34, the Huffman encoding circuit 40, the transmission buffer 41, and the error correction encoding circuit 42 of the decision circuit 30. The signal is supplied to the multiplexer 43 and transmitted by the multiplexer 43.

As described above, in this example, when transmitting a still image, a moving image is stored in, for example, four frames of memories 27a, 27b, 27c and 27d, respectively.
Since these are sequentially transmitted, even in a format based on the recommendation of H261, it is possible to transmit an image having a resolution that is an integral multiple of the CIF image, and orthogonally transform image data in the inter and intra modes. After that, it is determined whether to transmit the inter-mode image or the intra-mode image. Therefore, it is possible to concentrate the control points by the feedback from the transmission buffer 41 into one, and to centralize the control. As a result, the system controllability can be improved, the processing system can be simplified, and the hardware cost can be reduced.

The present invention is not limited to the above-described embodiments, but may take various other configurations without departing from the spirit of the present invention.

[0186]

According to the present invention described above, the orthogonal transformation, the amount
Storage means for storing the digitized and encoded image data
Overflow information, inter mode and
Information amount of image data orthogonally transformed by
Based on the comparison result of
Since the orthogonally transformed image data in either de were to choose a <br/> or quantization, Fidoba than accumulating means
Control points can be concentrated on one
Therefore, there is an advantage that controllability can be improved by centralizing control, a processing system can be simplified, and hardware costs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal high-efficiency encoding apparatus according to the present invention.

FIG. 2 is a diagram showing a communication flow for explaining one embodiment of the video signal high efficiency coding apparatus of the present invention.

FIG. 3 is a timing chart for explaining one embodiment of a video signal high-efficiency encoding apparatus according to the present invention;

FIG. 4 is a flowchart for explaining one embodiment of the video signal high efficiency coding apparatus of the present invention.

FIG. 5 is a block diagram showing an example of a conventional high efficiency coding apparatus.

FIG. 6 is a diagram showing an outline of a communication system.

FIG. 7 is a block diagram of a videophone system.

FIG. 8 is a diagram showing a configuration of image data.

FIG. 9 is an explanatory diagram showing high efficiency coding.

FIG. 10 is an explanatory diagram showing blocks of image data.

[Explanation of symbols]

 28, 33 Orthogonal transformation circuit 30 Judgment circuit 34 Quantization circuit 40 Huffman encoding circuit 41 Transmission buffer 42 Error correction encoding circuit 43 Multiplexer

Claims (1)

(57) [Claims] A first orthogonal transform unit for orthogonally transforming a video signal in a frame ; and a second orthogonal transform unit for orthogonally transforming an inter-frame difference signal of the video signal.
And orthogonally transformed image data by the first orthogonal transforming means and image data orthogonally transformed by the second orthogonal transforming means.
Type and a selection means for selecting whether to quantize either of said orthogonally transformed image data by the first orthogonal transformation image data in the orthogonal transform means and said second orthogonal transform means, the selection Quantizing the image data selected by the means
And means for encoding the quantized image data by the quantization means
Encoding means for storing image data encoded by the encoding means;
And a selection means , wherein the selection means includes an overflow information from the storage means.
Information and the image data orthogonally transformed by the first orthogonal transformation means.
Data and the image data orthogonally transformed by the second orthogonal transformation means.
Select image data based on comparison result of data amount with data
A video signal high-efficiency encoding device.