JPH05111013A - Highly efficient encode for video signal - Google Patents

Abstract

PURPOSE:To improve controllability based upon the centralization of control, to simplify a processing system and to reduce the cost of a hardware by compar ing the information volume of an intra-frame coded video signal with that of an inter-frame coded video signal and selecting the inter-frame coded video signal or the inter-frame coded video signal based upon the compared result. CONSTITUTION:This video signal highly efficient encode has an orthogonal conversion circuit 28 for orthogonally transforming an intra-frame coded video signal, an orthogonal transformation circuit 33 for orthogonally transforming an inter-frame coded video signal and a judging circuit 30 for selecting either one of orthogonally transformed video signals and compares the information volume of the intra-frame coded video signal with that of the inter-frame coded video signal. Thus the intra-frame coded video signal or the inter-frame coded video signal is selected based upon the compared result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal high-efficiency coding apparatus suitable for application to, for example, a so-called video conference system or a video telephone system.

[0002]

2. Description of the Related Art In recent years, there has been proposed a method of combining still image information and moving image information in addition to audio information and transmitting the information to another place.

For example, in a video conference system,
A person who is in a distant place can hold a conference by exchanging audio and video using Iwayu audio-visual (AV) equipment.

When voice information and image information are combined and mutually communicated at distant places like this video conference system, these voice and image information are encoded and transmitted respectively.

The encoding of this image information was performed in December 1990.
Video CODEC (coder, decoder) recommendation H.M., which was established by the International Telegraph and Telephone Consultative Committee (CCITT) under the umbrella of the International Telecommunication Union (ITU) in January. 261 standardized.

The moving picture coding is applied to a standard television or a high definition (H) as a signal source.
D) It is used in fields such as broadcasting and communication as applications involving signal transmission to a remote place using a television, and storage as applications for local signal processing.

Recommendation H. As a video format according to H.261, a common intermediate format (CIF: Common In) that can resolve differences in television systems depending on regions (the whole world) and can communicate between CODECs
terminating format).

The resolution of an image based on this CIF is 35 horizontal pixels.
2, vertical 288 dots.

The structure of the image data to be transmitted has a hierarchical structure as shown in FIG.

That is, in the intermediate format CIF, one picture (each of 1 to 12 in the figure) is G
group of Block (GOB) (1 in the figure
.. 33), one GOB is a macro block composed of luminance information Y and color information CB and CR, and one luminance information Y (1 to 4 in the figure) is a block of 8 pixels × 8 pixels. To be done.

The source coded output, that is, the quantization index of the transform coefficient, the motion vector information, the block type information, etc., is further data-compressed by the variable length coding utilizing the statistical property and then multiplexed into one bit string. It

Further, which of the six blocks forming the above macroblock is effective is coded as a pattern.

The image data sent to the transmission line is provided with macroblock attribute information for each of the six blocks forming the macroblock, and a GOB header is attached for each of the macroblocks forming the GOB. A picture header is attached to each of the GOBs that make up the data set, and the data string is formed.

In the transmission of the image data, the image information of the interpolated frame is formed on the transmitting side and transmitted to the receiving side.

Here, the transmission data DATA is composed of image data which has been subjected to high efficiency coding processing as shown in FIGS. 9 and 10.

[0016] The high-efficiency encoding, for example, as shown in FIG. 9A, the time _{t = t 1, t 2,} t 3 video image PC1 at ......, PC2, PC3 ...... digitally encoded reception side The intra-frame coding process is designed to improve the transmission efficiency by compressing the digital data to be transmitted by utilizing the feature that the video signal has a large autocorrelation during the transmission process. And inter-frame encoding processing is executed.

In the intra-frame encoding process, as shown in FIG. 9A, images PC1, PC2, PC3, ... For example, a difference between pixel data which are adjacent one-dimensionally or two-dimensionally along the horizontal operation line direction is calculated. The desired compression processing is executed, and thus the transmission frame image data having the compressed bit number is formed for the corner images PC1, PC2, PC3 ....

In the inter-frame coding process, as shown in FIG. 9B, the images PC12 and PC23 representing the deviations between the images PC1 and PC2, PC2 and PC3 ...
...... asking, this vector data x ₀ representing the motion of the image, and _{x 1, x 2, x 3} ......, a difference data between sequentially adjacent images, the initial image PC1 at the time t = t ₁
It is transmitted to the receiving side together with the image data (composed of intra-frame encoded data).

Thus, the images PC1, PC2, PC3 ...
It is possible to highly efficiently encode the video signal into digital data having a bit number smaller than that in the case of transmitting all the pixel data and transmit the video signal.

Then, as shown in FIG. 10, the image data to be transmitted is divided into one block by a predetermined number of frames (for example, 10 frames), and the block data ... BL (N-1), BLN, BL (N + 1) ……
Are sequentially subjected to high-efficiency encoding processing, and then transmitted from the transmitting side to the transmission path in that order.

Block data BLN (N = ... N-1,
N, N + 1 ...) are the first frame data D1
Has the intra-frame encoded processing data as
The tenth frame data D2 to D10 includes interframe coding processing data.

Here, the intra-frame encoding process is difference data for all pixels forming an image for one frame, as described with reference to FIG.
The frame image data representing one image is reproduced by sequentially adding the difference data for the frames.

On the other hand, the second to tenth frame data D2 to D10 which are inter-frame coded data are shown in FIG. 9B.
As described above, only the pixel in which the change has occurred in the successive frame images is converted into motion vector data and difference data representing the difference between the inter-frame images.

Thus, in practice, the first frame data D1 constitutes transmission data having relatively low compression efficiency (thus having a large number of bits) by constructing data representing the difference of all pixels for one frame. Against the second
The tenth frame data D2 to D10 constitutes transmission data having a relatively high compression efficiency (and thus having a small number of bits), which represents only the movement between the image data.

FIG. 6 shows a universal communication format using the above-mentioned intermediate format CIF.

That is, as shown in FIG. 6, a video camera 31 having a specification of 625 scanning lines at 50 hertz (for example, PAL system) or a video camera having a specification of 525 scanning lines at 60 hertz (for example, NTSC system). The converter 32 converts the image data captured by the converter 33 into the image data in the CIF format described above.

Then, the image data is encoded and transmitted by the coder 35, and the image data encoded and transmitted by the coder 35 is decoded by the decoder 36 to be CIF.
Convert to image data of the format.

Further, the image data in the CIF format is converted into the original video signal by the converter 37 or 39, and the specification of 625 scanning lines at 50 Hz (for example, P
The video signal converted by the television of the specification (for example, NTSC system) with 525 scanning lines is projected at the television 38 of AL system or 60 hertz.

In the above communication process, Recommendation H.264 is used. The prescribed range of 261 is the range of the coder (encoder) 35 and the decoder (decoder) 36.

An example of the video conference system is shown in FIG. 7, and an example of the video conference system will be described below with reference to FIG.

In FIG. 7, reference numeral 41 denotes a terminal device, which is capable of communicating with another terminal device 42 via a network 43 under the control of another point control unit 44.

The configuration of the terminal device 41 (the configuration of the terminal device 42 is the same as the configuration of the terminal device 41 described below) will be described.

That is, at the time of transmission, the video signal supplied from the video input / output device 45 is supplied to the video codec 46,
This video codec 46 has an intermediate format (CIF)
Image data, filtered for noise removal, etc., and then supplied to the multimedia multiplexer / separator 53.

The device that supplies the image data to the video input / output device 45 may be any device that outputs the image data.

On the other hand, the audio signal from the audio input / output device 48 is also supplied to the audio codec 49, subjected to encoding processing and the like by this audio codec 49, and further delayed for a predetermined time, and then to the multimedia multiplexer / separator 53. Supplied.

Information from the telematic device 51 is also supplied to the multimedia multiplexer / separator 53.

The respective data supplied to the multimedia multiplexer / separator 53 are subjected to multiplexing processing by the multimedia multiplexer / separator 53 under the control of the system control device 52, and thereafter, the network interface. 54
And to the other terminal device 42 via the network 43.

On the other hand, when the transmission signal from another terminal device 42 is received, the multiplexed signal is supplied to the multimedia multiplexer / separator 53 via the network interface 54, and the multimedia multiplexer / separator 53 performs the separation processing. The video data is supplied to the video codec 46, the audio data is supplied to the audio codec 49 via the delay device 50, and the data for the telematic device is supplied to the telematic device 51.

The encoded video data is converted into the original video signal by the video codec 46, and then supplied to, for example, a television (not shown) via the video input / output device 45, and the television is controlled. It is displayed as an image on the surface.

The encoded audio data is converted into an original audio signal by the audio codec 49, and then supplied to, for example, a speaker (not shown) via the audio input / output device 48 and output by the speaker or the like. To be done.

In such a video conference system,
The video codec 46 described above is a video recommendation H.264. It corresponds to the range of 261.

As described above, the codec 46 encodes image data and the like when transmitting image data and the like, and decodes the encoded image data when receiving image data to obtain the original image data. Is.

FIG. 5 shows a block diagram of a transmission side (coder) and a reception side (decoder) of image data, which will be described below.

For the sake of convenience of description, a coder of the transmitting side terminal and a decoder of the receiving side terminal are shown, and the decoder of the transmitting side terminal and the coder of the receiving side terminal are not shown, respectively, not shown as a codec. To do.

In FIG. 5, reference numeral 1 is an input terminal to which a video signal from the video input / output device described in FIG. 7 is supplied. The video signal from the input terminal 1 is converted into a digital video signal by the A / D converter 2. Motion detection
It is supplied to the motion correction circuit 3.

The motion detection / motion correction circuit 3 performs 16 × motion compensation inter-frame prediction based on the digital video signal from the A / D converter 2 and the image data of the previous frame from the frame memory 23 described later. 16 pixels are targeted, and as a result, only the motion information of the digital video signal is supplied to the determination circuit 4.

Based on the overflow information from the buffer 8, the decision circuit 4 decides whether the motion information from the motion detection / motion compensation circuit 3 should be sent in the inter mode or the intra mode.

As described above, the inter mode is a mode in which the difference between preceding and following frames is extracted to obtain an inter-frame difference signal, and the intra mode is a mode in which a lot of information is extracted from one frame to obtain an intra-frame prediction signal. is there.

Then, the data from the judgment circuit 4 is supplied to the orthogonal transformation circuit 5.

The orthogonal transformation circuit 5 orthogonally transforms the data from the judgment circuit 4 into a block size of 8 × 8, and supplies the transformed data to the quantization circuit 6.

By the orthogonal transformation by the orthogonal transformation circuit 5,
The data from the determination circuit 4 (time axis data) is converted to frequency axis data having a small amount of information.

The quantizing circuit 6 quantizes the transformed data from the orthogonal transforming circuit 5 based on the overflow information from the buffer 8 and supplies the quantized image data to the Huffman coding circuit 7.

On the other hand, the image data quantized by the quantizing circuit 6 is also supplied to the inverse quantizing circuit 20, is inversely quantized by the inverse quantizing circuit 20, and then is inversely orthogonal by the inverse orthogonal transform circuit 21. The data is orthogonally transformed, decoded by the decoder (local decoder) 22, and then stored in the frame memory 23.

The image data from the frame memory 23 is supplied to the above-mentioned motion detection / compensation circuit 3 after distortion between blocks is removed by the loop filter 24.

The Huffman encoding circuit 7 encodes the image data from the quantization circuit 7 by giving a short code corresponding to the number of "0".

The image data from the Huffman coding circuit 7 is supplied to the error correction coding circuit 9 via the buffer 8.

The error correction coding circuit 9 carries out error correction addition to the image data from the buffer 8 and copes with noise in the transmission line (corresponding to the network 43 explained in FIG. 7).

The image data from the error correction coding circuit 9 is supplied to a multiplexer 10, and various data other than the image data is variable length coded by the multiplexer 10 and multiplexed into a code string having a predetermined data structure. To do.

The image data from the multiplexer 10 is supplied to the demultiplexer 11 on the receiving side.

The data of the code string multiplexed by the demultiplexer 11 on the receiving side is converted into the original image data, and then supplied to the inverse Huffman coding circuit 13 through the error correction coding circuit 12.

Image data quantized in the inverse Huffman encoding circuit 13 is supplied to the inverse quantization circuit 14 after which the image data on the frequency axis is inversely quantized. It is said that.

The image data on the frequency axis is supplied to the inverse orthogonal transform circuit 14, converted into image data on the time axis, and further supplied to the decoder 16 to be the original image data.
Further, after being temporarily stored in the frame memory 17, it is supplied to the D-A converter 18 and converted into an analog video signal by the D-A converter 18.

The analog video signal is output from the output terminal 1
9 and the video output device 45 described with reference to FIG. 7, and is supplied to a television (not shown) or the like, and is output as a received image on the tube surface.

[0064]

By the way, in the above-mentioned video signal high-efficiency coding apparatus, the decision circuit 4 is provided before the orthogonal transformation circuit 5 orthogonally transforms the determination of inter and intra of the blocks of the input video signal. Is going by.

The determination of inter or intra performed by the determination circuit 4 is controlled by feedback of the remaining amount of the transmission buffer 8 because so-called frame dropping is performed.

On the other hand, also in the quantization circuit 6 in the subsequent stage of the orthogonal transformation circuit 5, control is performed by feeding back the remaining amount of the transmission buffer 8 described above.

All of the above two feedback systems are performed through the system CPU.

Therefore, these two control points are dispersed before and after the orthogonal transformation circuit 5, which causes a problem that control by buffering between the control points becomes complicated.

Further, since the interface with the system CPU is distributed in two places, there is the inconvenience that the processing system becomes complicated and the hardware becomes expensive.

The present invention has been made in view of the above points, and provides a video signal high-efficiency coding apparatus capable of improving controllability by centralizing control, simplifying a processing system, and reducing hardware cost. It is a proposal.

[0071]

A video signal high-efficiency coding apparatus according to the present invention is, for example, as shown in FIGS. 1 to 4, a system 28 for orthogonally transforming an intra-frame coded video signal, and an inter-frame coded system 28. And a selection means 30 for selecting either the intra-frame coded video signal or the inter-frame coded video signal from the two systems. The information amounts of the encoded video signal and the inter-frame encoded video signal are compared, and the intra-frame encoded video signal or the inter-frame encoded video signal is selected based on the comparison result. It is a thing.

[0072]

According to the present invention described above, the information amounts of the intra-frame coded video signal and the inter-frame coded video signal are compared, and based on the comparison result, the intra-frame coded video signal or Since the video signal encoded between the frames is selected, it is possible to improve the controllability by centralizing the control, simplify the processing system, and reduce the hardware cost.

[0073]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the video signal high efficiency coding apparatus of the present invention will be described in detail below with reference to FIG.

In FIG. 1, portions corresponding to those in FIGS. 5 to 11 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numeral 25 denotes an input terminal to which an analog video signal is supplied from a device for outputting an image, and the video signal from the input terminal 25 is supplied to the analog-digital conversion circuit 26.

The analog-digital conversion circuit 26 has, for example, a CPU (not shown) inside, converts the video signal from the input terminal 1 into digital data, and converts the converted digital image data into a still image to be described later. Each of the memories 27a and 27 that constitute the memory 27 when in the mode
Write in b, 27c and 27d respectively.

This analog-digital conversion circuit 26
In the still image mode, sampling is performed for each moving image frame by, for example, a sampling clock having four different phases (meaning that the phase of the sampling clock is shifted) to extract image data of four frames.

Then, for example, the image data a sampled at the first sampling clock is converted into an image identifier (I
D) is written in the memory 27a, the image data b sampled by the second sampling clock is written in the memory 27b by the image identifier, and the image data c sampled by the third sampling clock is written in the memory 27a. Is added to the memory 27c, and the image data d sampled at the fourth sampling clock is added to the memory 27d with an image identifier.

The image data a, b, c and d written in the memory 27 are sequentially read out and supplied to the orthogonal transformation circuit 28 as inter mode data (interframe difference signal).

The orthogonal transformation circuit 28 converts the image data read from the memory 27 or the intra mode image data directly supplied from the analog-digital conversion circuit 26 into the block of 8 × 8 pixels described in FIG. Is used as a unit to convert the data on the time axis into the data on the frequency axis to obtain compressed data with good transmission efficiency, and this image data is supplied to one fixed contact 29a of the switch 29 constituting the determination circuit 30.

On the other hand, the motion detection / compensation circuit 31 performs motion detection and motion compensation of the image data a, b, c and d written in the memory 27 or the image data directly supplied from the analog-digital conversion circuit 26. , Supplied from the frame memory 38 via the loop filter 39
Based on the image data of the previous frame, for example, 16 × 1
The target is 6 pixels.

The moving image data or still image data a, b, c and d from the motion detecting / compensating circuit 31 and the previous image data subjected to the motion detecting / compensating process are sent to the subtracting circuit 32. Each of them is supplied and subjected to subtraction processing by the subtraction circuit 32.

The inter-frame difference signal obtained by the subtraction circuit 32 is supplied to the orthogonal transformation circuit 33 and converted from the time axis data to the frequency data in the same manner as the orthogonal transformation circuit 28 described above. It is supplied to the other fixed contact 29b of 29.

The determination circuit 30 determines, based on the overflow information from the buffer (transmission buffer) 41 and the result obtained by the algorithm for determining whether to transmit the image data in the inter or intra mode, which will be described later.
The movable contact 29c of the switch 29 is connected to the fixed contact 29a or 29b.

That is, when the buffer 41 overflows or when the result obtained by the algorithm is judged to be transmitted in the inter mode, the movable contact 2 of the switch 29 is moved.
9c is connected to the fixed contact 29b and the image data in the inter mode is supplied to the quantizing circuit 34. In other cases, or when it is determined by the algorithm that the image data is to be transmitted in the intra mode, the movable contact 29c of the switch 29 is connected.
Is connected to the fixed contact 29a and the image data in the intra mode is supplied to the quantization circuit 34.

The quantizing circuit 34 quantizes the image data from the judging circuit 30 in the macroblock unit described with reference to FIG. 8, and supplies the quantized image data in the macroblock unit to the Huffman encoding circuit 40. At the same time, it is also supplied to the inverse quantization circuit 35.

The inverse quantization circuit 35 inversely quantizes the image data of the macro block unit from the quantization circuit 34 and supplies the inversely quantized image data to the inverse orthogonal transform circuit 36.

The inverse orthogonal transform circuit 36 transforms the image data on the frequency axis from the inverse quantization circuit 35 into image data on the time axis, and supplies this image data to the decoder 49.

This decoder 49 is an inverse orthogonal transform circuit 48.
Image data is written in the frame memory 38.

The image data written in the frame memory 38 is supplied to the above-mentioned motion detection / compensation circuit 31 via a loop filter 39 for removing distortion components between blocks.

The quantized image data supplied to the Huffman coding circuit 40 is supplied to the error correction coding circuit 42 via the buffer 41.

The image data from the buffer 41 is added with error correction by the error correction coding circuit 42,
After that, it is supplied to the multiplexer 43, multiplexed with other information, and sent to the receiving side.

The demultiplexer 44 on the receiving side obtains image data from the data from the multiplexer 43 and supplies this image data (including the image identifier in the still image mode) to the error correction coding circuit 45.

The image data subjected to the error correction processing in the error correction coding circuit 45 is then supplied to the inverse Huffman coding circuit 46, and the inverse Huffman coding circuit 4 is supplied.
The data is returned to the quantized data at 6, and the inverse quantization circuit 47
To the image data on the frequency axis by the inverse quantization circuit 47.

Then, this image data is processed by the inverse orthogonal transform circuit 4
The data on the frequency axis is converted back to the data on the time axis by 8 and then supplied to the decoder 49.

After the image data is decoded by the decoder 49 and stored in the frame memory 50,
In the still image mode, the selector 51 writes the data in any of the memories 53a, 53b, 53c, and 53d forming the memory 53 based on the identification data attached to each still image data, and in the moving image mode. ,
It is supplied to the DA converter 54 through the selector 51, and is output as an analog video signal by the DA converter 54 through the output terminal 55.

In the still picture mode, the selector 51 uses the control signal from the detection circuit 52 to store the image data read from the frame memory 50 in accordance with the identification data attached to the memories 53a, 53b, 53c.
And 53d.

The detection circuit 52 is the inverse Huffman coding circuit 4
The image identifier added to the image data from 6 detects which of the above-mentioned image data a, b, c, d the image data is, and the selector 51 is responsive to the detection result. Supply control signals.

In the still picture mode, the memory 53
The further read image data a, b, c, and d are converted into an analog video signal by the DA converter 54 as one still image, and the analog video signal is output from the output terminal 55 to an external device (such as a television). ..

Therefore, when this analog still image is displayed on the screen of a monitor or the like, a still image having four times as many pixels as the CIF image, that is, having twice the resolution, is displayed. Become.

Next, the communication flow in the above-mentioned video signal high efficiency coding apparatus will be described with reference to FIG.

In FIG. 2, thin solid arrows indicate the flow of processing, broken arrows with numbers respectively indicate the flow of processing to be repeated, and thick arrows indicate the communication processing between the respective circuits. Show the flow.

First, step 100 of the moving image mode 100.
At a, the command data and the image data from the AD converter 26 are supplied to the error correction coding circuit 42.

At this time, bit 3 of the command signal is set to "0" (release off) and bit 2 is set to "0" (document camera off).

In step 100b, the error correction coding circuit 42 transmits the moving image through the multiplexer 43 in accordance with the above-mentioned command signal, and the completion signal A-
It is supplied to the D converter 26.

Here, the above-described operation, that is, the supply of the command data and the image data by the A / D converter 26 to the error correction coding circuit 42 and the operation of the A / D converter 26 by the error correction coding circuit 42 are performed. The supply of the completion signal is repeated, and the moving image data is transmitted via the multiplexer 44.

Next, in step 200a, the system C
The PU requests the freeze picture to the multiplexer 43.

Then, in step 200b, the multiplexer 43 supplies a control signal for causing the decoder 37 to perform a freeze picture operation in response to a request from the system CPU.

In step 200c, the completion signal from the decoder 37 is supplied to the multiplexer 43, which causes the multiplexer 43 to output a signal indicating this to the system C.
Supply to PU.

At step 200d, the system CPU enters the freeze picture mode.

Next, in step 300a, the system CPU enters the still image mode and a control signal indicating this is supplied to the A / D converter 26.

In step 300b, the A / D converter 26 supplies instruction data indicating a freeze request to the error correction coding circuit 42 in response to a control signal from the system CPU.

That is, bit 3 of this instruction data is set to "0".
(Release off), bit 2 is set to “0” (document camera off), and the codec is forced to generate an insignificant block.

In step 300c, the error correction coding circuit 42 performs a picture freeze operation and supplies a completion signal to the AD converter 26.

Therefore, the image is not updated while the connection is maintained.

Next, in step 400a of the picture freeze mode 400, the AD converter 26 supplies the instruction data to the error correction coding circuit 42 and stores the still image data in the memory 27.

In step 400b, the error correction coding circuit 42 supplies a completion signal to the AD converter 26.

Then, these steps 400a and 400
The operation of b is repeated four times, and the memories 27a, 27b, 2
7c and 27d in this order
stored in a to 27d.

Next, step 50 of the still image mode 500.
At 0a, the AD converter 26 supplies command data for preparing the transmission of a still image to the error correction coding circuit 42.

That is, in the above step 500a,
The document camera signal (FIG. 3B), which is bit 2 of the instruction data, is set to “1” (document camera on) and bit 3 is set to “0” (release off) in synchronization with the vertical synchronization signal shown in FIG. 3A. ).

In step 500b, the error correction coding circuit 42 supplies the A / D converter 26 with a completion signal indicating that the preparation for the still image transmission is completed.

That is, in the above step 500b,
When the completion signal is supplied to the AD converter 26 by the error correction coding circuit 42, the AD converter 26 performs error correction coding on the trigger signal shown in FIG. 3C in synchronization with the vertical synchronization signal shown in FIG. Supply to the circuit 42.

Transmission of the still image data starts from here, but in this example, the first still image frame uses a plurality of moving image frames from a coarse quantization step size to a fine quantization step size. Enables progressive transmission.

That is, only the first still image frame is transmitted in the intra mode for all one moving image frame, and when the quantization step is reduced to the minimum, the next still image frame is transmitted.

Then, similarly, the still image frame is transmitted as an inter frame by using a plurality of moving image frames from a coarse step size to a fine step size.

By repeating such a method,
Send multiple still image data.

From the second frame, since the pixel is adjacent to the immediately preceding frame and the pixel correlation is strong, it is possible to transmit as the inter mode by orthogonal transforming and quantizing only the difference information. ..

That is, when the trigger signal as shown in FIG. 3C is supplied to the error correction coding circuit 42, the still image data of the first frame is read from the memory 27a, and as shown in FIG. 3D, in the intra mode. It is transmitted by the multiplexer 43.

Next, in step 600a of the mode 600 for transmitting the still image data in the inter mode, the A / D converter 26 causes the memories 27a, 17b, 27c,
Image data is sequentially read from 27d and sequentially supplied to the error correction coding circuit 42.

At step 600b, the error correction coding circuit 4 to which the image data is supplied from the A / D converter 26.
2 supplies the A / D converter 26 with a trigger signal as shown in FIG. 3C.

Then, the memories 27a, 27b, 27c,
The still image data read from 27d is transmitted by the multiplexer 43.

As shown in FIG. 3, the error correction coding circuit 4
Every time the trigger signal from FIG. 2 (FIG. 3C) becomes “1”, as shown in FIG. 3D, still image data of the first to fourth frames (only the first frame is initially transmitted in the intra mode). ) Is transmitted sequentially in inter mode.

In this still image data, which memory 27a
The identification data indicating whether or not the data has been read from .about.27d is added and transmitted to the receiving side, that is, the demultiplexer 44.

Then, as described with reference to FIG. 1, after this, the selector 51 determines the identification data of the still image data, so that any of the memories 53a, 53b, 53c and 53d corresponding to this selector 51. Is written into the memory, and after 4 frames are written, it is treated as one still image image data, converted into an analog still image signal by the DA converter 55, and then output through the output terminal 55. It

Then, this analog still image signal is
For example, it is displayed on a tube surface such as a monitor connected to the output terminal 55.

Since the analog still picture image signal projected on the screen of the monitor (not shown) is composed of one still picture image signal by four frames of still picture image data, it is recommended by the video recommendation H261. It has four times as many pixels as the CIF image, that is, twice as much resolution.

In this example, a still image having four times as many pixels as the CIF image of the video recommendation H261 is obtained. However, if the number of pixels is an integral multiple of the number of pixels of this CIF image, the number of pixels is A still image with double the number of pixels can be obtained.

Next, in step 700a of the picture freeze mode 700, the error correction coding circuit 42 supplies the completion signal indicating that the transmission of the still image data is completed to the A / D converter 26.

In step 700b, the AD converter 26 supplies a completion signal to the system CPU and also supplies instruction data to the error correction coding circuit 42.

That is, the codec is forcibly output an insignificant block, and still image data is not transmitted while the connection is maintained.

In step 700c, the system CPU is supplied with a completion signal from the A / D converter 26 to cancel the still image mode.

In step 800a of the moving picture mode 800, the system CPU is set to the moving picture mode and this system CPU supplies the A / D converter 26 with a control signal to that effect.

At step 800b, the AD converter 26 supplies the instruction data to the error correction coding circuit 42 by the control signal from the system CPU.

That is, bit 3 of the instruction data is set to "1" (release on).

In step 800c, the error correction coding circuit 42 enters the moving image mode by the instruction data from the A / D converter 26 and supplies a completion signal to the A / D converter 26.

At step 800d, the command and the image data from the AD converter 26 are supplied to the error correction coding circuit 42, respectively.

That is, as shown in FIG. 3B, bit 2 of the instruction data is set to "0" (document camera off) and bit 3 is set to "0" (release off).

At step 800e, the error correction coding circuit 42 supplies the completion signal to the A / D converter 26, and the image data can be transmitted through the multiplexer 43.

Next, step 900 of the moving image mode 900.
At a, the system CPU supplies a control signal requesting cancellation of the freeze operation of the decoder 37 to the AD converter 26.

At step 900b, the AD converter 26 supplies the instruction data to the error correction coding circuit 42.

That is, bit 2 of the instruction data is set to "0" (document camera off) and bit 3 is set to "1" (release on).

At step 900c, the error correction coding circuit 42 is operated in accordance with the control signal from the AD converter 26.
While stopping the freeze operation of the decoder 37,
A completion signal is supplied to the A / D converter 26.

At step 900d, the image data (moving image data) and the command data from the A / D converter 26 are supplied to the error correction coding circuit 42, respectively.

That is, bit 2 of the instruction data is set to "0" (document camera off) and bit 3 is set to "0" (release off).

In step 900e, the error correction coding circuit 42 supplies a completion signal to the A / D converter 26 and also transmits image data (moving image data) through the multiplexer 43.

Next, the discrimination between the above-mentioned inter and intra modes will be described.

That is, in this example, after the orthogonal transformation is performed, it is determined whether the image data is transmitted in the inter or intra mode.

In this way, the frame dropping and quantizing circuit 3
Since the control of No. 4 can be centralized in one place, the circuit and the like can be easily mounted and the control can be ensured.

To explain the algorithm for discriminating between the inter mode and the intra mode, the operation is performed on the coefficient of the four luminance blocks after the orthogonal transformation by the orthogonal transformation circuit 28 in the macroblock unit described above.

Basically, the square or absolute cumulative value of the AC component of each of the inter and intra corresponds approximately to the code amount after variable-length coding. Therefore, these are compared to each other.

If the change in the luminance of the entire block (DC component of the inter block) is smaller than a certain value, this macro block is likely to be judged as an insignificant block. Make it a block.

This is summarized as follows.

That is, the luminance change in the entire macroblock can be expressed by the following equation 1.

[0164]

[Equation 1]

In addition, AC of inter and intra blocks
The cumulative addition of the absolute values of the components is expressed by the following equations 2 and 3, respectively.

[0166]

[Equation 2]

[0167]

[Equation 3]

However, n is 63.

Then, according to the above equations 1, 2, and 3,
The determination algorithm is as shown in the flowchart of FIG.

The determination algorithm will be described below with reference to the flowchart of FIG.

First, in step 100, the inter DC
It is determined whether ≦ 256 (constant), and if “YES”, the process proceeds to step 110, and if “NO”, step 1
Move to 20.

That is, the DC component of the inter mode is obtained in macro block units, and it is determined whether or not this is a constant 256 or less.

At step 110, the inter mode is set. That is, the image data to be transmitted is set to the inter mode.

That is, here, the determination circuit 30 described in FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29b for the inter mode.

As a result, the inter-mode image data from the orthogonal transformation circuit 33 passes through the switch 29, the quantization circuit 34, the Huffman coding circuit 40, the transmission buffer 41, and the error correction coding circuit 42 of the judgment circuit 30. It is supplied to the multiplexer 43 and transmitted by this multiplexer 43.

In step 120, the inter ACsum
<Intra ACsum is determined. If “YES”, the process proceeds to step 130, and if “NO”, step 14
Move to 0.

That is, the AC component of the image data in the inter mode is obtained in macroblock units, and the absolute value, that is,
Similarly, the AC power of intra-mode image data is calculated in macroblock units, the absolute value, that is, the power weight is calculated, and the power weight of these inter modes is calculated as the power weight of the intra mode. Determine if less than.

At step 130, the inter mode is set. That is, the image data to be transmitted is set to the inter mode.

That is, here, the determination circuit 30 described with reference to FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29b for the inter mode.

As a result, the inter mode image data from the orthogonal transformation circuit 33 is passed through the switch 29, the quantization circuit 34, the Huffman coding circuit 40, the transmission buffer 41, and the error correction coding circuit 42 of the judgment circuit 30. It is supplied to the multiplexer 43 and transmitted by this multiplexer 43.

At step 140, the intra mode is set. That is, the image data to be transmitted is set to the intra mode.

That is, here, the determination circuit 30 described in FIG. 1 connects the movable contact 29c of the switch 29 to the fixed contact 29a for the intra mode.

As a result, the intra mode image data from the orthogonal transformation circuit 28 is passed through the switch 29, the quantization circuit 34, the Huffman coding circuit 40, the transmission buffer 41, and the error correction coding circuit 42 of the judgment circuit 30. It is supplied to the multiplexer 43 and transmitted by this multiplexer 43.

As described above, in this example, when transmitting a still image, a moving image is stored in the memories 27a, 27b, 27c and 27d for four frames, respectively,
Since this is transmitted sequentially, even in the format based on the recommendation of H261, it is possible to transmit an image having a resolution that is an integral multiple of the image of CIF, and orthogonally transform the image data in inter and intra modes. After that, it is determined whether to transmit the image in the inter mode or the image in the intra mode. Therefore, it is possible to concentrate the control points by the feedback from the transmission buffer 41 into one, and the control is centralized. It is possible to improve the system controllability, simplify the processing system, and reduce the hardware cost.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0186]

According to the present invention described above, the information amounts of the intra-frame coded video signal and the inter-frame coded video signal are compared, and the intra-frame coded video is compared based on the comparison result. Since the signal or the inter-frame coded video signal is selected, there is an advantage that the controllability can be improved by the centralized control, the processing system can be simplified, and the hardware cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal high efficiency coding apparatus of the present invention.

FIG. 2 is a diagram showing a communication flow for explaining an embodiment of the video signal high efficiency encoding device of the present invention.

FIG. 3 is a timing chart for explaining an embodiment of the video signal high efficiency encoding apparatus of the present invention.

FIG. 4 is a flow chart for explaining an embodiment of the video signal high efficiency encoding apparatus of the present invention.

FIG. 5 is a block diagram showing an example of a conventional high efficiency encoding device.

FIG. 6 is a diagram showing an outline of a communication system.

FIG. 7 is a block diagram of a videophone system.

FIG. 8 is a diagram showing a structure of image data.

FIG. 9 is an explanatory diagram showing high efficiency encoding.

FIG. 10 is an explanatory diagram showing blocks of image data.

[Explanation of symbols]

 28, 33 Orthogonal transformation circuit 30 Judgment circuit 34 Quantization circuit 40 Huffman coding circuit 41 Transmission buffer 42 Error correction coding circuit 43 Multiplexer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/15 8943-5C 11/04 Z 9187-5C

Claims (1)

[Claims] 1. A system for orthogonally transforming an intraframe-encoded video signal, a system for orthogonally transforming an interframe-encoded video signal, and the intraframe-encoded video signal from the two systems. And selecting means for selecting one of the inter-frame coded video signals, comparing the information amounts of the intra-frame coded video signal and the inter-frame coded video signal, A video signal high-efficiency coding apparatus, wherein the intra-frame coded video signal or the inter-frame coded video signal is selected based on a comparison result.