JP3120535B2 - Video tape recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder and, more particularly, to a video tape recorder which eliminates the need for one of variable-speed playback images, which is a special playback image.

[0002]

2. Description of the Related Art Conventionally, there has been a video tape recorder in which a reproduced video signal is written to a frame memory in a time division multiplexing (TDM) processing unit for each TDM memory map. FIG. 7 shows a TDM memory map of an analog high-definition (HD) video tape recorder among frame memories of such a video tape recorder. In this type of video tape recorder, for example, TDMα and TD are respectively assigned to addresses TDM1 to TDM10 for storing time-division multiplexed data (referred to as TDM data) of four memory maps.
Mβ, TDMγ, TDMδ and TDMa, TDMb, T
DMc and TDMd are written. In FIG. 7, A,
B indicates two channels, and channels A and B are 1A, 2A, 3A, and channels 1B, 2B, 3B,
.., SEG1-4 are 4 for each of channels A and B
5 shows a memory map divided into two.

FIG. 8 is a timing chart showing a phase relationship with respect to a horizontal synchronizing signal in the 2-channel, 4-segment video tape recorder. 8A shows a PLL horizontal synchronizing signal for synchronizing the reproduced video signal in the horizontal direction. FIG. 8B shows a reference for writing TDM information to a predetermined address of the frame memory of FIG. 7 for the PLL horizontal synchronizing signal. It shows a pulse. FIG.
3 shows video data in which TDMα is written at address TDM1 in the memory map of SEG1 of channel A and TDMβ is written in TDM5. FIG. 8D shows FIG.
4 shows video data for writing TDMa at address TDM2 of the memory map of SEG1 of channel A and writing TDMb in TDM6.

[0004]

However, in the conventional video tape recorder, a signal delayed from the pulse generator (not shown) by a predetermined time τ is used as it is in FIG.
When used as the memory write reference pulse shown in (b), video data cannot be reliably stored in a desired TDM memory map at the proper timing. This is because, for example, the memory write reference pulses of the channels 2A and 2B are linked and operate similarly to the memory write reference pulses of the channels 1A and 1B. As a result, for example, the signal that should be displayed on the fifth line on the screen is 1
There was also a risk that the line would shift.

FIGS. 9 and 10 show a case where a signal delayed from a pulse generator (not shown) at the time of special reproduction by a predetermined time τ is directly transferred to one of the screens 51 of a subject using the memory reference pulse shown in FIG. This is an example of the news. FIG. 9 shows an example of an image of a subject leaning on one side when a video signal is reproduced on the screen 51 at a slow speed. FIG. 9 shows a state in which the image is deflected by 4H in the direction of arrow 100 as shown by a chain line 52a with respect to the real image 52 of the subject represented by the solid line. FIG. 10 shows fast forward (Cue) or rewind (Re)
5) shows an example of the deflection of a part of the subject when the image is reproduced in the view (view). In FIG. 10, a chain line 52 corresponds to a real image 52 of a subject represented by a solid line.
As shown by a, the strip portions 102 and 104 show a state in which the image is partially shifted in the vertical direction by 4H. The above-mentioned video tape recorder has a problem that the bias to one side of the reproduced image becomes remarkable at the time of the special reproduction, and it becomes difficult to see in an extreme case. Also, for example,
The memory writing position may be shifted by one line due to vibration of a motor for rotating the capstan.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a video tape recorder capable of eliminating a deviation of a reproduction screen in one direction at the time of special reproduction and allowing a reproduced image to be always viewed at an easily viewable position.

[0007]

Means for Solving the Problems The present invention as means for solving the above problems, a reference pulse generator for generating a pulse to be a reference to write the reproduced video signal to the frame memory, the frame wherein a synchronizing signal generator for generating a horizontal synchronizing signal for reproducing the read video signal from the memory, less than half of one period of each horizontal synchronizing signal in response to the reference pulse outputted from the reference pulse generator pulse every a width, a gate pulse setting unit that sets the first and second gate pulse to continue communicating, the first output from the horizontal synchronizing signal and the gate pulse setting unit that is output from the synchronizing signal generator First based on the gate pulse
A first memory write reference setting section for setting a first timing signal by obtaining a gate output of the above, a horizontal synchronization signal output from the synchronization signal generation section, and a second gate output from the gate pulse setting section A second memory write reference setting unit for setting a second timing signal by obtaining a second gate output based on the pulse; a reference pulse output from the reference pulse generation unit; A phase adjusting section for adjusting the timing of the memory writing reference pulse in accordance with the first and second timing signals output from the memory writing reference setting section; and a phase adjusting section for adjusting the timing in the special reproduction mode. A write control unit that controls writing of the reproduced video signal to the frame memory based on the write reference pulse.

[0008]

A reference pulse generator generates a reference pulse for writing a reproduced video signal to a frame memory , and generates a horizontal synchronizing signal for reading and reproducing video data stored in the memory. Then, the video data is reproduced as a video signal for each frame. In response to the reference pulse output from the reference pulse generator, the gate pulse setting unit sets continuous first and second gate pulses each having a pulse width of less than half of one cycle of the horizontal synchronization signal. , first to obtain a horizontal <br/> synchronizing signal and the first and second gate outputs respectively based on first and second gate pulse output from the gate pulse setting unit that is output from the synchronizing signal generator · a second timing signal, respectively it first
-Set by the second memory writing reference setting unit. Then, the reference pulse output from the reference pulse generator and the first and second
The phase adjustment unit adjusts the output timing of the memory writing reference pulse according to the playback image position information indicated by the output from the memory writing reference setting unit, thereby reducing the visibility due to the bias of the video screen during special playback. To prevent

[0009]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a partial configuration of an embodiment of a video tape recorder of the present invention, and FIG. 2 is a circuit diagram showing a control system of the embodiment of the video tape recorder of the present invention. In these figures, reference numeral 1 denotes a system controller. The system controller 1 synchronizes with a reference pulse generator 1a that generates a pulse 200 serving as a memory writing reference and reproduces a video signal for each TDM memory map of the frame memory 10. Synchronous signal generator 1 for generating signal 201
b, and gate pulse setting units 1c and 1d for setting gate pulses 202 and 203 in response to the reference pulse output from the reference pulse generation unit 1a.

In FIG. 2, one input terminal of an AND circuit 2 which is a first memory write reference setting unit is connected to a gate pulse setting unit 1d, and the other input terminal of the AND circuit 2 is connected to a second memory write reference unit. The first gate pulse 202 and the synchronization signal 201 are connected to one input terminal of the AND circuit 3 serving as the reference setting unit and to the synchronization signal generation unit 1b.
Is entered. The output side of the AND circuit 2 is a latch circuit 4 composed of an RS flip-flop as a state defining unit.
And the logical product output 205 is input to the set terminal of the latch circuit 4 which is the state defining unit. One input terminal of the AND circuit 3 has a synchronizing signal generator 1
b, the synchronization signal 201 is input, the other input terminal of the AND circuit 3 is connected to the gate pulse setting unit 1c, and the second gate pulse is input. The output side of the AND circuit 3 is connected to a set terminal S of a latch circuit 5 composed of an RS flip-flop as a state defining unit, and an AND output 204 is input to the set terminal S of the latch circuit 5.

In FIG. 2, a logical product output 20 as first and second gate pulses output from AND circuits 2 and 3 is shown.
5 and 204 are input to the set terminals S of the latch circuits 4 and 5 as described above. The reset terminals of the latch circuits 4 and 5 are connected to an output terminal ST of a gate pulse detecting unit (not shown) for resetting the latch circuits 4 and 5 in synchronization with the output of the first and second gate pulses. . The output terminals Q of the latch circuits 4 and 5 are connected to one input terminal of a delay circuit 7 which is a phase adjustment unit for adjusting the output timing of the memory write reference pulse. An X signal as a timing signal is output, and a Y signal as a second timing signal is output from an output terminal Q of the latch circuit 5.

In FIG. 2, a reference pulse generator 1a of the system controller 1 is connected to a waveform shaping circuit 6, and a pulse 200, which is a sine wave output shown in FIG. Be shaped. The output terminal of the waveform shaping circuit 6 is connected to the other input terminal of the delay circuit 7, and the waveform-shaped signal is input to the delay circuit 7. In the delay circuit 7 serving as the phase adjusting unit, based on the X and Y signals output from the latch circuits 4 and 5 and the output shaped by the waveform shaping circuit 6, for example, the output timing of four memory write reference pulses Adjust to

[0013] In the delay circuit 7, the X being outputted from the latch circuits 4 and 5, on the basis of the output whose waveform is shaped by the Y signal and the waveform shaping circuit 6, a delay time _{τ7a, (τ + τ H /} 3)
Delay time 7b, (τ−τ _H / 3) delay time 7c and (τ
+ Τ _H / 2) The delay time 7d is delayed, the circuit for leading the phase is switched, and the output timing of the memory write reference pulse is adjusted. Here, τ is PG as shown in FIG.
Τ _H indicates the period of the horizontal synchronizing signal phase-synchronized as shown in FIG. (1) (Adjustment of Timing of Output Timing of Memory Write Reference Pulse in Delay Circuit 1) This is performed by the AND outputs 203 and 204 of the AND circuits 2 and 3, and the AND output 205 of the AND circuit 2 is H (high). ) Level, the latch circuit 4 is operated.
When the AND output 204 of the AND circuit 3 is at the L (low) level, the Y output of the latch circuit 5 is at the L (low) level. At this time, the output timing of the memory write reference pulse is delayed by τ _H. (2) (Adjustment 2 of output timing of memory write reference pulse in delay circuit 7) AND output 205 of AND circuit 2 is at L (low) level, and X output of latch circuit 4 is at L (low) level. And A
When the AND output 204 of the ND circuit 3 is at the H (high) level, the Y output of the latch circuit 5 is at the H (high) level.
At this time, the output timing of the memory write reference pulse is advanced by τ _H. (3) (Adjustment 3 of the output timing of the memory write reference pulse in the delay circuit 7) The AND output 205 of the AND circuit 2 is at the H (high) level, and the X output of the latch circuit 4 is at the H (high) level. When the AND output 204 of the AND circuit 3 is at the H (high) level, the Y output of the latch circuit 5 is at the H (high) level. At this time, the output timing of the memory write reference pulse is delayed by τ _H / 2. (4) (Adjustment 4 of output timing of memory write reference pulse in delay circuit 7) AND output 205 of AND circuit 2 is at L (low) level, and X output of latch circuit 4 is at L (low) level When the AND output 204 of the AND circuit 3 is at the L (low) level, the Y output of the latch circuit 5 is at the L (low) level. At this time, the phase of the output timing of the memory write reference pulse is set to the delay time τ of the memory write reference pulse.
To be kept in the same state.

In FIG. 2, the automatic / shift changeover switch 8 selects the shift changeover mode position 8a in the above-mentioned variable speed reproduction mode, and selects the changeover mode position 8b in the normal reproduction mode. When selecting the shift changeover mode position 8a with the automatic / shift changeover switch 8, the shift changeover mode 8a of the automatic / shift changeover switch 8 is selected.
And one input terminal of the memory write control unit 9 are connected,
The writing of the reproduced video signal to the frame memory 10 is controlled via the memory writing control unit 9 by the clock whose timing has been adjusted by the delay circuit 7.

In FIG. 2, the other input terminal of the memory write control unit 9 is provided with a phase comparison circuit 11, a voltage control type oscillator 1, a frequency divider 13, and a low-frequency three-wave circuit 14 for a phase synchronization circuit ( PLL), which is the output of the frequency divider 13
An L-adjusted horizontal synchronization signal is input. A playback horizontal synchronization (PBH sync) signal is output from a playback synchronization signal generator (not shown) of the system controller 1, and the playback horizontal synchronization signal is input to one input terminal of the phase comparison circuit 11. The voltage output divided by the frequency divider 13 is input to the other input terminal of the phase comparison circuit 11. An output terminal of the phase comparison circuit 11 is connected to an input terminal of the low-pass filter 14 to remove a high-long-wave voltage component. Low pass filter 14
Is connected to the input terminal of the voltage-controlled oscillator 12, and an oscillation signal having a frequency corresponding to the voltage input to the voltage-controlled oscillator 12 is output.

In FIG. 2, the input terminal of the frame memory 10 is connected to the output terminal of the memory writing control unit 9, and the reproduced video signal is shown in FIG. Temporarily write to the desired TDM memory map. An output terminal of the frame memory 10 is connected to an input terminal of the decoder 15, and after a predetermined time, the decoder 15 outputs a desired TDM signal of the frame memory 10.
Read the written video signal from the memory map. Reproduction output circuit 16 is connected to the output terminal of the decoder 15, the luminance signal Y read by the decoder 15, the first color difference signal P _B and the second color difference signal P _R is reproduced output circuit 16
Are output via

FIG. 3 is a timing chart showing the phase relationship between the PLL horizontal synchronizing signal, the memory write reference pulse, and the first and second gate pulses described above for explaining the operation of the embodiment shown in FIGS. is there. FIG. 3A is a timing chart of the PLL horizontal synchronizing signals a to f, in which the interval between bc indicates the time τ _H for one cycle of the PLL horizontal synchronizing signal. This is the output synchronization signal 201. FIG. 3B shows the time τ of the memory write reference pulse, and the pulse 200 output from the synchronization signal generator 1b of the reference pulse generator 1a in FIG.
It is. FIG. 3C shows the first gate pulse, and the first gate pulse output from the gate pulse setting unit 1c in FIG.
The gate pulse 202 of FIG. FIG. 3D shows a second gate pulse, and the gate pulse setting unit 1d of FIG.
Is the second gate pulse 203 output from the second gate pulse. Note that the first gate pulse 202 sets a time τ _G shorter than half the time τ _H for one cycle of the PLL horizontal synchronization signal, and the second gate pulse 201 sets the time after the memory write reference pulse τ. A time τ _G shorter than half of the time τ _H for one cycle of the PLL horizontal synchronization signal is set, and is set continuously.

FIG. 4 shows a memory map of the frame memory 10 shown in FIGS. In the frame memory 10, for example, addresses TDM1 to TDM10 for storing time-division multiplexed data of four memory maps,
DMα, TDMβ, TDMγ, TDMδ and TDMa,
TDMb, TDMc and TDMd 30 to 37 are written. In FIG. 4, A and B indicate two channels. Channels A and B are composed of 1A, 2A, 3A, and channels 1B, 2B, 3B,. It shows a memory map divided into four.

FIG. 5 is a timing chart showing the phase relationship of each part with respect to the horizontal synchronizing signal. FIG. 5A shows a PLL horizontal synchronizing signal for synchronizing a reproduced image in the horizontal direction. FIG. 5B shows a reference for writing TDM data to a predetermined address of the frame memory 10 in FIG. It shows a pulse. FIG. 5C shows FIG.
3 shows video data in which TDMα is written at address TDM1 in the memory map of SEG1 of channel A and TDMβ is written in TDM5. FIG.
4 shows video data for writing TDMa at address TDM2 of the memory map of SEG1 of channel A and writing TDMb in TDM6. The video reproduction data is written to a desired address on the memory map of the frame memory 10 shown in FIGS. 1 and 2 according to the timing indicating the phase relationship of each section with respect to the horizontal synchronization signal.

FIG. 6 shows an H level on a video tape, which can be used for high-definition television. Reference numeral 20 denotes a direction in which the head reads the video tape, and an area 21 indicating a preamble for 3H, in which the ramp signal R and the segment synchronizing signal VL in which the synchronizing signal shown in FIG. , A carrier signal CW is written, and after this preamble, a 136H TDM (TCI) video signal is written. SEG1
ＳSEG4 indicate that the memory map of FIG. 4 is divided into four ranges for each of the two channels A and B. X indicates a control signal.

According to the above-described embodiment, in the special reproduction in the variable speed reproduction mode or the like, the memory write reference pulse shown in FIG.
The position (b) can be set to an ideal position with respect to the PLL horizontal synchronization signal, and the memory writing position can always be set reliably. It is possible to eliminate partial vertical deviation at the time of return. In the above embodiment, the case where the present invention is applied to a high-definition television is described, but it goes without saying that the present invention can be applied to other cases.

[0022]

As described above, according to the present invention, the position of the memory write reference pulse can be set to an optimum position with respect to the horizontal synchronizing signal at the time of special reproduction, and the memory write position is always defined reliably. It is possible to obtain excellent effects such as eliminating vertical deviation in a slow image and partial vertical deviation during fast-forward or rewind.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a partial configuration of an embodiment of a video tape recorder of the present invention.

FIG. 2 is a circuit diagram showing a playback control system of the video tape recorder according to the embodiment of the present invention.

FIG. 3 is a timing chart showing a phase relationship among a PLL horizontal synchronizing signal, a memory write reference pulse, and first and second gate pulses described above for explaining the operation of the embodiment of FIGS. 1 and 2;

FIG. 4 shows a TDM memory map of the frame memory shown in FIGS. 1 and 2;

FIG. 5 is a timing chart showing a phase relationship of each unit with respect to a horizontal synchronization signal used in one embodiment of the present invention.

FIG. 6 is a format example of a video tape used in one embodiment of the present invention.

FIG. 7 shows a memory map of a conventional video tape recorder.

FIG. 8 is a timing chart showing a phase relationship of each unit with respect to a horizontal synchronization signal used in a conventional video tape recorder.

FIG. 9 is a diagram showing an example in which a subject is reproduced by a conventional video tape recorder.

FIG. 10 is a diagram showing an example in which a subject is reproduced by a conventional video tape recorder.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 System controller 1a Reference pulse generator 1b Synchronous signal generator 1c First gate pulse setting unit 1d Second gate pulse setting unit 2 First memory writing reference setting unit 3 Second memory writing reference setting unit 4 , 5 State definition unit 7 Phase adjustment unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5 / 91-5 / 956 H04N 5/782-5/783 G11B 20/02 H04N 9/79-9 / 898

Claims (1)

(57) [Claims] A reference pulse generator for generating a reference pulse for writing a reproduced video signal to a frame memory; and a synchronization signal for generating a horizontal synchronization signal for reading and reproducing the video signal from the memory for each frame. A generating unit; and a gate for setting continuous first and second gate pulses each having a pulse width equal to or less than half of one cycle of the horizontal synchronizing signal in response to the reference pulse output from the reference pulse generating unit. Setting a first timing signal by obtaining a first gate output based on a pulse setting unit and a horizontal synchronization signal output from the synchronization signal generation unit and a first gate pulse output from the gate pulse setting unit A first memory write reference setting unit, a horizontal synchronization signal output from the synchronization signal generation unit, and a second gate pulse output from the gate pulse setting unit A second memory write reference setting unit that obtains a second gate output based on the reference pulse and sets a second timing signal; a reference pulse output from the reference pulse generator; and the first and second memories A phase adjuster for adjusting the timing of the memory write reference pulse according to the first and second timing signals output from the write reference setting unit; and a write adjusted by the phase adjuster in the special reproduction mode. A video tape recorder, comprising: a write control unit that writes and controls a reproduced video signal in the frame memory based on a reference pulse.