JP3115663B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a structure in which a buried layer formed in a semiconductor substrate is contacted and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 5 and 6 show examples of a conventional semiconductor device. FIG. 5 is a cross-sectional view of a main part showing an example of a conventional NPN bipolar transistor. In the figure, 15 is a P-type silicon substrate, 17 is an N ^- type epitaxial growth layer epitaxially grown on a P-type silicon substrate,
-Type silicon substrate 15 and N ⁻ -type epitaxial growth layer 17
Will be referred to as a semiconductor substrate 1 hereinafter. Reference numeral 16 denotes an N ⁺ buried layer provided in the semiconductor substrate 1, which drives a predetermined region of the P-type silicon substrate after an impurity such as antimony (Sb) is implanted at a high concentration. N ^- type epitaxy growth layer 1
7 is embedded in the semiconductor substrate 1 by growing. The 18 is a N ⁺ -type buried lead layer for taking out the potential of the N ⁺ -type buried layer, phosphorus heavily doped as an impurity from a predetermined region on the semiconductor substrate 1, for example the buried layer 16 of the same conductivity type And diffused to reach the N ⁺ type buried layer 16. Reference numeral ² denotes an element isolation insulating film formed using, for example, a selective oxidation method, 5 denotes a P ⁺ -type external base layer for taking out a base electrode, 6 denotes a P ^-- type intrinsic base layer, 7 denotes an N ⁺ -type emitter layer, 11 is an interlayer insulating film, 1
3a to 13c are contact holes, and 14a to 14c are aluminum wirings.

As described above, in the conventional semiconductor device, when a contact electrode is formed in the buried layer 16 formed in the semiconductor substrate 1, a predetermined region on the semiconductor substrate 1 has the same conductivity type as that of the buried layer 16. The impurity is doped and diffused to provide a buried extraction layer 18, a contact hole 13 a is opened for the buried extraction layer 18, and the aluminum interconnection 14 a is received.

FIG. 6 is a sectional view of an essential part showing an example of a conventional P-channel MOS transistor having a well potential extracting region. In the figure, reference numeral 1 denotes a semiconductor substrate such as a P-type silicon substrate, 2 denotes an element isolation insulating film formed by using, for example, a selective oxidation method, 8 denotes an N-type well provided in a predetermined region of the semiconductor substrate 1, Reference numeral 4 denotes an N ⁺ -type buried layer provided in a predetermined region in the semiconductor substrate 1. Here, the N-type well 8 and the N ⁺ -type buried layer 4 are formed, for example, by phosphorus (P) from the entire surface of the semiconductor substrate 1 and the predetermined region on the element isolation insulating film 2 after the formation of the element isolation insulation film 2. Is implanted at several hundred keV and several MeV, respectively, to form a so-called retrograde well structure. At this time, as apparent from the figure, the N ⁺ type buried layer 4 is raised by a surface step difference below the element isolation insulating film 2 to reflect the shapes of the semiconductor substrate 1 and the element isolation insulating film 2. It has a vertical structure. Reference numeral 9 denotes a gate electrode, 10 denotes a P ⁺ -type source and drain region, and 19 denotes an N ⁺ -type well potential extraction region. Here, the N ⁺ -type well potential extracting region 19 is a complementary MOS transistor (CM) in which a P-channel MOS transistor and an N-channel MOS transistor are simultaneously formed.
OS), the N-channel MOS transistor N
^Since it is formed simultaneously with the ⁺ type source and drain regions (not shown), it is necessary to increase the short channel effect resistance of the N-channel MOS transistor. When only a P-channel MOS transistor is formed, the N
^{A +} -type well potential extraction region 19 is formed.
11 is an interlayer insulating film, 13a to 13c are contact holes, and 14a to 14c are aluminum wirings.

As described above, in the conventional semiconductor device, when a contact electrode is formed in the N-type well 8 and the N ⁺ -type buried layer 4 formed in the semiconductor substrate 1, the contact electrode is formed from a predetermined region on the semiconductor substrate 1. The N-type well 8 and the N ⁺ -type buried layer 4 are doped with impurities of the same conductivity type and diffused to provide an N ⁺ -type well potential extraction region 19, a contact hole 13 a is opened, and an aluminum wiring 14 a is provided. I was

[0006]

Since the conventional semiconductor device is configured as described above, for example, the NP shown in FIG.
In the example of the N bipolar transistor, the N ⁺ type buried layer 1 is used.
8 and a P having a well potential extraction region shown in FIG.
In the case of the channel MOS transistor, if it is not a complementary MOS transistor (CMOS), it is necessary to separately provide the N ⁺ -type well potential extraction region 19, and there is a problem that the number of steps increases.

[0007] N ⁺ -type buried layer 16 in the example of the NPN Bas Lee polar transistor shown in FIG. 5, also the P in the example of channel MOS transistor N ⁺ -type buried layer 4 having a well potential extraction region shown in FIG. 6, Since they are not directly connected by a low-resistance layer such as an aluminum wiring, the parasitic resistance increases accordingly. In particular, in the case of a complementary MOS transistor (CMOS), since the N ⁺ -type well potential extraction region can be formed only at a small depth, the parasitic resistance has further increased.

Due to the increase of the parasitic resistance, in the example of the NPN semiconductor bipolar transistor shown in FIG. 5, the saturation operation in the high current region is easily caused by the increase of the resistance of the collector, and the well potential extraction region shown in FIG. In the example of the P-channel MOS transistor having the above, there is a problem that the latch-up resistance is reduced due to an increase in the well resistance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device which does not cause deterioration in characteristics due to an increase in parasitic resistance, and a method for manufacturing the same.

[0010]

The semiconductor device according to the present invention of claim 1 SUMMARY OF THE INVENTION comprises a semiconductor substrate, a transistor and an element isolation insulating film disposed on the semiconductor substrate,
Part at the bottom of the upper Symbol isolation insulating film formed in contact, and the trunk from the bottom of the isolation insulating film
A conductive layer which is continuously formed toward the bottom of the register, and holes made form through the upper <br/> Symbol isolation insulating film, at least partially provided in the upper Kiananai, upper Symbol those having a conductive film formed so as to contact with the conductive layer.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming an element isolation insulating film in a predetermined region on a main surface side of a semiconductor substrate; A transistor between the bottom of the element isolation insulating film and the element isolation insulating film so that a part thereof is in contact with the bottom of the insulating film.
Forming a continuous conductive layer under the formation region; and forming a transistor in the transistor formation region.
And that step, a step of forming a hole reaching the above electrically conductive layer through the element isolation insulating film, at least a portion within the hole and forming a conductive film in contact with the conductive layer Including.

Further, manufacturing how the semiconductor device according to the present invention of claim 3 is the production of a semiconductor device according to claim 2, wherein
In the method, the conductive layer is subjected to high energy ion implantation .
It is obtained so as to more form.

[0013]

In the semiconductor device according to the first aspect of the present invention, the transistor is formed from the bottom of the element isolation insulating film.
Since the conductive layer continuously formed on the lower part of the conductive layer is in contact with the conductive film having a low resistance, it is possible to prevent the deterioration of the characteristics due to the increase in the parasitic resistance as described above.

The semiconductor device according to the invention of claim 2 of the present application
In the method of manufacturing a semiconductor device, since a hole penetrating through the element isolation insulating film and reaching the conductive layer can be formed at the same time as an opening for forming another contact, an example of the NPN bipolar transistor shown in FIG. In the example of the P channel MOS transistor having the N ⁺ buried extraction layer 18 and the well potential extraction region shown in FIG.
If not a complementary MOS transistor (CMOS), N
Only ⁺ type well potential drawing separately providing step region 19 minutes that enables to reduce the number of steps.

A semiconductor device according to a third aspect of the present invention.
In the production method of the body apparatus, by forming using a high energy ion implanting the conductive layer, the formation such that at least partly in contact with the bottom of the easily said isolation insulating film in a single step that enables.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram for explaining a first embodiment of the present invention, and is a cross-sectional view of a main part showing an example of an NPN bipolar transistor. 2 (a) to 2 (d) are main-portion cross-sectional views for explaining the manufacturing process. FIG. 3 is a cross-sectional view of a principal part for describing a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part illustrating an example of a transistor. Fig. 4 (a)
(D) are main-portion cross-sectional views for explaining the manufacturing process.

A first embodiment of the present invention will be described step by step with reference to FIG. As shown in FIG. 2A, an isolation insulating film 2 is formed in a predetermined region on the main surface side of the semiconductor substrate 1.

Next, as shown in FIG. 2 (b), a photoresist film is provided on the entire surface and then patterned to form a mask 3. Using this as a mask, for example, about 1% of phosphorus (P) is implanted by high energy implantation. The N ⁺ -type buried layer 4 is formed by implanting about 1E13 to 1E15 cm ⁻² at about 3 MeV. At this time, as apparent from the drawing, the N ⁺ type buried layer 4 is raised by a surface step difference below the element isolation insulating film 2 to reflect the shapes of the semiconductor substrate 1 and the element isolation insulating film 2. The structure is in contact with the element isolation insulating film 2.

[0019] Then after removing the photoresist film 3 as shown in FIG. 2 (c), P for extraction base electrode
^{The + type} external base layer 5, the P ⁻ type intrinsic base layer 6, and the N ⁺ type emitter layer 7 are sequentially formed by a normal flow.

Next, as shown in FIG. 2 (d), after an interlayer insulating film 11 is provided on the entire surface, a photoresist film is provided on the entire surface and patterned to form 12, which is used as a mask, for example, by an anisotropic etching method. Is used to etch the interlayer insulating film 11 and the element isolation insulating film 2 to simultaneously open the contact holes 13a to 13c. At this time, the bottom of the contact hole 13a reaches the N ⁺ type buried layer 4. Finally, as shown in FIG. 1, for example, aluminum wirings 14a to 14c are provided as a low-resistance conductive film.

In this embodiment, since the low-resistance conductive film is in contact with one conductive layer formed so as to be at least partially in contact with the bottom of the element isolation insulating film, the parasitic resistance is low. Deterioration of characteristics due to an increase in resistance can be prevented.

Further, by forming the conductive layer using high-energy ion implantation, the conductive layer is formed such that at least a portion thereof is easily in contact with the bottom of the element isolation insulating film in a single step. Can be.

Further, since the hole penetrating the element isolation insulating film and reaching the conductive layer can be formed at the same time as the opening for forming another contact, only the step of separately providing the N ⁺ type embedded lead-out layer 18 is required. The number of steps can be reduced.

Next, a second embodiment of the present invention will be described step by step with reference to FIG. Next, FIG.
After a photoresist film is provided over the entire surface as shown in FIG.
About 1E at about 1-3MeV using high energy implantation.
The N ⁺ type buried layer 4 is formed by implanting about 13 to 1E15 cm ⁻² . At this time, as apparent from FIG.
^{Since the +} type buried layer 4 reflects the shapes of the semiconductor substrate 1 and the element isolation insulating film 2, it is raised below the element isolation insulating film 2 by a surface step difference and comes into contact with the element isolation insulating film 2. It has become. Up to this point, the manufacturing method is exactly the same as in the first embodiment.

Next, as shown in FIG. 4C, after the photoresist film 3 is removed, a gate electrode 9 and a P ⁺ type source / drain region 10 of the MOS transistor are sequentially formed by a normal flow.

[0026] After providing the interlayer insulating film 11 on the entire surface as shown in FIG. 4 (d) to the next, the entire surface of 12 is patterned by providing a photoresist film, for example, anisotropic etching method with this as a mask The contact holes 13a to 13c are simultaneously opened by etching the interlayer insulating film 11 and the element isolating insulating film 2 by using. At this time, the bottom of the contact hole 13 has reached the N ⁺ type buried layer 4. Finally, as shown in FIG. 3, for example, aluminum wirings 14a to 14c are provided as a low-resistance conductive film.

In this embodiment, since the low-resistance conductive film is in contact with the conductive layer formed so as to be at least partially in contact with the bottom of the layer-separating insulating film, the characteristic due to an increase in parasitic resistance is obtained. Degradation can be prevented.

Further, by forming the conductive layer using high-energy ion implantation, the conductive layer is formed such that at least a part thereof is easily in contact with the bottom of the element isolation insulating film in a single step. Can be.

Further, since a hole penetrating the element isolation insulating film and reaching the conductive layer can be formed at the same time as an opening for forming another contact, only the step of separately providing the N ⁺ -type well potential extraction region 19 is required. The number of steps can be reduced.

[0030]

As described above , according to the semiconductor device of the first aspect of the present invention , the semiconductor substrate and the semiconductor substrate
Transistor and element isolation insulating film disposed on a plate
So that a part thereof is in contact with the bottom of the element isolation insulating film.
Formed from the bottom of the element isolation insulating film.
Conductive layer continuously formed under the transistor
And a hole formed through the element isolation insulating film,
At least a portion is provided in the hole and is in contact with the conductive layer.
And a conductive film formed so that
In, the effect of the bottom conductive formed to a part is in contact with the layer of the element isolation insulating film, in order to contact the conductive film directly low resistance, can prevent deterioration of characteristics due to an increase in parasitic resistance
There is .

Further, according to the method of manufacturing a semiconductor device according to the invention of claim 2 of the present application, the predetermined area on the main surface side of the semiconductor substrate is determined.
Forming an element isolation insulating film in the region, and forming a transistor between the element isolation insulating film from the bottom of the element isolation insulating film so that a part thereof is in contact with the bottom of the element isolation insulating film. forming a continuous conductive layer under the transistor formation region; and forming a transistor in the transistor formation region.
Forming a hole, forming a hole through the element isolation insulating film to reach the conductive layer, and forming a conductive film so that at least a part of the hole is in contact with the conductive layer. Therefore, a hole that penetrates through the element isolation insulating film and reaches the conductive layer can be formed simultaneously with an opening for forming another contact. In the case of an NPN bipolar transistor, an N ⁺ type buried layer is formed. P-channel M having extraction layer and well potential extraction region
In the case of the OS transistor, the number of steps can be reduced by the number of steps for separately providing an N ⁺ -type well potential extraction region.

A semiconductor according to the invention of claim 3 of the present application.
According to the method of manufacturing a device, the semiconductor device according to claim 2 is provided.
In the manufacturing method, formed as since to form by using a high energy ion implanting the conductive layer, readily at least partly in contact at the bottom of the isolation insulating film and the conductive layer in one step There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps;

FIG. 5 is a cross-sectional view of a principal part showing a first example of a conventional semiconductor device.

FIG. 6 is a cross-sectional view of a principal part showing a second example of a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation insulating film 4 conductive layer 13 a hole 14 a conductive film

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Koji Uga 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. LSI Research Institute (72) Inventor Hiromi Honda 4-1-1 Mizuhara, Itami-shi, Hyogo Address Mitsubishi Electric Corporation, within LSI Laboratories (56) References JP-A-4-269835 (JP, A) JP-A-64-42165 (JP, A) JP-A-2-58864 (JP, A )

Claims (3)

(57) [Claims] 1. A semiconductor substrate, a transistor and an insulating film for element isolation provided on the semiconductor substrate, and formed so as to be partially in contact with a bottom of the insulating film for element isolation; A conductive layer formed continuously from the bottom of the insulating film to the lower part of the transistor; a hole formed through the element isolation insulating film; and at least a part provided in the hole, the conductive layer And a conductive film formed so as to be in contact with the semiconductor device. 2. A step of forming an element isolation insulating film in a predetermined region on a main surface side of a semiconductor substrate; and a step of forming a bottom of the element isolation insulating film so that a part of the insulating film is in contact with the bottom of the element isolation insulating film. From the insulating film for element isolation
Forming a continuous conductive layer in the lower part of the transistor formation region between the two, and forming a transistor in the transistor formation region.
Including the extent, forming a hole reaching the above electrically conductive layer through the element isolation insulating film, a step of at least partially within said hole to form a conductive film in contact with the conductive layer A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein said conductive layer is formed by high-energy ion implantation.