JP3113131B2 - IC logic tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an IC logic tester.
About the over.

[0002]

2. Description of the Related Art After an IC device is manufactured, it is inspected by an IC tester. The IC device to be inspected is a logic IC
In the case of (1), a logic tester is used, and the outline of the configuration will be described with reference to FIG. The IC logic tester shown in FIG. 3 includes a signal generation unit 1, a test circuit 2, and a determination processing unit 3.
It is composed of The signal generator 1 includes a test code generator 11, a threshold setting circuit 12, a pattern generator 13, and a strobe generator 14.
More, the pulse T _P is given synchronized to the pattern generating circuit 13 and the strobe generating circuit 14. Test circuit 2 is 2
Comparator unit 21 composed of comparators 21a and 21b
AND AND COMPOSITION UNIT 2 composed of two AND circuits 22a and 22b
2, and one OR circuit 23 and AND circuit 24 , respectively
But are connected in tandem as shown, the phase inverter 25
The phase adjustment circuit 26 is connected to the output sides of the pattern generation circuit 13 and the strobe generation circuit 14, respectively. Also,
The judgment processing section 3 has a data display 3a. The IC device 4 to be inspected has its input side connected to a test code generation circuit 11.
Next, the output side is connected to the comparator unit 21 for inspection.

[0003] FIG.
A time chart of the sign or pulse signal of each part of the C logic tester is shown, and the inspection method will be described with reference to FIG. When a test instruction is issued to the test code generation circuit 11 by a microprocessor (not shown), for example, three columns of test codes Ta, Tb, and Tc shown in FIG. Are AND-combined to output a binary pulse Pa. However, the test code has a unit code U of unit length t ₀ shown in Ta as a unit,
There are other various types such as Tb and Tc in which n-times are combined in a predetermined arrangement. In testing,
According to the test command, a plurality of sets corresponding to the test codes are selected and input to the IC device 4, and a corresponding serial pulse train is output. The above pulse Pa
Corresponds to the case of one output pulse, and the output pulse Pa will be described below. However, the situation is the same for a plurality of pulse trains.

[0004] The output pulses Pa of the IC device 4 includes two comparators 21a, and 21b of the + terminal - compared to respectively input to the terminals, and the high level threshold from the threshold setting circuit 12 V _H and the low level threshold v _L Then, a high-level H pulse Pb and a low-level L pulse Pc are output and input to the AND circuits 22a and 22b, respectively. The pattern generating circuit 13 generates a pattern signal _PT of a correct pulse train serving as a reference of a pulse train (pulse Pa in this case) output from the IC device 4, and outputs the high-level H pattern signal _PTH to an AND circuit 22a. Then, a low-level L pattern signal _PTL inverted in phase by the phase inverting circuit 25 is _supplied to the AND circuit 22b, and is AND-combined with the pulse Pb and the pulse Pc. Pulse P
If a has the same width as the unit code U and the same phase (that is, normal), the output pulses Pd and Pe of the AND circuits 22a and 22b are both 0, and the OR pulse Pf obtained by OR-combining them with the OR circuit 23 is also obtained. Also, the judgment pulse R, which is 0, and thus AND-combined with the strobe signal ST by the AND circuit 24
Becomes 0, and the IC device 4
Is determined to be good, and a good message is displayed on the data display 3a. Generally speaking, regardless of the configuration of the output pulse train, the decision pulse R for this is 0
(No) is considered as a good condition of the IC device 4, and if it is 1 (Yes), it is determined to be bad, and each message is displayed on the display 3a.

On the other hand, recent IC logic testers have been improved in speed in response to the use of ultra-LSI IC devices, and the test frequency has been reduced to several tens of MHz or less by reducing the width t ₀ of the unit code U. That is all. Therefore, the output pulse Pa has rising and falling portions,
As shown in the figure, the waveforms are distorted due to delay and delay, whereby the pulses Pb and Pc shift in width and phase with respect to the unit code U, and the pulses p _HU and p _H appear in the rising portions of the pulses Pd and Pe. _LU has pulses p _HD and p _{LD in the} falling part
Are generated, and unnecessary pulses p _U and p _D are generated in the OR pulse Pf obtained by OR-combining them. On the other hand, the phase of the strobe signal ST is set substantially at the center of each unit code U by the phase adjusting circuit 26, and this is input to the AND circuit 24 and AND-combined with the pulses p _U and p _D.
However, since the pulses p _U and p _D do not coincide with the strobe signal ST, the determination pulse R becomes 0, and the output pulse P
The IC device 4 is determined to be good irrespective of the waveform distortion of a.

[0006] Figure 5 is a time chart for when the output pulses of the IC device 4 is abnormal, (a) represents the malfunction or noise in the circuit, useless harmful pulse P _EX on the output side of the IC device 4 began springing (B) shows the case where the pulse Pa to be output is missing (MISS). In FIG. 5 (a), the pulses Pb and Pc output from the comparator unit 21 with respect to the source pulse P _EX
Is input to the AND synthesizing unit 21, but the pattern signal _PT has no pulse corresponding to the pulse Pa, and the pattern signal P _TH
Remain at the low level L and the pattern signal _PTL remains at the high level H, so that the same pulses Pd and Pe as the pulses Pb and Pc are input to the OR circuit 23. Its orpulse P
f is AND-combined with the strobe signal ST by the AND circuit 24, a determination pulse R (error pulse e) is generated, which is input to the determination processing unit 3 and the IC device 4 is determined to be defective. It is displayed on the display 3a.

Next, in FIG. 5 (b), when the pulse Pa is missing (MISS), the pulse Pb becomes low level L,
Pc is the high level H, whereas the high level H portion of the pattern signal P _TH corresponding to the pulse Pa, also since the pattern signal P _TL is part of the low level L, as the above-mentioned pulse P _EX Similarly, these AND pulses Pd,
An OR pulse Pf is obtained following Pe, and is further AND-combined with the strobe signal ST to generate a determination pulse R (error pulse e), and the IC device 4 is determined to be defective.

[0008] Next Figure 6, the width is quite narrow gushing Shi pulse P _EX in the of FIG. 5 (a), also showed abnormal case, this case good IC device not be Introduction determination pulse R is May be determined. In FIG. 6, the width of the pulse P _EX is smaller than half the unit length t ₀ of the unit code U,
Assuming that the phase is, for example, in front of the unit code U,
The strobe signal ST is as shown in FIG.
, The AND pulse Pf is not AND-combined with the OR pulse Pf, so that an error pulse e for determination cannot be obtained. In order to detect the OR pulse Pf in this case, the strobe signal ST may be set at a position (b) closer to the front. But pulse P _EX
Appears at an arbitrary phase, so that the position of the strobe signal ST cannot be determined. However, since the distortion of the pulse P _EX is greater at the falling edge, attempts have been made in the past to set the strobe signal ST after the unit code U, but this method is not always perfect.

[0009]

SUMMARY OF THE INVENTION Recent VLSI
With the development of IC devices, it is necessary to inspect IC devices more strictly than before. For example, it is desirable to detect unnecessary pulses p _U and p _D due to the above-described waveform distortion and to inspect the pulses up to the width of the pulse Pa. To this end, it is conceivable to adjust the strobe signal ST to an appropriate phase. However, the pulses p _U and p _D are located at two points, the rising and falling edges of the OR pulse Pf.
The number of strobe signals ST cannot be set near both at the same time. In addition, a narrow source pulse P shown in FIG.
It is desirable to detect _EX, but the OR pulse Pf for this is not always detected by one strobe signal ST as described above. For example, the conventional test circuit is insufficient for strict inspection. The present invention has been made in view of the above, and has a conventional manner of the inspection function measures the width of the output pulse Pa having the waveform distortion, also adding the function of detecting the pulse P _EX out welling narrow It is another object of the present invention to provide a test circuit for inspecting the IC device 4 more strictly than before.

[0010]

SUMMARY OF THE INVENTION The present invention provides an IC logic.
In the above-mentioned IC logic tester, a strobe signal generator is provided which outputs two series of strobe signals, each of which can be adjusted in phase, in synchronization with a cycle of a unit code constituting a test code. The phase of the two series of strobe signals respectively set in the vicinity of them between the rising and falling points of the unit code, strobe both a strobe signal to create a determined pulse and Oaparusu with and synthesis of the additional two series 2 corresponding to the signal
When the judgment unit obtains one judgment pulse, the judgment unit has two series
Pulse of binary pulse with reference to the strobe signal interval
This is to determine the suitability of the width of the thread .

[0011]

In the test circuit described above, the strobe signal generator provided therein outputs two series of strobe signals whose phases can be adjusted in synchronization with the cycle of the unit code constituting the test code. The two series of strobe signals are
The respective phases are set in the vicinity of the rising and falling points of the unit code, and the IC device is determined to be good by the determination pulse of 0 for the normal output pulse as in the conventional case, and the output of the IC device flows out. When the pulse P _EX having substantially the same width as the unit code U and the pulse Pa are missing, respective determination pulses R (error pulse e) are obtained, and the IC device is determined to be defective as in the conventional case. . Further, in the above-described test circuit, when the output pulse Pa of the IC device has a waveform distortion, the unnecessary pulses p _U and p _D generated in the OR pulse Pf are:
The output pulse Pa is detected by one or both of the two strobe signals, and by referring to the interval between the two strobe signals.
Is roughly measured and its suitability is determined. Also,
In the case of a source pulse P _EX ′ having a small width and an arbitrary phase, the OR pulse Pf is detected by one of the strobe signals, and it is determined that there is an abnormality in an IC device or the like.

[0012]

FIG. 1 is a block diagram showing an embodiment of an IC logic tester to which a test circuit 2 'according to the present invention is applied, and FIG. 2 is a view for explaining a part of the operation. The IC logic tester shown in FIG. 1 has the same signal generator 1 as that of FIG. 3 described above, and a test circuit 2 ′ is provided with a strobe generator 27 instead of the phase adjustment circuit 26 of FIG. Necessary functions are added to the judgment processing unit 3. The same components as those in FIG. 3 are denoted by the same reference numerals, and their operations are the same as those in FIG. In FIG. 1, a strobe generating unit 27 includes a strobe generating circuit 14.
Phase adjustment circuit (U) 27a, connected to the phase adjustment circuit
(D) and 27b, made of a multiplexer (MPX) 27c, the strobe signal ST of the strobe generating circuit 14, the phase adjustment circuit 27a, the phase adjustment is input to 27b, a strobe signal ST _U two series from each, ST _D is output and switched by a multiplexer (MPX) 27c and input to the AND circuit 24 alternately. In FIG. 2A, the strobe signal ST _U has a phase of an interval t ₁ with respect to a rising point of the unit code U having a width t ₀ , and the strobe signal ST _D has a phase of an interval t ₂ with respect to a falling point. Is set. Both strobe signal ST _U, interval t ₃ of the ST _D is (t ₀ -t ₁
−t ₂ ), and an output pulse Pa having a waveform distortion or a narrow source pulse P _EX due to the intervals t _{1 to} t _3.
Since the detection is affected, these are appropriately set by a trial experiment or the like. Note that the strobe signals ST _U , ST
_D sets intervals t ₁ and t ₂ in a microprocessor (not shown), and is supplied to each of the phase adjusting circuits 27a and 27b.

The operation of the two strobe signals ST _U and ST _D will be described. The OR pulse Pf output from the OR circuit 23 is described below.
And the two strobe signals ST _U and ST _D are alternately AND-combined by the AND circuit 24, and the normal output pulse Pa of the IC device 4 is determined to be good by the determination pulse R being 0 as in the conventional case. In addition, even if the pulse P _EX flowing to the output side of the IC device 4 and having the same width as the unit code U and the pulse Pa are missing, the error pulse e for each determination is obtained, Similarly I
The C device is determined to be defective. On the other hand, when the output pulse Pa has a waveform distortion, the unnecessary pulses p _U and p _D generated in the OR pulse Pf due to this are as shown in FIG.
(a), the two strobe signals ST _U, taken respectively and ST _D and outputs an error pulse e _U, e _D, in the determination process section 3, both strobe signal ST _U, S
Its width with reference to the interval t ₃ of T _D is measured in the schematic, appropriateness of the width of the output pulse Pa is determined. In the case of the pulse P _EX 'out springing narrower, thereby narrow Oaparusu Pf width produced, as shown in FIG. 2 (b), for example, a strobe signal ST _U and the AND is taken error pulse e _U is output, and it is determined that there is an abnormality such as a circuit of the IC device 4 or noise mixed therein. As described above, the IC device 4 is inspected more strictly than before, and the result is displayed on the data display 3a.

[0014]

As described above, in the test circuit according to the present invention, in addition to the conventional functions, when the output pulse output from the IC device has a distortion, the width of the output pulse is roughly measured to determine whether the output pulse is appropriate. The IC device is provided with a function of judging and detecting a narrow source pulse. IC devices are inspected more strictly than before, and there are excellent devices that contribute to quality control.

[Brief description of the drawings]

FIG. 1 shows a block diagram of an embodiment of an IC logic tester to which a test circuit 2 ′ of the present invention is applied.

FIG. 2 is a diagram illustrating the operation of a test circuit 2 '.

FIG. 3 shows a block diagram of an IC logic tester.

FIG. 4 is a time chart of a code or a pulse signal of each part of the IC logic tester.

Figure 5 shows a time chart for the case the IC device 4 is abnormal, (a) shows the case where the pulse P _EX began springing on the output side of the IC device 4, (b) when the output pulse Pa is missing (MISS) Are respectively shown.

FIG. 6 is a time chart for a narrow source pulse P _EX ′.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal generation part, 11 ... Test code generation circuit, 12 ... Threshold setting circuit, 13 ... Pattern generation circuit, 14 ... Strobe generation circuit, 2 ... Conventional test circuit, 2 '... Test circuit of this invention, 21 ... Comparator Parts, 21a, 21b ... comparator 22 ... AND combining part, 22a, 22b ... AND circuit, 23 ... OR circuit, 24 ... AND circuit, 25 ... phase inversion circuit, 26 ... phase adjustment circuit, 27 ... phase adjustment part, 27a, 27b… Phase adjustment circuit, 27
c ... multiplexer (MPX), 3 ... judgment processing unit, 3a
... Data record display section 4 ... IC device to be inspected, T _a ,
T _b, T _c ... test code, U ... unit code, t ₀ ... unit code width, Pa ... IC device of the output pulse, V _H, V _L ... threshold, Pb, Pc ... comparator output pulses, P _T ... pattern signal, Pd, Pe ... and pulse Pf ... Oaparusu, P _EX ... gushing Shi pulses, P _EX '... pulse out welling narrow, p _U, p _D ... useless pulse, R ... determination pulse,
e, e _U , e _D ... error pulse.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G01R 31/26 H01L 21/66

Claims (1)

(57) [Claims] 1. A plurality of test codes constituted by a combination of unit codes are input in parallel to an IC device having a logic circuit therein, and the codes input in parallel are input to a plurality of test codes.
Output related to the logic operation by the logic circuit
The output as a pulse train of binary serial to the IC device is synchronized with the cycle of the unit code, the outputs compared to each threshold by two comparators, a high level and a low level respective comparator outputs and each pulse, the binary pulse train to the each pulse of high level and a low level of the pulse train of the correctness have 2 values corresponding respectively and synthesized, and oR combining the aND pulses said and synthesis, further wherein A strobe signal is AND-combined with the OR-combined OR pulse to create a decision pulse, and a decision unit decides the presence or absence of the decision pulse. A strobe signal that alternately outputs two sequences of strobe signals that are synchronized with the cycle of the unit code and whose phases can be adjusted. The strobe signal generating unit provided near their between the rising and falling points of the unit code phase of the strobe signal of the two series
Respectively set near to create the result pulse to both said strobe signal the Oaparusu the AND synthesized and, further
Two determinations corresponding to the two series of strobe signals
When the determination unit obtains a pulse, the determination unit
The binary pulse is referred to with reference to the interval of the series strobe signal.
And judging the appropriateness of the width of the scan pulse, I
C logic tester .