JP3112117B2 - Differential transmission circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential transmission circuit used for differentially transmitting data in a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in order to increase the operating speed of a MOS type semiconductor integrated circuit, a differential transmission circuit is required to have a higher transmission speed. Hereinafter, a conventional differential transmission circuit will be described. FIG. 4 shows a circuit diagram of a conventional differential transmission circuit. In FIG. 4 , 0 is a ground terminal and 1 is a power supply terminal. 71 and 72 are complementary input data lines, 73 and 74 are complementary internal data lines, 75 and 76 are complementary output data lines, and 77 and 78 are input data lines 71 and 72. N-channel MOS transistors 79 and 80 received at the gates are used to latch data on internal data lines 73 and 74, respectively.
A latch circuit composed of channel MOS transistors,
81 is an N-channel MOS transistor inserted between the sources of the NMOSs 77 and 78 and the ground terminal 0, 82 and 8
3 is an N-channel MOS transistor receiving the data of internal data lines 73 and 74 at its gate, 84 and 85 are P-channel MOS transistors for latching the data of output data lines 75 and 76
Latch circuit composed of transistors, 86 is NMOS
N-channel MOS transistors 87, 88 and 89 inserted between the sources 82 and 83 and the ground terminal are circuits for precharging the data lines to an arbitrary voltage.

[0003] The constructed differential transmission circuit as described above will be described with reference to FIG. 5 for the operation below. First, before input data is applied to the input data lines 71 and 72, the complementary data lines connected to each other by voltage precharge circuits 87, 88 and 89 are connected to NMOS.
77, 78, 82, and 83 are precharged to a voltage that turns on. Complementary data line potential difference (hereinafter referred to as input data)
Starts to be applied to the gates of the NMOSs 77 and 78,
The NMOSs 81 and 86 are changed from the off state to the on state by a clock signal, and the MOSs of 77, 78, 79 and 80 are changed.
And a differential amplifier circuit composed of MOSs 82, 83, 84 and 85 is operated, and data is transmitted to the internal data lines 73 and 74 and the output data lines 75 and 76. In such a case, at the start of the circuit operation, the NMOS receiving the input data at the gate is already in the ON state, so that the current driving capability of the MOS is large and the clock signal is
As soon as it is applied to 6, the output data is transmitted. For such a differential transmission circuit, for example,
Of Solid State Circuit 24 (1989
Year) 1225, pages 1219 pages (Journal of S o lid-Stat
e Circuits, vol.24 (1989) PP1219-1225).

[0004]

However, in the above-described conventional configuration, the MOSs 81 and 8 operating the differential amplifier circuit are not provided.
When the input data is M
Considering the timing margin, if the voltage is applied earlier than the signal is input to the gates of the OS 77 and 78, the circuit will malfunction, such as generating noise and amplifying and transmitting erroneous data due to imbalance of circuit elements. Then, the timing of the clock signal must be set. In this case, there is a problem that the data transmission speed is governed by the timing of the clock signal, and it is difficult to transmit data at a higher speed.

At the start of operation of the circuit, the NMOS 77,
Since a voltage is applied to the gates of 78, 82, and 83 to turn on all the MOSs, a through current flows from the power supply terminal to the ground terminal during that time, which causes a problem that the current consumption of the circuit increases. Was.

During the precharge period of the data line, the data line is generally connected to the NMOS 77, 78, 82, 8
In order to set the voltage at which all 3 are turned on, the precharge is started after the clock signal for operating the circuit is cut off, and after the precharge is completed, the clock signal is input to turn on the MOSs 81 and 86. Otherwise, a through current will flow from the power supply terminal to the ground terminal. However, such control naturally delays the timing of turning on the MOSs 81 and 86 by the clock signal, which hinders an increase in data transmission speed. As described above, the conventional circuit has a problem that the configuration is such that high speed and low power consumption do not coexist.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a differential transmission circuit which enables high-speed transmission operation and low power consumption of data when transmitting data.

[0008]

In order to achieve this object, a differential transmission circuit according to the present invention comprises a gate having input terminals complementary to each other.
Connected to data line, source connected to power supply terminal,
A pair of rain is connected to complementary internal data lines.
A first P-channel MOS transistor and a gate
Connected to internal data lines complementary to each other, and the source is grounded
Internal drain on the side different from the gate
A pair of first N-channel MOS transistors connected to the data line.
A first differential amplifier circuit comprising a transistor and a gate
Connected to internal data lines complementary to each other, source is grounded
Output data line connected to terminal and complementary drain
Pair of second channel MOS transistors connected to
And a gate connected to the complementary output data line.
The source is connected to the power supply terminal, and the drain is connected to the gate.
Is a pair of second P connected to different side output data lines.
Second differential amplifier comprising a channel MOS transistor
Circuit and said gate connected to complementary input data lines
The turned off first P-channel MOS transistor
A first precharge that charges an input data line to a voltage that causes a state
Charge circuit and an internal data line in which the gates are complementary to each other.
The first and second N-channel MOS transistors connected to
Charge the internal data lines to a voltage at which the transistor turns off.
A second precharge circuit and the gates are complementary to each other.
The second P-channel MO connected to the output data line
Connect the output data line to the voltage at which the S transistor turns off.
And a third precharge circuit for charging.
It shall be the.

[0009]

With this structure, before the input data is applied, the input data line and the output data line are precharged to the power supply voltage and the internal data line is precharged to the ground voltage, respectively. MO is fluctuation
When the threshold voltage of the S transistor is exceeded, the MOS transistor receiving the data at the gate is immediately turned on and the data is transmitted to the output side, so that the operation speed of the circuit is not governed by the timing of the clock signal. High-speed data transmission can be achieved. In addition, the differential transmission circuit consumes current for the data line on the side where the voltage applied to the gate fluctuates only during the operation of the circuit, so that the current consumption of the circuit can be reduced.

[0010]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1A is a circuit diagram of a differential transmission circuit according to the first embodiment, and FIG. 1B is a circuit diagram of a precharge circuit according to the first embodiment.

In FIG. 1A, 0 is a ground terminal, 1 is a power supply terminal, 2 and 3 are input data lines complementary to each other, 4 and 5
Are complementary internal data lines, 6 and 7 are complementary output data lines, 8 and 9 have gates connected to input data lines 2 and 3, source is connected to power supply terminal 1, and drain is internal data line 4 P-channel MOS transistors 10 and 11 are connected to internal data lines 4 and 5, have a source connected to ground terminal 0, and have a drain different from the internal data line connected to the gate. N-channel MOS transistors 12 and 13 connected to internal data lines 4 and 5 forming a latch circuit for internal data lines 4 and 5 have gates connected to internal data lines 4 and 5 and sources connected to ground terminal 0, respectively. N-channel MOS transistors having drains connected to output data lines 6 and 7, gates connected to output data lines 6 and 7, and sources connected to power supply terminal 1. P-channel MOS transistors whose drains are connected to output data lines on the side different from the output data line to which the gates are connected to form a latch circuit for output data lines 6 and 7 are input terminals 16 and 18, respectively. A precharge circuit for charging data lines 2 and 3 and output data lines 6 and 7 to a power supply voltage, and 17 is a precharge circuit for discharging internal data lines 4 and 5 to a ground voltage.

A1 is a pair of PMOSs 8, 9 whose gates are connected to input data lines 2, 3 complementary to each other, whose source is connected to the power supply terminal 1, and whose drains are connected to internal data lines 4, 5 complementary to each other. And a pair of NMOSs 10 and 10 whose gates are connected to the internal data lines 4 and 5 complementary to each other, whose source is connected to the ground terminal 0 and whose drain is connected to the internal data lines 4 and 5 on the side different from the gate. 11 is a first differential amplifier circuit.

A2 is a pair of NMOSs 12 whose gates are connected to the complementary internal data lines 4 and 5, whose sources are connected to the ground terminal 0, and whose drains are connected to the complementary output data lines 6 and 7. , 13 and a pair of gates connected to the complementary output data lines 6 and 7, a source connected to the power supply terminal 1, and a drain connected to the output data lines 6 and 7 on the side different from the gate. PMOS14,1
5 is a second differential amplifier circuit.

In FIG. 1B, 19, 20, 21
Is a P-channel MO constituting the precharge circuit 16
S transistors, 22, 23, and 24 are precharge circuits 1
7, an N-channel MOS transistor,
5, 26 and 27 are P constituting the precharge circuit 18.
It is a channel MOS transistor.

The operation of the differential transmission circuit configured as described above will be described with reference to FIG. FIG. 2 shows the waveforms of the input data line, the internal data line, and the output data line. The X-axis shows time, and the Y-axis shows the amplitude of the data line. First, before the input data is applied to the input data lines 2 and 3, the precharge circuit sets the input data lines 2 and 3 and the output data lines 6 and 7 to the power supply voltage and the internal data lines 4 and 5 to the ground voltage in advance. It is precharged using 16 to 18. When the precharge circuit is released, the transistors 8, 9, 12, and 13 receiving data at the gates are turned off, so that the differential transmission circuit does not operate and waits for input data to be applied. . When input data is applied to the input data lines 2 and 3 and one of the voltages 2 and 3 drops by more than the threshold value of the PMOS, the PMOS is immediately turned on and the internal data line to which the drain is connected is connected. Start charging 4 or 5.
As soon as the voltage of the internal data line exceeds the threshold voltage of the NMOS, the NMOS turns on, discharges the charge of the output data line, and transmits data to the output data line.

As described above, in the present embodiment, when data is transmitted, the transmission speed is not dominated by the clock signal, so that the data transmission speed can be increased. The differential transmission circuit operates at the power supply terminal 1 during operation.
Since at least one MOS transistor on the path from the power supply terminal to the ground terminal 0 is in the off state, a through current does not flow from the power supply terminal to the ground terminal, so that current consumption can be reduced. When the present embodiment is used for a data read amplifier of, for example, a 64 megabit dynamic random access memory, the data read amplifier has 20 to
30% higher speed and 30-50% lower power consumption are achieved.

During the precharge period of the circuit, when an intermediate voltage is applied to the gate of the MOS transistor due to the equalization of the data line and a through current may flow from the power supply terminal to the ground terminal, the P-channel MOS transistor 8 and the 9 between the source and the power supply terminal and between the sources of the N-channel MOS transistors 12 and 13 and the ground terminal. It goes without saying that the effect of the differential transmission circuit of the example is the same.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram of a differential transmission circuit similar to that of FIG. 1. The same parts as those of FIG. 1 are denoted by the same reference numerals, and detailed description is omitted. FIG. 3 differs from FIG. 1 in that a signal whose gate has only a decoding function is provided between the sources of P channel MOS transistors 8 and 9 and the power supply terminal and between the sources of N channel MOS transistors 12 and 13 and the ground terminal. The point is that the MOS transistors 28 and 29 of the switches connected to the lines are inserted.

The operation of the differential transmission circuit configured as described above will be described below. When an output of a specific data line is selected from a plurality of data lines and used, a switch having a decoding function is generally inserted into the output data line. However, in this case, the differential transmission circuit that transmits data that is not actually used also operates, so that current consumption increases. In the present embodiment, by inserting a switch of a MOS transistor whose gate is connected to a signal line having only a decoding function between a source and a power supply of a differential amplifier circuit, a differential transmission circuit of an actually operating differential transmission circuit is inserted. The operation speed and the current consumption have exactly the same effects as in the first embodiment, and the differential transmission circuit connected to the unused data line is not operated, so that the current consumption can be reduced accordingly. For example, when one set of data lines is decoded and used from two sets of data lines, the current consumption of the differential transmission circuit is halved.

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

As described above, the present invention provides a large capacity MO such as a DRAM (dynamic random access memory) or an SRAM (static random access memory).
In an S-type semiconductor integrated circuit, it is possible to realize a differential transmission circuit having an excellent effect on high-speed data transmission and low power consumption of a circuit when transmitting data differentially.

[Brief description of the drawings]

[1] (a) Schematic (b) circuit diagram of the precharge circuit of the differential transmission circuit according to a first embodiment of the present invention

FIG. 2 is a waveform chart for explaining the operation of the differential transmission circuit in the embodiment.

FIG. 3 is a circuit diagram of a differential transmission circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional differential transmission circuit.

FIG. 5 is a waveform chart for explaining the operation of the conventional differential transmission circuit .

[Explanation of symbols]

0 Ground terminal 1 Power supply terminal 2, 3 Input data line 4, 5 Internal data line 6, 7 Output data line 8, 9 P-channel MOS transistor 10, 11, 12, 13 N-channel MOS transistor 14, 15 P-channel MOS transistor 16 , 17,18 Precharge circuit

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI H04L 25/02 (72) Inventor Atsushi Fujiwara 1006 Ojidoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References Special JP-A-61-96587 (JP, A) JP-A-59-154691 (JP, A) JP-A-57-82286 (JP, A)

Claims (2)

(57) [Claims] A pair of first P-channel MOS transistors each having a gate connected to a complementary input data line, a source connected to a power supply terminal, and a drain connected to a complementary internal data line; Are connected to the internal data lines complementary to each other, the source is connected to the ground terminal,
A first differential amplifier circuit including a pair of first N-channel MOS transistors having a drain connected to an internal data line on a side different from the gate, a gate connected to the internal data lines complementary to each other; A pair of second channel MOS transistors each having a source connected to the ground terminal, a drain connected to the complementary output data line, a gate connected to the complementary output data line, and a source connected to the power supply terminal. A second differential amplifier circuit composed of a pair of second P-channel MOS transistors whose drains are connected to an output data line on the side different from the gate, and the gates are connected to complementary input data lines. A first precharge circuit for charging an input data line to a voltage at which the first P-channel MOS transistor is turned off; Second precharge circuit, wherein the gate is mutually complementary output data lines to charge the internal data line to the voltage connected to said auxiliary internal data line and the first and second N-channel MOS transistor is turned off And a third precharge circuit for charging an output data line to a voltage at which the second P-channel MOS transistor is turned off. 2. The first differential amplifier circuit according to claim 1, wherein
Between the source of the P-channel MOS transistor and the power supply terminal and the second N-channel MOS of the second differential amplifier circuit.
A differential transmission circuit, wherein a switch of a MOS transistor whose gate is connected to a signal line having a decoding function is inserted between a source of the transistor and a ground terminal.