JP3112113B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3112113B2 JP3112113B2 JP04050462A JP5046292A JP3112113B2 JP 3112113 B2 JP3112113 B2 JP 3112113B2 JP 04050462 A JP04050462 A JP 04050462A JP 5046292 A JP5046292 A JP 5046292A JP 3112113 B2 JP3112113 B2 JP 3112113B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- main surface
- external
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】この発明は、リードフレームを有
する半導体装置に関し、特に外部と接続する外部リード
の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a lead frame, and more particularly to an improvement in an external lead connected to the outside .
【０００２】[0002]
【従来の技術】図１１、１２は従来の半導体装置を示す
図であり、図１１は構成を示す斜視図、図１２は断面図
である。図において、１は銅や鉄ニツケル合金などの金
属板を打ち抜き、成形加工が施されたリードフレーム、
このリードフレーム１は半田付けやワイヤボンドのボン
ディング性を向上するためにニツケルや錫などのメッキ
６が施されている。８は半導体チップで、リードフレー
ム１の所定の位置に半田付けや導電性の樹脂等７でダイ
ボンドされている。９は半導体チップ８と外部リード１
ａとを接続した金やアルミニュームなどのワイヤ、２は
リードフレーム１の外部との接続部を残して半導体チッ
プ８を覆う外装樹脂で一般にエポキシ樹脂が用いられて
いる。2. Description of the Related Art FIGS. 11 and 12 are views showing a conventional semiconductor device, FIG. 11 is a perspective view showing the structure, and FIG. 12 is a sectional view. In the drawing, reference numeral 1 denotes a lead frame formed by punching a metal plate such as copper or an iron nickel alloy, and performing a forming process.
The lead frame 1 is plated with nickel, tin, or the like 6 in order to improve the solderability and the bonding property of wire bonding. Reference numeral 8 denotes a semiconductor chip, which is die-bonded to a predetermined position of the lead frame 1 by soldering or conductive resin 7. 9 is a semiconductor chip 8 and external leads 1
A wire 2 such as gold or aluminum connected to a is an exterior resin for covering the semiconductor chip 8 except for a connection portion with the outside of the lead frame 1, and an epoxy resin is generally used.
【０００３】次に動作について図６〜図１０を用いて説
明する。上記のように構成された半導体装置（図６）
は、基板５に取り付けられるように外部リード１ａの折
り曲げ（フォミング）が行われる（図７）。次に、図８
に示すように、外部リード１ａを基板５の接続電極５ａ
に挿入し、半導体装置を基板５の定位置に配置する。次
に、図９に示すように半田１０を用いて外部リード１ａ
と接続電極５ａとを接続し、次に図１０に示すように、
基板５の裏面に突出した外部リード１ａの切り揃えが行
われる。Next, the operation will be described with reference to FIGS. Semiconductor device configured as described above (FIG. 6)
The external leads 1a are bent (formed) so as to be attached to the substrate 5 (FIG. 7). Next, FIG.
As shown in FIG. 5, the external lead 1a is connected to the connection electrode 5a of the substrate 5.
And the semiconductor device is arranged at a fixed position on the substrate 5. Then, the external lead 1a by using solder 10 as shown in FIG. 9
And the connection electrode 5a, and then, as shown in FIG.
The external leads 1a protruding from the back surface of the substrate 5 are trimmed.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置のリ
ードフレームは以上のように構成されているので、半導
体装置を基板５に取り付けるとき、外部リード１ａの成
形や外部リード１ａの形状に合った接続電極５ａが必要
で、さらに、外部リード１ａと接続電極５ａとの接続は
半田１０に依存しなければならず、接続後に外部リード
１ａの切り揃えが必要である。このため、作業工程が多
いという問題点があった。Since THE INVENTION Problems to be Solved by the lead frame of the conventional semiconductor device is constructed as above, when mounting the semiconductor device on the substrate 5, appropriate to the shape of the molding or the external lead 1a of the external lead 1a The connection electrode 5a is required, and the connection between the external lead 1a and the connection electrode 5a must depend on the solder 10. After the connection, the external lead 1a needs to be aligned. For this reason, there was a problem that there were many work processes.
【０００５】この発明は上記のような問題点を解消する
ためになされたもので、作業工程を減少し得るようにし
たリードフレームを得ることを目的とする。[0005] The present invention has been made to solve the above problems, and has as its object to obtain a lead frame capable of reducing the number of working steps.
【０００６】[0006]
【課題を解決するための手段】この発明にかかる半導体
装置は、基板の主面に樹脂封止型半導体素子と配線電極
とを設け、前記樹脂封止型半導体素子の外部リードを前
記配線電極に接合した半導体装置において、前記配線電
極に前記基板の主面と間隔をおいて電極主面を設け、こ
の電極主面に前記外部リードを重ね合わせると共に、前
記外部リードと前記配線電極とを溶接したものである。
この発明に係る半導体装置は、また、外部リードの先端
が電極主面上に位置するようにしたものである。この発
明に係る半導体装置は、更に、電極主面を基板の主面と
ほぼ平行に形成すると共に、外部リードを直線状にした
ものである。A semiconductor device according to the present invention comprises a resin-encapsulated semiconductor element and a wiring electrode on a main surface of a substrate.
With the external leads of the resin-encapsulated semiconductor element facing forward.
In the semiconductor device bonded to the wiring electrode,
An electrode main surface is provided on the pole at an interval from the main surface of the substrate, and
Superimpose the external lead on the electrode main surface of
The external lead and the wiring electrode are welded .
The semiconductor device according to the present invention may further include a tip of an external lead.
Are located on the main surface of the electrode . The semiconductor device according to the present invention may further include a main surface of the electrode and a main surface of the substrate.
The outer leads are formed substantially parallel and the external leads are linear .
【０００７】[0007]
【作用】この発明における半導体装置は、配線電極と外
部リードとの接続を、半田に依存しない溶接としたこと
に加えて、配線電極をブロック化することができ、この
配線電極の電極主面に重ね合わせた外部リードを溶接装
置の電極で配線電極に押圧して溶接するため、基板に対
する応力集中を緩和することができ、結果的に基板を薄
くすることができる。 また、外部リードの先端が電極主
面上に位置することで、先端を切り揃える作業が不要と
なり、製造工程が簡単で生産性に優れるだけでなく、外
部リードを切り揃える場合に生ずる外部リードの電極主
面との接合部への応力を皆無とすることができる。ま
た、外部リードの先端が配線電極の周囲のスペースを無
用に占拠することもない。更に、半導体素子が基板にほ
ぼ平行に配置されることで、基板を含め総体的にコンパ
クトに半導体装置を構成することができる。According to the semiconductor device of the present invention, the wiring electrode is
The connection with the lead is made welding independent of solder
In addition, wiring electrodes can be blocked,
External leads superimposed on the electrode main surface of the wiring electrode are welded
Since the electrodes are pressed against the wiring electrodes and welded,
Stress concentration can be reduced, resulting in a thin substrate.
Can be done. Also, the tip of the external lead is
Positioning on the surface eliminates the need to trim the tip
Not only is the manufacturing process simple and productive, but also
Main electrode of external lead generated when trimming external leads
The stress on the joint with the surface can be completely eliminated. Ma
Also, the tip of the external lead leaves no space around the wiring electrode.
There is no occupation for use. Further, by arranging the semiconductor element substantially in parallel with the substrate, the semiconductor device can be configured to be compact as a whole including the substrate.
【０００８】[0008]
【実施例】実施例１． 以下、この発明の実施例１を図について説明する。図４
はこの発明の実施例１による半導体素子の断面図であ
る。図において、１はリードフレーム、１ａは外部と接
続される外部リードで、溶接可能な材質で構成され、直
線状とされている。６はリードフレーム１と外部リード
１ａとの所要の部分に施されたメッキ層、８は半導体チ
ップで、半田または導電性樹脂７でリードフレーム１の
所定の位置に取り付けられている。９は半導体チップ８
と外部リード１ａとを接続するワイヤで、外部リードと
の接続は、図４に示されるように、メッキ層６の部分で
行われる。このように構成されたものは、リードフレー
ム１と外部リード１ａの外部との接続部を残して半導体
チップ８を覆うように外装樹脂２で成形され、図１に示
す半導体素子が形成される。ここで、外部リード１ａの
外部との接続部にはメッキは施されず、素材面が露出し
ている。[Embodiment 1] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG.
1 is a sectional view of a semiconductor device according to Embodiment 1 of the present invention. In FIG, 1 is a lead frame, 1a denotes an external lead connected to an external, is constituted by weldable materials, straight
It is linear . Reference numeral 6 denotes a plating layer applied to required portions of the lead frame 1 and the external leads 1a. Reference numeral 8 denotes a semiconductor chip, which is attached to a predetermined position of the lead frame 1 by solder or conductive resin 7. 9 is a semiconductor chip 8
The connection between the external lead 1a and the external lead 1a is made at the plating layer 6 as shown in FIG. The semiconductor device shown in FIG. 1 is formed in such a structure as to cover the semiconductor chip 8 except for the connection between the lead frame 1 and the outside of the external lead 1a. Here, the connection portion of the external lead 1a with the outside is not plated, and the material surface is exposed.
【０００９】次に動作について図１〜図３を用いて説明
する。上記のように構成された図１の半導体素子は、図
２に示すように基板５の主面の所定位置に配置され、同
様に基板５の主面に設けられた配線電極４の電極主面上
に外部リード１ａの先端が載せられ、溶接電極３によっ
て外部リード１ａが配線電極４の電極主面に押圧され、
スポット溶接で接続される。配線電極４の電極主面は図
２、図３に示すように基板５の主面と間隔をおいて設け
られ、しかも基板の主面とほぼ平行に形成されているた
め、スポット溶接終了後における外部リード１ａと配線
電極４との接続状態及びこれらと基板５との位置関係は
図３に示すように半導体素子が基板５の主面とほぼ平行
に配置される。なお、配線電極４と基板５との接続を外
部リード１ａと配線電極４との接続と同時に行なっても
よい。Next, the operation will be described with reference to FIGS. The semiconductor device of FIG. 1 configured as described above is arranged at a predetermined position of the main surface of the substrate 5, as shown in FIG. 2, the
The tip of the external lead 1a is placed on the electrode main surface of the wiring electrode 4 provided on the main surface of the substrate 5 as described above, and the external lead 1a is pressed against the electrode main surface of the wiring electrode 4 by the welding electrode 3. And
Connected by spot welding. The electrode main surface of the wiring electrode 4 is a figure.
2. Provided at an interval from the main surface of the substrate 5 as shown in FIG.
And is formed substantially parallel to the main surface of the substrate.
Therefore, the connection state between the external lead 1a and the wiring electrode 4 after the end of the spot welding and the positional relationship between these and the substrate 5 are as follows.
As shown in FIG. 3, the semiconductor element is substantially parallel to the main surface of the substrate 5.
Placed in The connection between the wiring electrode 4 and the substrate 5 may be made simultaneously with the connection between the external lead 1a and the wiring electrode 4.
【００１０】[0010]
【発明の効果】以上のようにこの発明によれば、配線電
極と外部リードとの接続を、半田に依存しない溶接とし
たことに加えて、配線電極をブロック化することができ
る。また、外部リードの先端が電極主面上に位置するこ
とで、先端を切り揃える作業が不要となり、製造工程が
簡単で生産性に優れるだけでなく、外部リードを切り揃
える場合に生ずる外部リードの電極主面との接合部への
応力を皆無とすることができる。また、外部リードの先
端が配線電極の周囲のスペースを無用に占拠することも
ない。更に、半導体素子が基板にほぼ平行に配置される
ことで、基板を含め総体的にコンパクトに半導体装置を
構成することができる。As described above, according to the present invention, the connection between the wiring electrode and the external lead is made by welding independent of solder, and the wiring electrode can be blocked . In addition, since the tip of the external lead is located on the main surface of the electrode, the work of trimming the tip is not required, which not only simplifies the manufacturing process and is excellent in productivity, but also reduces the external lead generated when trimming the external lead. The stress at the joint with the electrode main surface can be completely eliminated. Further, the tip of the external lead does not unnecessarily occupy the space around the wiring electrode. Further, by arranging the semiconductor element substantially in parallel with the substrate, the semiconductor device can be configured to be compact as a whole including the substrate.
【図１】この発明の実施例１による半導体装置の外観図
である。FIG. 1 is an external view of a semiconductor device according to a first embodiment of the present invention.
【図２】この発明の実施例１による半導体装置の溶接状
態図である。FIG. 2 is a welding state diagram of the semiconductor device according to the first embodiment of the present invention.
【図３】この発明の実施例１による半導体装置の溶接終
了後の外観図である。FIG. 3 is an external view of the semiconductor device according to the first embodiment of the present invention after welding is completed.
【図４】この発明の実施例１による半導体装置の構造を
示す断面図である。FIG. 4 is a sectional view showing the structure of the semiconductor device according to Embodiment 1 of the present invention;
【図５】この発明の実施例２による半導体装置の外観図
である。FIG. 5 is an external view of a semiconductor device according to a second embodiment of the present invention.
【図６】従来の半導体装置の外観図である。FIG. 6 is an external view of a conventional semiconductor device.
【図７】従来の半導体装置のフォーミングを示す外観図
である。FIG. 7 is an external view showing forming of a conventional semiconductor device.
【図８】従来の半導体装置の取り付け作業を示す外観図
である。FIG. 8 is an external view showing a mounting operation of a conventional semiconductor device.
【図９】従来の半導体装置の接続作業を示す外観図であ
る。FIG. 9 is an external view showing a connection operation of a conventional semiconductor device.
【図１０】従来の半導体装置の接続後のリードカットを
示す外観図である。FIG. 10 is an external view showing a lead cut after connection of a conventional semiconductor device.
【図１１】従来の半導体装置の構造を示す斜視図であ
る。FIG. 11 is a perspective view showing the structure of a conventional semiconductor device.
【図１２】従来の半導体装置の構造を示す断面図であ
る。FIG. 12 is a cross-sectional view illustrating a structure of a conventional semiconductor device.
１ リードフレーム、 １ａ リード、 ２ 外
装樹脂、３ 溶接電極、 ４ 配線電極、
５ 基板。1 lead frame, 1a lead, 2 exterior resin, 3 welding electrode, 4 wiring electrode,
5 Substrate.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−73750（ＪＰ，Ａ) 特開 昭56−169338（ＪＰ，Ａ) 特開 平３−154317（ＪＰ，Ａ) 特開 平４−10610（ＪＰ，Ａ) ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-62-73750 (JP, A) JP-A-56-169338 (JP, A) JP-A-3-154317 (JP, A) JP-A-4- 10610 (JP, A)
Claims (3)
線電極とを設け、前記樹脂封止型半導体素子の外部リー
ドを前記配線電極に接合した半導体装置において、前記
配線電極に前記基板の主面と間隔をおいて電極主面を設
け、この電極主面に前記外部リードを重ね合わせると共
に、前記外部リードと前記配線電極とを溶接したことを
特徴とする半導体装置。1. A resin-encapsulated semiconductor device is provided on a main surface of a substrate.
A wire electrode, and an external lead of the resin-encapsulated semiconductor element.
A semiconductor device in which a gate is joined to the wiring electrode,
An electrode main surface is provided on the wiring electrode at a distance from the main surface of the substrate.
When the external lead is superimposed on the main surface of the electrode,
Wherein the external lead and the wiring electrode are welded .
るようにしたことを特徴とする請求項１記載の半導体装
置。2. The tip of the external lead is located on the main surface of the electrode.
The semiconductor device according to claim 1, wherein:
すると共に、外部リードを直線状にしたことを特徴とす
る請求項１または請求項２記載の半導体装置。3. The main surface of the electrode is formed substantially parallel to the main surface of the substrate.
And external leads are straightened.
3. The semiconductor device according to claim 1 or claim 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04050462A JP3112113B2 (en) | 1992-03-09 | 1992-03-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04050462A JP3112113B2 (en) | 1992-03-09 | 1992-03-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05251620A JPH05251620A (en) | 1993-09-28 |
| JP3112113B2 true JP3112113B2 (en) | 2000-11-27 |
Family
ID=12859544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04050462A Expired - Lifetime JP3112113B2 (en) | 1992-03-09 | 1992-03-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3112113B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005016830A1 (en) | 2004-04-14 | 2005-11-03 | Denso Corp., Kariya | Semiconductor device and method for its production |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6273750A (en) * | 1985-09-27 | 1987-04-04 | Toshiba Corp | Semiconductor device |
-
1992
- 1992-03-09 JP JP04050462A patent/JP3112113B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05251620A (en) | 1993-09-28 |
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