JP3109918B2 - Active phase equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active phase equalizer built in an integrated circuit.

[0002]

2. Description of the Related Art The configuration of a phase equalizer is as shown in FIG. That is, the input terminal 1 has the inductor L and the capacitance C
The input terminal 2 is connected to the output terminal 3 via a resistor R. In order to equalize the phase of the signal X (S), the signal X (S) is supplied to the input terminal 2 and the signal -X (S) having the opposite phase is supplied to the input terminal 1. When the output Y (S) is obtained, Y (S) = [{SL + (1 / SC)} / {R + SL + (1 / SC)}] X (S) − [R / {R + SL + (1 / SC)}] X (S) = [{SL + (1 / SC) -R} / {R + SL + (1 / SC)}] X (S) = [(S 2 LC-SCR + 1) / (S 2 LC + SCR + 1)] X (S) = [{S ² − (R / L) S + (1 / LC)} / {S ² + (R / L) S + (1 / LC)}] × X (S) (1) , Y (S) / X ( S) = - a ^{[S 2 (R / L)} S + (1 / LC) / S 2 + (R / L) S + (1 / LC)] ... (2). From the equation (2), the gain is all-pass, and the phase equalizer characteristic is obtained. In the above circuit, a phase equalizer can be realized with a small number of elements, but when an integrated circuit is formed, the inductor L cannot be incorporated.

[0003]

In the above-mentioned conventional phase equalizer, it is impossible to form an integrated circuit entirely because of including the inductor L. Therefore, the present invention
An object of the present invention is to provide an active phase equalizer that can be built in an integrated circuit.

[0004]

SUMMARY OF THE INVENTION The present invention is a unit having two input terminals and one output terminal and comprising a resistor, a capacitor and a buffer circuit, wherein one input terminal is supplied with a predetermined potential and the other input terminal is input. A three-terminal circuit unit having a low-pass filter characteristic in a predetermined band when a signal is applied, and a high-pass filter characteristic in a predetermined band when a predetermined potential is applied to the other input terminal and an input signal is applied to one input terminal. And a signal −X (S) having a phase opposite to that of the input signal in the first 3
The input signal is supplied to one input terminal of the terminal circuit unit, and the positive-phase signal X (S) of the input signal is supplied to the other input terminal of the first three-terminal circuit and one input terminal of the second three-terminal circuit. Then, the output signal of the first three-terminal circuit unit and the output signal of the second three-terminal circuit unit
And the output of the third three-terminal circuit unit is supplied to the second three-terminal circuit unit.
The configuration is such that feedback is provided to the other input terminal of the terminal circuit unit.

[0005]

According to the above means, since the three-terminal circuit unit does not have an inductor, the whole can be built in the integrated circuit.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The input terminal 21 receives the negative-phase signal -X (S) of the input signal, and the input terminal 22 receives the positive-phase signal X (S) of the input signal. The input terminal 21 is connected to the first input terminal in1 of the first three-terminal circuit unit 31, and the input terminal 22 is connected to the second input terminal in2 of the first three-terminal circuit unit 31 and the second input terminal in2. First input terminal of three-terminal circuit unit 32
Connected to in1. The output terminal out of the second three-terminal circuit unit 32 and the output terminal out of the first three-terminal circuit unit 31 are respectively connected to the first input terminal in1 and the second input terminal in2 of the third three-terminal circuit unit 33. It is connected.
The output terminal out of the third three-terminal circuit unit 33 is connected to the output terminal 23 of the circuit and to the second input terminal in2 of the second three-terminal circuit unit 32.

Here, the first, second, and third three-terminal circuit units 31, 32, and 33 have the same configuration, apply a predetermined potential to the second input terminal in2, and apply an input signal to the first input terminal in1. When given, a low-pass filter characteristic is exhibited in a predetermined band,
When a predetermined potential is applied to the first input terminal in1 and an input signal is applied to the second input terminal in2, a high-pass filter characteristic is exhibited in a predetermined band. As a specific configuration, for example, a configuration as illustrated in FIG. That is, the resistor 41 is connected in series to the first input terminal in1, the capacitor 42 is connected in series to the second input terminal in2, and the connection point of the resistor 41 and the capacitor 42 is
It is connected to an output terminal out via a buffer circuit 43. As shown in FIG. 1C, the buffer circuit has a simple configuration in which the base of the transistor Q1 is input, the collector is connected to the power supply line, the emitter is connected to the output terminal, and the current source is connected. This three-terminal circuit unit applies a predetermined potential to the second input terminal in2,
When an input signal is given to in1, the transfer function becomes G (S) = (1
/ SC) / (R + (1 / SC)) = 1 / (1 + SCR)
And has a low-pass filter characteristic. Also,
A predetermined potential is applied to the first input terminal in1, and the second input terminal in2
, The transfer function is given by G (S) = R / (R
+ (1 / SC)) = SCR / (1 + SCR), and has a high-pass filter characteristic.

FIG. 2 shows the circuit of FIG. 1A more specifically. 3 terminal circuit units 31, 3
The internal resistances of R2 and R33 are R1, R2 and R3, and the capacitance is C1.
, C2, C3 and the buffer circuits BF1, BF2, B
F3. Now, the input of the buffer circuits BF1 and BF2 will be referred to as V (S) and W (S), and it will be described that this circuit obtains the phase equalizer characteristics. V (S) = ｛R1 / (R1 + (1 / SC1)｝ X (S)-｛(1 / SC1) / (R1 + (1 / SC1)｝ X (S) = ｛1 / (1 + SC1 R1) ｝ (SC1 R1 -1) X (S) (3) W (S) = ｛(1 / SC2) / (R2 + (1 / SC2)｝ X (S) + ｛R2 / (R2 + (1 / SC2)｝ Y (S) = ｛1 / (1 + SC2R2)｝ ｛X (S) + SC2R2Y (S)｝ (4) Y (S) = R3 / ｛R3 + (1 / SC3)｝ V ( S) + (1 / SC3) / ｛(R3 + (1 / SC3)｝ W (S) = ｛SC3R3 / (1 + SC3R3)｝ V (S) + ｛1 / (1 + SC3R3)｝ W (S) (5) From the equations (3), (4) and (5), V (S) and W (S) are obtained.
1 (A), the transfer function of the circuit of FIG. 1A is as follows: Y (S) = [{SC3 R3 / (1 + SC3 R3)]. Times. {(SC1 R1 -1) / (1 + SC1 R1)}] X (S) + [1 / (1 + SC3 R3) × {1 / (1 + SC2 R2)}] X (S) + {1 / (1 + SC3 R3)} SC2 R2 / (1 + SC2 R2)} Y (S) / X (S) = [{ (S 2 C1 C3 R1 R3 -SC3 R3) / (1 + SC1 R1)} + {1 / (1 + SC2 R2)}] / [{(S 2 C2 C3 R2 R3 + SC3 R3 +1) / (1 + SC2 R2)] (6) In the expression (6), C1 = C2 (7), R1 = R2 ...
When put (8), equation (6), Y (S) / X ( S) = (S 2 C1 C3 R1 R3-SC3 R3 +1) / (S 2 C1 C3 R1 R3 + SC3 R3 + 1) ... (9)

Thus, the gain is all-pass, and the circuit of FIG. 1A can have the characteristics of a phase equalizer. The condition of C1 R1 = C2 R2 (CR products are equal)
The same phase equalizer characteristics as above can be obtained even if Since the input and output of the buffer circuit BF3 are the same signal, the circuit output may be taken out from the input side of the buffer circuit BF3.

[0011]

As described above, according to the present invention, a phase equalizer can be realized by combining three terminal circuit units without using an inductor, and all circuits can be integrated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention and a diagram showing some details.

FIG. 2 is a diagram showing a specific example of a block in FIG.

FIG. 3 is a circuit diagram showing a phase equalizer.

[Explanation of symbols]

 31, 32, 33 ... 3-terminal circuit unit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-63922 (JP, A) JP-A-53-20748 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03H 11/18

Claims (2)

(57) [Claims] An input terminal has two input terminals and one output terminal. When a predetermined potential is applied to one input terminal and an input signal is applied to the other input terminal, a low-pass filter characteristic is exhibited in a predetermined band, and the other input terminal is provided. When a predetermined potential is applied to one input terminal and an input signal is applied to the input terminal, a plurality of three-terminal circuit units exhibiting high-pass filter characteristics in a predetermined band are used. The signal is supplied to one input terminal of the three-terminal circuit unit, and the positive-phase signal X (S) of the input signal is supplied to the other input terminal of the first three-terminal circuit and the second input terminal.
To one input terminal of the three-terminal circuit of
An output signal of the terminal circuit unit and an output signal of the second three-terminal circuit unit are supplied to the other and one input terminal of the third three-terminal circuit unit, respectively, and an output of the third three-terminal circuit unit is supplied to the terminal. An active-type phase equalizer, wherein feedback is provided to the other input terminal of the second three-terminal circuit unit so that a signal derived from the third three-terminal circuit unit obtains a phase equalization characteristic. 2. The three-terminal circuit unit, wherein a first input terminal connects a resistor in series, a second input terminal connects a capacitor in series, and a connection point between the resistor and the capacitor is connected to an output terminal via a buffer circuit. 2. The active phase equalizer according to claim 1, wherein the active phase equalizer is connected.