JP3109570B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a semiconductor layer comprising silicon.
To a method for manufacturing a semiconductor device .

[0002]

2. Description of the Related Art Conventionally, a semiconductor having a semiconductor layer made of silicon
Body device, for example, a thin film transistor, having an insulating surface
Fabrication on a substrate has been studied.

However, substrates having low heat resistance such as glass substrates
When forming a semiconductor device on the top, configure the semiconductor device
Fabricated because it is difficult to increase the crystallinity of the silicon film
It has been difficult to improve the performance of the semiconductor device.

[0004]

DISCLOSURE OF THE INVENTION The present invention is manufactured at a low temperature.
To produce semiconductor devices with high performance
With the goal.

[0005]

[Means for Solving the Problems] In order to solve the above-mentioned problems
In addition, one of the inventions disclosed in this specification is a method on a glass substrate.
A step of forming a silicon oxide film and disilane as a reaction gas
Alternatively, the acid is prepared by a reduced pressure CVD method using trisilane.
Forming an intrinsic non-single-crystal semiconductor layer on a silicon nitride film
When, the semiconductor layer is heated at a temperature not exceeding 700 ° C.
Crystallizing, and forming a gate insulating film on the semiconductor layer.
Forming a semiconductor device.
It is a manufacturing method.

In this structure, the low pressure CVD method
At a temperature 100 to 200 ° C. lower than the crystallization temperature of silicon
It is characterized by being implemented.

Further, in this configuration, the non-single-crystal half
The conductor is an amorphous semiconductor.

Further, in this structure, the semiconductor layer
The crystallization step should be performed in the range of 450 to 700 ° C.
And features.

In this structure, the semiconductor layer may be
Concentration of oxygen atoms is 7 × 10 ¹⁹ atoms / cm ³
It is characterized by the following.

One of the other inventions disclosed herein is a gas
Forming a silicon oxide film on a glass substrate, a reaction gas
To the reduced pressure CVD method using disilane or trisilane.
Forming an intrinsic non-single-crystal semiconductor layer on the silicon oxide film.
Forming and heating the semiconductor layer for crystallization
And the non-single-crystal half by the low-pressure CVD method.
During the formation of the conductor layer, boron is added to the semiconductor layer.
A method for manufacturing a semiconductor device.

In this structure, the semiconductor layer is 1 × 1
Concentration in the range of 0 ¹⁵ to 1 × 10 ¹⁷ atoms / cm ³
And containing boron.

In this structure, the semiconductor layer may be
Concentration of oxygen atoms is 7 × 10 ¹⁹ atoms / cm ³
It is characterized by the following.

One of the other inventions disclosed in this specification is a countermeasure.
Decompression C using disilane or trisilane as reaction gas
By VD method, a semiconductor layer containing silicon is formed on an insulating surface.
Forming and crystallizing the semiconductor layer by heating.
The crystallization of the semiconductor layer after the crystallization.
Shift is lower than that of single crystal silicon.
Semiconductor device manufacturing method characterized in that
It is .

[0014] One of the other inventions disclosed in this specification is a countermeasure.
Decompression C using disilane or trisilane as reaction gas
By VD method, a semiconductor layer containing silicon is formed on an insulating surface.
Forming and crystallizing the semiconductor layer by heating.
The semiconductor layer after the crystallization is Raman
The crystal grain size in the range of 50-500Å
A method for manufacturing a semiconductor device, comprising:

In the above structure, the insulating surface is made of glass
A silicon oxide film formed on a substrate.
You.

[0016] One of the other inventions disclosed in this specification is a countermeasure.
Decompression C using disilane or trisilane as reaction gas
Intrinsic non-single-crystal semiconductor layer containing silicon by VD method
Forming a semiconductor layer on an insulating surface;
℃ by heating at a temperature not exceeding a process for crystallizing, the
After the crystallization step, the crystallized semiconductor layer is converted into an island-shaped semiconductor.
Patterning, and the crystallized semiconductor layer
Forming a gate insulating film thereon.
Semiconductor device manufacturing method.

One of the other inventions disclosed in this specification is a small one.
At least P-channel transistor and N-channel transistor
Upon manufacturing a semiconductor device including a static, and the reaction gas
Pressure CVD using disilane or trisilane.
A non-single-crystal semiconductor layer containing silicon on the insulating surface.
Forming the semiconductor layer at a temperature not exceeding 700 ° C.
Crystallizing by heating in the P channel
Threads of transistors and N-channel transistors
For canteens Rudo voltage is controlled to be approximately the same
In addition, boron is added to the semiconductor device.
This is a method for manufacturing a semiconductor device.

According to the above configuration, it can be manufactured at a low temperature and
A semiconductor device having excellent performance can be manufactured. Less than
Examples are shown below.

[0019]

[Embodiment 1] A flat display is attracting attention instead of a CRT as a display of an OA device or the like, and expectation for a large area is particularly strong. As other applications of flat displays, development of wall-mounted TVs is also proceeding at a rapid pace. Also, demands for flat display colorization and high definition have been considerably increased.

A liquid crystal display device is known as a typical example of the flat display. In this method, an electric field is applied to a liquid crystal composition held between a pair of glass substrates with an electrode interposed therebetween to change the state of the liquid crystal composition, and display is performed by utilizing the difference between the states. In order to drive the liquid crystal, there are a type provided with a thin film transistor (hereinafter referred to as a TFT) and other switching elements, and a type having a simple matrix configuration. In any case, a driver circuit for sending a signal for driving the liquid crystal to each wiring in the vertical and horizontal (X, Y) directions is provided around the display.

This driver circuit is usually formed of a single crystal silicon MOS integrated circuit (IC). This I
C is provided with pad electrodes corresponding to the respective display electrodes, and a printed board is interposed between the two. First, the pad electrodes of the IC are connected to the printed board, and then the printed board is connected to the display. Was. This printed circuit board is an insulating substrate made of glass epoxy or paper epoxy or a substrate made of flexible plastic, and the occupied area must be equal to or larger than the display. Similarly, the volume had to be considerably increased.

Such a conventional display has the following disadvantages due to the above-described configuration.

That is, the X direction of the matrix wiring, the Y direction
Since the same number of connections as the number of display electrodes or source (drain) wirings or gate wirings in the direction are made with the printed circuit board, there is a limit on the spacing between the connectable connection parts due to mounting technology. A high definition display could not be produced.

In addition to the display body, a printed circuit board, an IC, and connection wiring are required, and the required area and volume are several times larger than the display body.

There are many connection points between the display body and the printed circuit board and between the printed circuit board and the IC, and the connection parts are considerably heavy, so that an excessive force is applied to the connection parts and the connection reliability is low.

On the other hand, as a method of solving such a drawback, it has been proposed that, in a display, particularly a display device using an active element as a switching element, the active element and the peripheral circuit are formed by TFTs on the same substrate. I have. However, according to this configuration, the aforementioned 3
Although the two disadvantages can be almost completely solved, another new problem has arisen.

Peripheral circuits other than active elements can be TF
Because of T, the number of elements formed on the same substrate increases,
The manufacturing yield of the TFT has decreased. Accordingly, the production yield of the display has also been reduced.

The peripheral circuit portion has a very complicated device structure as compared with the device structure of the active device portion. Therefore, the circuit pattern becomes complicated, the manufacturing process technology becomes more sophisticated, and the cost increases. In addition, naturally, the number of multi-layer wirings is increased, and the number of process steps is increased and the manufacturing yield of the TFT is lowered.

Since a transistor constituting a peripheral circuit is required to have a fast response speed, a polycrystalline semiconductor is usually used. Therefore, in order to polycrystallize the semiconductor layer,
High temperature processing was required, and an expensive quartz substrate or the like had to be used.

The present embodiment is to solve the above-mentioned six problems in an appropriately balanced manner, and relates to a liquid crystal display device having a low cost and a high production yield.

That is, a first substrate on which a pixel matrix having a plurality of gate lines, a plurality of source (drain) lines, and a thin film transistor having a complementary configuration is formed, and a second substrate disposed opposite to the first substrate. A liquid crystal display device comprising a substrate and a liquid crystal composition held between the pair of substrates, wherein a peripheral circuit connected to an X or Y matrix wiring formed on the first substrate is provided. At least a part of the peripheral circuit is a thin film transistor formed by the same process as a complementary structure similar to the active element connected to the pixel, and the remaining peripheral circuit is constituted by a semiconductor chip .

The connection between the IC and the substrate as the remaining peripheral circuits which are not formed into TFTs is performed by providing an IC chip directly on the substrate and using a COG method or an IC chip connected to each connection terminal.
This can be realized by a TAB method in which individual resin substrates are provided on a flexible organic resin substrate and the resin substrate and the display substrate are connected.

That is, in the present embodiment , not all the peripheral circuits of the liquid crystal display device are formed into TFTs, but only a simple part of the element structure, only a functional part having a small number of elements, or a circuit in which a general-purpose IC is difficult to obtain. Only part, and even IC
Only the high cost parts are made into TFTs, so that the production yield of the liquid crystal display device can be improved and the production cost can be reduced .

In addition, by forming a part of the peripheral circuit as a TFT, an external IC which has conventionally required a considerable number is required.
Fewer, Ru der which reduce manufacturing costs.

Further, since the active element and the peripheral circuit are formed by a complementary type (CTFT) thin film transistor formed by the same process, the capability of driving the pixel is improved.
The redundancy can be given to the peripheral circuit, and the liquid crystal display device with a sufficient margin can be driven.

When the entire peripheral circuit is formed as a TFT, the size of the display substrate must be increased in both the X direction and the Y direction, and the occupation area of the entire display device increases. Only a small size of the substrate is required, and the display device can be easily adjusted to the external dimensions of the computer or the device using the display device, and the display device occupies a small area and volume.

Parts where the element structure in the peripheral circuit is complicated,
For example, a high-level fabrication technology is required to turn the element structure that requires multilayer wiring or the part with the function of an amplifier into a TFT, but the part that is technically difficult by turning part of the TFT into a TFT. By using a conventional IC, a portion having a simple element structure or a simple function can be formed into a TFT, and a display device can be realized at low cost and high yield.

Further, by forming only a part of the TFT, the number of thin film transistors in the peripheral circuit portion can be considerably reduced. When the functions of the peripheral circuits in the X and Y directions are the same, the number is almost half. Become. As described above, by reducing the number of elements to be TFTs, the production yield of the substrate can be improved, and a display device in which the area and volume of the substrate can be reduced can be realized at low cost.

Furthermore, by using a semi-amorphous semiconductor of a new concept instead of a conventionally used polycrystalline or amorphous semiconductor for the semiconductor layer used for the TFT, it can be manufactured at a low temperature, and the carrier of A TFT with very high mobility and high response speed can be realized.

This semi-amorphous semiconductor is an LPC
It is obtained by performing a thermal crystallization treatment after forming a film by a VD method, a sputtering method, a PCVD method, or the like. The following description will be made by using a sputtering method as an example.

That is, when a single crystal silicon semiconductor is used as a target in the sputtering method and sputtering is performed with a mixed gas of hydrogen and argon, atomic silicon is separated from the target by sputtering (impact) of heavy atoms of argon, and the silicon is formed. While flying on a substrate having a surface, a cluster of tens to hundreds of thousands of atoms solidified at the same time leaves the target as a cluster and flies to the surface to be formed.

During this flight, hydrogen bonds to the dangling bonds of silicon in the outer periphery of this cluster, and a hydrogen atom is formed as a region having a relatively high order on the surface to be formed in a bonded state. That is, on the surface on which the film is formed, there is a high order and S
A state of a mixture of a cluster having an iH bond and pure amorphous silicon is realized. This is 450 ° C to 700
Due to the heat treatment in a non-oxidizing gas at a temperature of 0 ° C., the Si—H bonds around the cluster react with other Si—H bonds to form Si—H bonds.
Create a Si bond.

This bond pulls each other at the same time,
Highly ordered clusters tend to transfer phase to a higher ordered state, ie crystallization. However, between adjacent clusters, Si-Si bonded to each other pulls between the clusters. The result shows that the crystal has lattice strain and the crystal peak in laser Raman is 520 cm for a single crystal.
It is measured shifted to the lower wave number side from ^-1 .

Further, since the Si-Si bond between the clusters anchors (connects) each other, the energy band in each cluster may be electrically connected to each other via the anchoring portion. Therefore, it is fundamentally different from polycrystalline silicon in which a crystal grain boundary acts as a carrier barrier, and has a carrier mobility of 10 to ²⁰⁰ cm ² / VS.
ec can be obtained.

In other words, a semi-amorphous semiconductor based on the above definition can be expected to have a state in which although it has apparent crystallinity, there is substantially no crystal grain boundary electrically. Of course, the annealing temperature is 450 ° C.
When crystallization accompanied by crystal growth of 1000 ° C. or more is performed instead of the intermediate temperature annealing at 700 ° C., oxygen and the like in the film are bent out to the grain boundaries due to the crystal growth, and a barrier is formed. This is a material (polycrystal) having the same crystal and grain boundaries as a single crystal.

When the degree of anchoring between clusters in this semiconductor is further increased, the carrier mobility is further increased. For this purpose, the amount of oxygen in the film is reduced to 7 × 10 ¹⁹ cm ^−3, preferably 1 × 10 ¹⁹ cm ^{−3.
When the value is −3} or less, crystallization can be further performed at a temperature lower than 600 ° C., and high carrier mobility can be obtained.

In this embodiment, description will be made using a liquid crystal display device having an m × n circuit configuration as shown in FIG. That is, only the analog switch array circuit portion 1 among the peripheral circuit portions connected to the wiring in the X direction in FIG. 1 is formed into a TFT 5 in the same manner as the active element provided in the pixel 6, and the peripheral circuit connected to the Y direction wiring. As for the part, only the analog switch array circuit part 2 is converted to a TFT, and the other peripheral circuit parts are IC4.
And is connected to the substrate by the COG method. Where TF
The T-shaped peripheral circuit portion is formed as a CTFT (complementary configuration) similarly to the active element provided in the pixel.

FIG. 2 shows an actual arrangement of electrodes and the like corresponding to this circuit configuration. FIG. 2 shows only a portion corresponding to 2 × 2 for the sake of simplicity.

First, a method for manufacturing a TFT on a liquid crystal display device used in this embodiment will be described with reference to FIGS. FIG.
In (A), a silicon oxide film as a blocking layer 51 is formed on a glass 50 that can withstand a heat treatment at an inexpensive temperature of 700 ° C. or less, for example, about 600 ° C.
It is made to a thickness of 0 °. The process conditions were a 100% oxygen atmosphere, a film formation temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The deposition rate using quartz or single crystal silicon as the target was 30 to 100 ° / min.

A silicon film was formed thereon by an LPCVD (low pressure gas phase) method, a sputtering method, or a plasma CVD method. When formed by the reduced pressure gas phase method, the temperature is 1
450-550 ° C lower by 00-200 ° C, for example 530 ° C
With disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H
₈ ) was supplied to a CVD apparatus to form a film. The pressure in the reactor was 30 to 300 Pa. The deposition rate is 50-250 ° /
Minutes. In order to control the threshold voltage (Vth) of the NTFT and PTFT to be substantially the same, boron is used to diborane to 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^−3.
May be added during the film formation.

In the case of performing the sputtering method, the back pressure before the sputtering was set to 1 × 10 ⁻⁵ Pa or less, and single crystal silicon was used as a target in an atmosphere in which hydrogen was mixed with 20 to 80% of argon. For example, argon was 20% and hydrogen was 80%. The deposition temperature is 150 ° C., the frequency is 13.56 MHz,
The sputter output was 400-800 W and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is set to, for example, 300 ° C., and monosilane (SiH
₄ ) or disilane (Si ₂ H ₆ ) was used. These were introduced into a PCVD apparatus, and a high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are:
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If the oxygen concentration is high, crystallization is difficult, and the thermal annealing temperature must be increased or the thermal annealing time must be increased. If the amount is too small, the leakage current in the off state increases due to the backlight. Therefore 4 × 10
The range was ¹⁹ to 4 × 10 ²¹ cm ⁻³ . Hydrogen is 4x
It was 10 ²⁰ cm ⁻³ , which was 1 atomic% as compared with silicon 4 × 10 ²² cm ⁻³ . In order to further promote crystallization of the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ c.
m ⁻³ or less, and oxygen is ion-implanted only into a channel formation region of a TFT constituting a pixel to form 5 × 10 ²⁰ to
You may add so that it may become 5 * 10 < ²¹ > cm <^-3> . At this time, since light is not irradiated to the TFTs constituting the peripheral circuit, it is effective to reduce the mixing of oxygen and to have a higher carrier mobility for high-frequency operation.

Next, the amorphous silicon film is
After fabrication to a thickness of ~ 5000mm, for example 1500mm, 4
Medium-temperature heat treatment in a non-oxide atmosphere at a temperature of 50 to 700 ° C. for 12 to 70 hours, for example, 600 hours in a hydrogen atmosphere
It was kept at a temperature of ° C. Since a silicon oxide film having an amorphous structure is formed on the substrate surface below the silicon film, no specific nucleus is present in this heat treatment, and the whole is uniformly heat-annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

By the annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state. In particular, a region having a relatively high order in a state after the formation of silicon is particularly likely to be crystallized to be in a crystalline state. However, since the silicon existing between these regions is bonded to each other, the silicons are mutually opposed. Single crystal silicon peak 522 measured by laser Raman spectroscopy
A peak shifted to a lower frequency side than cm ⁻¹ is observed. Its apparent particle size, calculated from the half width, is 5
Although it is like a microcrystal having a size of 0 to 500 °, there are actually a large number of regions having high crystallinity and a cluster structure, and a semi-amorphous structure in which each cluster is bonded to each other by silicon (anchoring). Could be formed.

As a result, the coating exhibits a state substantially free of grain boundaries (hereinafter referred to as GB). Carriers can easily move from one cluster to another through the anchored locations between the clusters, so-called GB
Carrier mobility higher than that of polycrystalline silicon that clearly exists. That is, hole mobility (μh) = 10 to 200 cm
² / VSec, electron mobility (μe) = 15-300 cm
² / VSec is obtained.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at the above-mentioned medium temperature, segregation of impurities in the film occurs due to solid phase growth from nuclei. Impurities such as oxygen, carbon, and nitrogen increase, and the mobility in the crystal is large. However, a barrier (barrier) is formed in GB to hinder the movement of carriers there. As a result, a mobility of 10 cm ² / Vsec or more cannot be easily obtained. That is, in this embodiment, a silicon semiconductor having a semi-amorphous or semi-crystalline structure is used for such a reason.

In FIG. 3A, the silicon film is subjected to photoetching using a first photomask, and a PTFT region 22 (channel width 20 μm) is placed on the right side of the drawing as NT
A region 13 for FT was formed on the left side.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 {for example, 1000}. This was made under the same conditions as those for forming the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix the sodium ions.

Thereafter, 1 to 5 × 10
A silicon film having a concentration of ²¹ cm ⁻³ or a multilayer film of the silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ was formed thereon. This was patterned using a second photomask to obtain FIG. 3B. Gate electrode 55 for PTFT, NT
A gate electrode 56 for FT was formed. For example, a channel length is 10 μm, and phosphorus-doped silicon is 0.2 μm as a gate electrode.
m, and molybdenum was formed thereon to a thickness of 0.3 μm. In FIG. 3C, a photoresist 57 is formed using a photomask, and boron is applied to the PTFT source 59 and drain 58 at 1 to 5 × 10 ¹⁵ cm ^−2.
Was added by an ion implantation method at a dose of. Next, FIG.
As shown in (D), a photoresist 61 was formed using a photomask. Source 64 and drain 6 for NTFT
Phosphorus 2 was added by an ion implantation method at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² .

These operations were performed through the gate insulating film 54. However, in FIG. 3B, the gate electrodes 55, 56
May be used as a mask to remove silicon oxide on the silicon film, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, heat annealing was performed again at 600 ° C. for 10 to 50 hours. The source 59 of the PTFT and the drain 64 of the NTFT were manufactured as P ⁺ and N ⁺ by activating impurities. Gate electrode 5
Channel formation regions 60 and 63 are formed below 5 and 56 as semi-amorphous semiconductors.

In this way, a C / TFT can be manufactured without applying a temperature to 700 ° C. or more in all steps, even though it is a self-aligned system. Therefore, it is not necessary to use an expensive substrate such as quartz as a substrate material, and this is a process very suitable for the large pixel liquid crystal display device of this embodiment .

In this embodiment, the thermal annealing is performed as shown in FIG.
(D) was performed twice. However, the annealing in FIG. 3A may be omitted depending on the required characteristics, and both may be shortened by the annealing in FIG. 3D to shorten the manufacturing time. In FIG. 4A, a silicon oxide film is formed on the interlayer insulator 65 by the above-described sputtering method. This silicon oxide film may be formed by an LPCVD method, a photo CVD method, or a normal pressure CVD method. For example, it was formed to a thickness of 0.2 to 0.6 μm, and then a window 66 for an electrode was formed using a photomask. Further, aluminum is formed on the entirety by sputtering, and leads 71 and 72 and contacts 67,
After fabricating No. 68 using a photomask, the surface was coated with an organic resin 69 for planarization, for example, a translucent polyimide resin, and the electrode hole was formed again using the photomask.

As shown in FIG. 4B, in order to connect the two TFTs to a complementary structure and connect the output terminals thereof to the electrodes of one pixel of the liquid crystal device as a transparent electrode, ITO (indium oxide) was formed by sputtering. (A tin oxide film). It is etched using a photomask and the electrodes 7
0 was configured. This ITO film was formed at room temperature to 150 ° C. and achieved by annealing at 200 to 400 ° C. in oxygen or atmosphere. Thus, PTFT 22 and NTF
The same glass substrate 50 as T13 and the electrode 70 of the transparent conductive film
Made above. The electrical characteristics of the obtained TFT are PTF
At T, the mobility is 20 (cm ² / Vs), and Vth is −5.9.
(V), the mobility of NTFT is 40 (cm ² / Vs),
Vth was 5.0 (V).

FIG. 2 shows an arrangement of electrodes and the like in a pixel portion of the liquid crystal display device. NTFT 13 is connected to the first scanning line 1
5 at the intersection of the data line 21 and the first scanning line 15
NTFTs for other pixels are similarly provided at the intersections between the data lines 14 and the data lines 14. On the other hand, PTFT is the second scanning line 1
8 and the data line 21. Also,
An NTFT for another pixel is provided at the intersection of the adjacent first scanning line 16 and data line 21. A matrix configuration using such a C / TFT is provided. The NTFT 13 is connected to the first scanning line 15 via a contact at the input end of the drain 64, and the gate 56 is connected to the data line 21 on which a multilayer wiring is formed.
The output terminal of the source 62 is connected to the pixel electrode 1 via a contact.
7 is connected.

On the other hand, the PTFT 22 has an input terminal of the drain 58 connected to the second scanning line 18 via a contact,
The gate 55 is connected to the data line 21 and the output terminal of the source 59 is connected to the pixel electrode 17 via a contact in the same manner as the NTFT. Thus, the pixel 23 made of the transparent conductive film and the C / TF are interposed (inside) between the pair of scanning lines 15 and 18.
T constituted one pixel. By repeating such a structure left, right, up and down, a 2 × 2 matrix is enlarged to 640 × 480, 1280 × 960.
Large-pixel liquid crystal display device.

As described above, a CMOS configuration is provided in which the NTFT 13 and the PTFT 22 manufactured by the same process as the switching element are provided.

As described above, one of the substrates is completed.
The other substrate is bonded by a conventional method, and STN liquid crystal is injected between the substrates. Next, as the remaining peripheral circuits, I
Use C4. This IC 4 is connected to each of the X-direction wiring and the Y-direction wiring of the substrate by COG.
This IC 4 is only connected to connection leads for supplying power and data from the outside, and there is no FPC for connection on one side of the board. The number is considerably reduced and reliability is improved. As described above, the liquid crystal display device of this example was completed.

In this embodiment, only the analog switch array part 1 of the peripheral circuits on the X direction side is connected to the analog switch array part 2 of the peripheral circuits on the Y direction side.
FT and C / TF in the same process as the switching element
Although the peripheral circuit portion is configured by IC4, the configuration is not particularly limited to this configuration. Considering the yield at the time of forming the TFT, the problem of the process technology at the time of forming the TFT, and the like, Only the portion that is easy to make into a TFT may be made into a TFT.

In this embodiment, since a semi-amorphous semiconductor is used as the semiconductor film, the mobility is 10 times or more as large as that of a TFT using a non-single-crystal semiconductor. Therefore, it can be used satisfactorily even for TFTs in peripheral circuits that require a high response speed, and is manufactured by the same process as an active element without the need to specially crystallize TFTs in a peripheral circuit portion as in the related art. I was able to.

Further, since the active element connected to the liquid crystal pixel has a C / TFT configuration, the operation margin is expanded, the pixel potential does not fluctuate, and a constant display level can be secured. However, there is an advantage that even if the defect is not good, a noticeable defect is not displayed.

With the structure shown in this embodiment , it is no longer impossible to increase the definition of the liquid crystal display due to the limitation of the external connection technology. Further, unnecessary connection between the wiring in the X direction or the wiring in the Y direction and the external peripheral circuit could be minimized, so that the reliability at the connection portion was improved.

In order to make only some of the peripheral circuits into TFTs,
The exclusive area of the display board itself can be reduced,
In addition, the substrate can be freely designed to the required dimensions and shape. In addition, it is possible to avoid a problem in manufacturing a TFT and to make only a portion having a high manufacturing yield into a TFT. Therefore, the manufacturing cost could be reduced.

Since a semi-amorphous semiconductor is used as the semiconductor film used for the TFT, a response speed which can be sufficiently used for peripheral circuits can be obtained. A TFT for a circuit could be formed at the same time.

In this embodiment , by connecting complementary TFTs to each pixel in a matrix, the threshold value is clarified. Switching speed is increased. Operating margin is increased. Can be done to some extent. The number of photomasks required for fabrication is N
It is only twice as large as in the conventional example using only TFTs.
Since the mobility of the carrier is ten times or more as large as that in the case of using amorphous silicon, the size of the TFT can be reduced, and even if two TFTs are provided in one pixel, the aperture ratio hardly decreases. It has many features.

Therefore, as compared with the conventional active TFT liquid crystal device using only the NTFT, it is possible to achieve several stages of production yield and a vividness of the screen.

Reference Example FIG. 5 shows a schematic external view of the liquid crystal display device of this example. The basic circuit and the like are exactly the same as in the first embodiment. In FIG. 5, a portion of the peripheral circuit connected to the wiring in the Y direction, which is configured by the IC 4, has the IC formed directly on the substrate by the COG method. The IC 4 is provided separately on the upper and lower portions of the substrate.

In this case, in the connection between the pad electrode of the IC 4 and the Y-direction wiring, the interval can be made smaller than in the case where the IC is formed on only one side. Therefore, it has a feature that a higher definition display pixel can be designed. Further, since the IC is provided on the substrate, the volume is hardly increased, and a thinner liquid crystal display device can be provided.

In the above-described embodiment, the TFTs of the active elements have a CMOS configuration. However, the present invention is not limited to this configuration. The TFTs may be composed of only NTFTs and PTFTs. The configuration increases the number of elements.

The position where the TFT is formed on the substrate is indicated by X
A TFT is formed not only on one side connected to the wiring in the direction or the Y direction, but also on the other side, and the TFTs are alternately formed.
By connecting T, the density of the TFT is reduced by half, thereby improving the manufacturing yield of the TFT.

[0082]

According to the present invention, it can be manufactured at a low temperature and has a high
A semiconductor device having excellent performance was able to be manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a liquid crystal display device having an m × n circuit configuration.

FIG. 2 is a diagram illustrating an arrangement of pixel portions of a liquid crystal display device.

FIG. 3 is a diagram schematically illustrating a manufacturing process of a TFT.

FIG. 4 is a diagram schematically illustrating a manufacturing process of a TFT.

FIG. 5 is a diagram showing another embodiment.

[Explanation of symbols]

 1, 2, ... Peripheral circuit 4 ... IC 5 ... Peripheral circuit made into TFT 6 ... Pixel 13 NTFT 22 PTFT

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-182816 (JP, A) JP-A-1-223719 (JP, A) JP-A-2-207537 (JP, A) JP-A-60-1985 245174 (JP, A) JP-A-63-237570 (JP, A) JP-A-57-99729 (JP, A) JP-A-63-237571 (JP, A)

Claims (4)

(57) [Claims] 1. An insulating surface having an oxygen concentration of 7 × 10 ¹⁹ atoms.
forming a non-single-crystal semiconductor layer mainly composed of s / cm ³ or less and silicon boron is added, the non-single-crystal semiconductor layer in a non-oxidizing atmosphere at 450
And forming a semiconductor layer by heating at to 700 ° C., a method for manufacturing a semiconductor device wherein the semiconductor layer has a Raman shift of Raman peak is lower wave number than single crystal silicon. 2. A semiconductor device including a P-channel transistor and an N-channel transistor, wherein a non-single-crystal semiconductor whose main component is silicon to which an oxygen concentration is 7 × 10 ¹⁹ atoms / cm ³ or less and boron is added to an insulating surface. Forming a layer; and 450 exposing the non-single-crystal semiconductor layer in a non-oxidizing atmosphere.
Forming a semiconductor layer by heating at a temperature of from about 700 ° C. to about 700 ° C. , wherein the semiconductor layer has a single-crystal Raman peak Raman shift.
A method for manufacturing a semiconductor device , wherein a wave number is lower than that of a recon, and the absolute values of threshold voltages of the P-channel transistor and the N-channel transistor are the same. 3. An apparatus according to claim 1 or 2, the manufacturing method of the non-single-crystal semiconductor layer is a semiconductor device which is characterized in that it has an amorphous structure. 4. The method of claim 1 or 2, the method for manufacturing a semiconductor device wherein the insulating surface is a surface of the silicon oxide film formed on a glass substrate.