JP3109090B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device having a dynamic RAM that stores charge in a capacitor.

[Prior Art] FIGS. 3A and 3B are cross-sectional views showing a method of manufacturing a conventional semiconductor memory device in the order of steps.

First, as shown in FIG. 3A, an N-type well 2 is selectively formed on the surface of a P-type silicon
By selectively forming a field oxide film 3 on the silicon substrate 1, the surface of the P-type silicon substrate 1 is formed in the memory cell formation region 4, the P-channel MOS transistor formation region 5, and the N-channel MOS transistor formation region. The element is separated into 6. Next, a gate oxide film 7 is formed on the P-type silicon substrate 1 in the regions 4 to 6. Then, a gate electrode 8 is patterned on the gate oxide film 7 in each of the regions 4 to 6. The gate electrode 8a is patterned on the field oxide film 3 near the memory cell formation region 4. Thereafter, source / drain regions 9a to 9c are formed by selectively introducing predetermined impurities into the surfaces of the P-type silicon substrate 1 in the regions 4 to 6, respectively.

Next, as shown in FIG. 3B, an interlayer insulating film is formed on the entire surface.
After depositing 10, a storage electrode 11 connected to one of the source / drain regions 9a is patterned on the interlayer insulating film 10 in the memory cell forming region 4. Next, this storage electrode 11
The capacitor film 12 and the plate electrode 13 are formed on the pattern.
Thereafter, the storage electrode 11, the capacitor film 12, and the plate electrode 13 are embedded in the interlayer insulating film 10 by further applying the interlayer insulating film 10. Next, a bit line 14 connected to the other source / drain region 9a is pattern-formed on the interlayer insulating film 10 in the memory cell formation scheduled region 4.

In the semiconductor memory device configured as described above, the storage electrode 11, the capacitance film 12, and the plate electrode 13 form a stack capacitance of the memory cell, and charges are accumulated in the stack capacitance.

[Problem to be Solved by the Invention] However, in the above-described conventional method for manufacturing a semiconductor memory device, after forming the source / drain regions 9a to 9c, the stack capacitance of the memory cell and the interlayer insulating film 10 are formed. For this reason, the source / drain regions 9a to 9c are significantly heated in the step of forming the stack capacitor, the reflow step after the formation of the interlayer insulating film 10, and the like. As a result, the P-channel MOS transistor and the N-channel MOS transistor have a problem that the impurities in the source / drain regions 9b and 9c diffuse into the substrate more than necessary and the transistor characteristics deteriorate. In particular, the characteristics of the P-channel MOS transistor greatly change due to heat.

The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor memory device that can prevent deterioration of transistor characteristics due to heat.

[Means for Solving the Problems] In a method for manufacturing a semiconductor memory device according to the present invention, a memory cell including a first MOS transistor and a capacitor is provided in a first region of a semiconductor substrate, and a second cell is provided in a second region. Forming a gate electrode on a semiconductor substrate in the first and second regions via a gate insulating film, respectively,
Selectively forming a first source / drain region on the surface of the semiconductor substrate in the first region, depositing an interlayer insulating film on the entire surface, and forming the first source / drain region on the interlayer insulating film.
Selectively forming a capacitor connected to the source / drain region of the semiconductor device; and forming the first source / drain on the interlayer insulating film.
Selectively forming a bit line connected to a drain region, selectively removing the interlayer insulating film in the second region, and selectively removing the interlayer insulating film in the second region. Removing, and selectively forming a second source / drain region on the surface of the semiconductor substrate in the second region, wherein the step of selectively forming the bit line comprises: Is performed before or after the step of selectively forming the interlayer insulating film, and the step of selectively removing the interlayer insulating film is performed after the step of selectively forming the bit line and the step of selectively forming the capacitor. It is characterized by being performed. In addition,
In claim 1 of the present application, a second region formed in the second region
A MOS transistor is a general MOS transistor for a peripheral circuit that is not a memory cell.
P-channel MO formed in the area where OS transistor is to be formed
It includes both an S transistor and an N channel MOS transistor formed in a region where an N channel MOS transistor is to be formed, and either one of them.

[Operation] In the present invention, after a gate electrode is selectively formed on a semiconductor substrate via a gate insulating film and a first source / drain region of a first MOS transistor forming a memory cell is formed, An interlayer insulating film is deposited on the entire surface, and a capacitor and a bit line connected to the first source / drain region are selectively formed on the interlayer insulating film. Then the second
The second source / drain region of the MOS transistor is selectively formed. After forming the capacity, bit line and interlayer insulating film of the memory cell in this way, the second source / drain region of the second MOS transistor is formed. Is not heated in the step of forming the interlayer insulating film and the step of forming the interlayer insulating film, and the impurity does not diffuse more than necessary into the substrate. For this reason, it is possible to prevent the transistor characteristics of the second MOS transistor from deteriorating due to heat.

In addition, a MOS transistor having a P-type channel has a relatively large change in characteristics due to heat treatment. For this reason, in the present invention, it is preferable that the second MOS transistor has a P-type channel.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

1A to 1C are sectional views showing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1A, an impurity such as phosphorus is implanted into the surface of a P-type silicon substrate 1, and the N-type well 2 is selectively formed by diffusing the impurity by heat treatment. Thereafter, a field oxide film 3 having a thickness of, for example, about 6000.degree. Is selectively formed on the P-type silicon substrate 1 so that the surface of the P-type silicon substrate 1 has a memory cell formation region 4 and a P-channel MOS transistor formation. Planned region 5 and Planned region 6 for forming N-channel MOS transistor
The element is separated. Next, a gate oxide film 7 is formed on the P-type silicon substrate 1 in the regions 4 to 6. Next, a polycrystalline silicon film having a thickness of, for example, about 3000 Å is formed on the entire surface, and an impurity such as phosphorus is diffused into the polycrystalline silicon film. The gate electrodes 8 are patterned on the gate oxide films 7 respectively. The gate electrode 8a is patterned on the field oxide film 3 near the memory cell formation region 4. After that, source / drain regions 9a are formed by selectively implanting impurities such as arsenic into the surface of the P-type silicon substrate 1 in the memory cell formation scheduled region 4. In this case, the implantation amount of arsenic ions is, for example, about 1 × 10
^{It is set to 15} cm ⁻² at an acceleration at which arsenic ions do not penetrate the gate electrode 8.

Next, as shown in FIG. 1B, an interlayer insulating film is formed on the entire surface.
After depositing 10, a storage electrode 11 connected to one of the source / drain regions 9a is patterned on the interlayer insulating film 10 in the memory cell forming region 4. Next, this storage electrode 11
The capacitor film 12 and the plate electrode 13 are formed on the pattern.
Thereafter, the storage electrode 11, the capacitor film 12, and the plate electrode 13 are embedded in the interlayer insulating film 10 by further applying the interlayer insulating film 10. Next, a bit line 14 connected to the other source / drain region 9a is pattern-formed on the interlayer insulating film 10 in the memory cell formation scheduled region 4.

Next, as shown in FIG. 1 (c), the interlayer insulating film 10 in the P-channel MOS transistor formation region 5 and the N-channel MOS transistor formation region 6 is selectively removed. Then, an impurity such as boron is selectively implanted into the region 5 where the P-channel MOS transistor is to be formed under the condition that the implantation amount is, for example, about 3 × 10 ¹⁵ cm ⁻² , so that
A source / drain region 9b is formed on the surface of the substrate. Also, N
An impurity such as arsenic is selectively implanted into the channel MOS transistor formation region 6 at a dose of, for example, about 3 × 10 ¹⁵ cm ⁻² , so that the source / drain regions 9 c To form Note that these impurities are implanted at an acceleration at which the impurities do not penetrate the gate electrode 8.

In the semiconductor memory device configured as described above, the storage electrode 11, the capacitance film 12, and the plate electrode 13 form a stack capacitance of the memory cell, and charge is accumulated in the stack capacitance, as in the conventional case. Has become.

According to the method of this embodiment, after forming the stack capacitance and the interlayer insulating film 10 of the memory cell, the source / drain regions 9b and 9c of the P-channel MOS transistor and the N-channel MOS transistor are formed.
b, 9c is not heated by the stack capacitance forming step and the reflow step after the formation of the interlayer insulating film 10, etc.
The impurity does not diffuse more than necessary into the substrate.
Therefore, the P-channel MOS transistor and the N-channel M
It is possible to prevent the characteristics of the OS transistor from being deteriorated by heat.

2A to 2C are cross-sectional views showing a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in the order of steps. In the present embodiment, unlike the first embodiment, only the source / drain regions of the P-channel MOS transistor are formed in the final step, and therefore, are the same as those shown in FIGS. 1 (a) to 1 (c). Are denoted by the same reference numerals, and detailed description of those portions is omitted.

First, as shown in FIG. 2A, an N-type well 2 is selectively formed on the surface of a P-type silicon substrate 1. afterwards,
By selectively forming the field oxide film 3 on the P-type silicon substrate 1, the surface of the P-type silicon substrate 1 is formed with the memory cell formation region 4, the P-channel MOS transistor formation region 5, and the N-channel MOS transistor formation. The element is separated into the planned area 6. Then, P of the regions 4 to 6
A gate oxide film 7 is formed on the silicon substrate 1. Next, gate electrodes 8 are patterned on the gate oxide films 7 respectively. The gate electrode 8a is patterned on the field oxide film 3 near the memory cell formation region 4. Then, the memory cell formation scheduled area 4 and the N channel
P-type silicon substrate 1 in region 6 where MOS transistor is to be formed
The source / drain regions 9a and 9c are formed respectively on the surface of the substrate.

Next, as shown in FIG. 2 (b), an interlayer insulating film is formed on the entire surface.
After depositing 10, a storage electrode 11 connected to one of the source / drain regions 9a is patterned on the interlayer insulating film 10 in the memory cell forming region 4. Next, this storage electrode 11
The capacitor film 12 and the plate electrode 13 are formed on the pattern.
Thereafter, the storage electrode 11, the capacitor film 12, and the plate electrode 13 are embedded in the interlayer insulating film 10 by further applying the interlayer insulating film 10. Next, a bit line 14 connected to the other source / drain region 9a is pattern-formed on the interlayer insulating film 10 in the memory cell formation scheduled region 4.

Next, as shown in FIG. 2C, the interlayer insulating film 10 in the region 5 where the P-channel MOS transistor is to be formed is selectively removed. The source / drain regions 9b are formed on the surface of the N-type well 2 in the region 5 where the P-channel MOS transistor is to be formed.
To form

In the method of the present embodiment, the source / drain regions 9c of the N-channel MOS transistors are formed simultaneously with the source / drain regions 9a of the MOS transistors constituting the memory cell in the same manner as in the prior art. On the other hand, the source / drain region 9b of the P-channel MOS transistor is formed after the stack capacitance of the memory cell and the interlayer insulating film 10 are formed.
As a result, it is possible to prevent the P-channel MOS transistor from having a relatively large characteristic change due to the heat treatment.

According to this embodiment, when a semiconductor memory device having the same gate length is manufactured, the effective channel length of the P-channel MOS transistor can be increased by about 0.1 μm as compared with the related art. In addition, there is an advantage that an extraction electrode of an N-channel MOS transistor can be formed when the bit line 14 is formed.

In each of the embodiments described above, a dynamic RAM having a stack capacity has been described. However, the present invention can be applied to a dynamic RAM having another capacity structure. Examples of the dynamic RAM include a memory having a planar capacity, a memory having a trench capacity, and a memory having a stack capacity on a bit line.

[Effects of the Invention] As described above, according to the present invention, after forming the first MOS transistor, the capacitance, the bit line, and the interlayer insulating film of the memory cell, the second source transistor of the second MOS transistor is formed. Since the drain region is formed, the second source / drain region is not heated by the step of forming the capacitor and the step of forming the interlayer insulating film, and the impurity is not diffused into the substrate more than necessary. Absent. For this reason,
It is possible to prevent the transistor characteristics of the second MOS transistor from deteriorating due to heat.

[Brief description of the drawings]

FIGS. 1A to 1C are sectional views showing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention in the order of steps.
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention in the order of steps, and FIGS. 3A and 3B are diagrams illustrating a method of manufacturing a conventional semiconductor memory device. It is sectional drawing which shows a method in order of a process. 1; P-type silicon substrate; 2; N-type well; 3; field oxide film; 4; memory cell formation region; 5; P-channel MOS transistor formation region; 6; N-channel MOS transistor formation region; 7; gate Oxide film, 8, 8a; gate electrode, 9a, 9b, 9
c; source / drain region, 10; interlayer insulating film, 11; storage electrode, 12; capacitance film, 13; plate electrode, 14; bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device, comprising: providing a memory cell including a first MOS transistor and a capacitor in a first region of a semiconductor substrate and providing a second MOS transistor in a second region. And selectively forming a gate electrode on the semiconductor substrate in the second region via a gate insulating film, respectively, and selecting a first source / drain region on the surface of the semiconductor substrate in the first region. Forming an interlayer insulating film over the entire surface; selectively forming a capacitor connected to the first source / drain region on the interlayer insulating film; Selectively forming a bit line connected to the first source / drain region on a film; selectively removing the interlayer insulating film in the second region; The surface of the semiconductor substrate Selectively forming a second source / drain region, wherein the step of selectively forming the bit line is performed before or after the step of selectively forming the capacitor, and The method of manufacturing a semiconductor memory device, wherein the step of selectively removing the film is performed after the step of selectively forming the bit line and the step of selectively forming the capacitor. 2. A method for manufacturing a semiconductor memory device comprising a memory cell comprising a MOS transistor and a capacitor on a P-type semiconductor substrate, a P-channel MOS transistor, and an N-channel MOS transistor. Selectively forming a gate electrode in a region where a channel MOS transistor and an N-channel MOS transistor are to be formed via a gate insulating film, respectively;
A step of selectively forming a drain region and a source / drain region for an N-channel MOS transistor; a step of depositing an interlayer insulating film over the entire surface; and a step of forming a source / drain of the memory cell MOS transistor on the interlayer insulating film. Selectively forming a capacitor connected to a region; and forming a source and a source of the memory cell MOS transistor on the interlayer insulating film.
Selectively forming a bit line connected to a drain region; selectively removing the interlayer insulating film in a region where the P-channel MOS transistor is to be formed;
Selectively forming a source / drain region for a channel MOS transistor, wherein the step of selectively forming the bit line is performed before or after the step of selectively forming the capacitor, The method of manufacturing a semiconductor memory device, wherein the step of selectively removing the interlayer insulating film is performed after the step of selectively forming the bit line and the step of selectively forming the capacitor.