JP3107462B2 - Waveform synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform synthesizing circuit, and more particularly, to a waveform synthesizing circuit for shaping a waveform used in a transmitter (LAN) for a local area network (LAN). When the voltage value reaches a comparative reference voltage assigned in advance, a plurality of current switching circuits that output a current of a predetermined magnitude are provided in parallel, and the currents output from the plurality of current switching circuits are superimposed and added. And a waveform synthesizing circuit for outputting the same.

[0002]

2. Description of the Related Art A local area network (LAN) is used to connect word processors, personal computers, intelligent terminals and the like installed in relatively limited places such as premises. FIG. 1 schematically illustrates a basic configuration example of Ethernet as a representative of a so-called bus-type LAN. In FIG. 1, a coaxial cable 3 is used as a transmission cable, and a terminating resistor 1 of 50 ohm is connected to each end for impedance matching. Also coaxial cable 3
A transmitter 2 for connecting a terminal to the coaxial cable 3 as needed and enabling communication with other terminals is incorporated in the transmission path of the present invention. Various terminal devices such as a personal computer 6, a file server 5, and a printer 4 are connected to each transmitter 2. Mutual communication is performed between the personal computers 6, and the file server 5 and the printer 4 are shared by them. . In the case of Ethernet, so-called CSMA / CD
(Carrier sense multiple access with collision det
Section), and high-speed communication with a transmission pulse width of 50 ns or 100 ns using a Manchester code is performed on a transmission signal. The terminal device 4 is connected to the coaxial cable 3.
The circuit of the transmitter 2 that connects the to 6 etc. should have a smooth pulse current waveform with few harmonics in order to prevent noise on the transmission path and suppress deterioration of the transmission waveform. It is specified in the standard IEEE802.3. In order to satisfy this standard, a waveform synthesizing circuit is incorporated in the circuit of the transmitter 2.

FIG. 2 shows an example of a conventional waveform synthesizing circuit.
This circuit includes a plurality of current switching circuits that output a current of a predetermined magnitude when the voltage value of the input pulse input to the input terminal (IN1) 11 reaches a comparative reference voltage Vra to Vre assigned in advance. Provided in parallel (a to e in this embodiment)
5), a circuit that superimposes currents respectively output from the plurality of current switching circuits a to e and outputs the added current as an output current from the output terminal (OUT) 12. For example,
The comparison reference voltages Vra to Vre applied to the plurality of current switching circuits a to e respectively correspond to the voltage control setting terminals (VCS) 1 in FIG.
9, a predetermined current of a constant current circuit comprising a transistor 20 and a resistor 21 and a voltage drop due to bleeder resistors R1 to R5, and emitter follower transistors 13 to 13 functioning as low impedance buffers provided in respective current switching circuits a to e. 17 is determined by the forward voltage between the base and the emitter. An example of the assignment of the comparative reference voltages Vra to Vre is shown below.
8 is a value obtained by adding the forward voltage between the base and the emitter to the forward voltage between the base and the emitter of the emitter follower transistor 17 and the forward voltage between the base and the emitter of the emitter follower transistor 17.
re = −5.95 volts, and thereafter, the respective voltage drops due to the resistors R2 to R5 are added, and Vrd = −6.08 volts, Vrc
= -6.40 volts, Vrb = -6.56 volts, and Vra = -6.70 volts.

The operation in this case will be described with respect to the current switching circuit e. When the pulse voltage input to the input terminal IN1 drops below the potential of Vre = -5.95 volts, the differential transistors TR1 and I out of TR2
The transistor TR1 on the N1 side is turned off, and the transistor TR2 to which Vre is supplied by the transistor 17 is turned on to output (pull) current to the output terminal 12. Next, when the pulse voltage of the input IN1 reaches Vrd = −6.08 volts, the current switching circuit d is operated, and both currents of the current switching circuits d and e are superimposed and the currents are added and output. Thereafter, similarly, the currents of the current switching circuits c to a are added, and a current obtained by combining the output transition waveforms in a stepwise manner is output to the output terminal OUT. Thereafter, when the input pulse voltage rises, a stepwise output transition waveform is synthesized in the reverse order. Therefore, a synthesized pulse output waveform is obtained in which the pulse transition waveform is reduced by the input pulse voltage transition time (for example, the passage time of Vre to Vrd) in which the input pulse sequentially passes between the comparison reference voltages Vra to Vre. In this output pulse, the stepwise transition portion is smoothed by a simple low-pass filter at the next stage, and a pulse waveform having a smooth transition shape at both the rising and the falling is obtained.

[0005]

However, the above-described waveform synthesizing circuit has the following problems. FIG. 3 shows an output current waveform when the above-described waveform synthesizing circuit is used. FIG. 3A shows a waveform of an input pulse input to the input terminal IN1, and FIG. 3C shows an ideal output current waveform of the waveform synthesizing circuit for the input pulse. As shown in FIG. 3C, the waveform actually desired is a symmetrical waveform whose transition portion is smooth. However, actually, a waveform shown in FIG. 3B is output from a conventional waveform synthesis circuit. In the case of this waveform, the change immediately after the rise and fall of the input pulse is abrupt, and the left and right waveforms are asymmetric, so that the output waveform cannot be said to be sufficiently shaped. This is due to the wiring capacitance and output terminal OU on the circuit board or LSI chip.
The waveform (FIG. 3 (B)) becomes more remarkable when the current consumption is reduced due to the output impedance of T12 or the like and the circuit is to be made into an LSI. In this case, since the output waveform of FIG. 3B contains a harmonic component forming a sharply changing portion, high-frequency noise is easily generated on the transmission line, and therefore, the signal waveform propagating on the transmission line is greatly deteriorated. There is a problem to do. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a waveform synthesizing circuit having a smooth output current waveform and a small number of high frequency components.

[0006]

Means for Solving the Problems In order to solve the above-mentioned problems, the present inventor has found that during his research, the reason why the waveform shaping is insufficient is that the set value of the comparative reference voltage assigned to each current switching circuit is problematic. I thought there was. And
In the above-described waveform synthesizing circuit, the present invention is considered to be caused by the fact that the comparison reference voltage assigned to each current switching circuit is set to be the same at the time of rising and falling of an input pulse. did. That is, according to the configuration of the present invention, when the voltage or current value at the time of rising and falling of the input pulse reaches a comparison reference value assigned to each of them in advance , a voltage or current signal of a predetermined magnitude is obtained. A plurality of signal output switching means, a signal addition means for superimposing and outputting output signals from the plurality of signal output switching means, and detecting rise and fall of the input pulse and detecting rise of the input pulse. To the plurality of signal output switching means , a first comparison reference value having a predetermined difference between them is provided as the comparison reference value. And a comparison signal switching means for providing a second comparison reference value different from the first comparison reference value having a predetermined difference between them.

Further, the comparing signal switching means comprises a delay means for generating a delay pulse which is delayed a predetermined time relative to the input pulse, the comparison of the first comparison reference value and the second by the delay pulse Configuration to switch the reference value
May that. Further, between and before the first comparison reference value.
The predetermined difference provided between the second comparison reference values is more preferably a large value at the beginning of the transition of the rising or falling edge of the input pulse and a small value near the end of the transition.

[0008]

Since the comparison reference value output from the comparison signal switching means can be individually set for the rising time and the falling time of the input pulse, the difference between the respective comparison reference values can be adjusted. Different waveform shaping can be set separately for the rising transition waveform of the input pulse and its falling transition waveform. In addition, the delay means delays the input pulse applied to the signal output switching means by a predetermined time and provides it to the comparison signal switching means. Therefore, when shaping the rising waveform of the input pulse, the comparison signal switching means sends the comparison reference value to the signal output switching means. (For rising), the comparison signal switching means is switched by the delayed input pulse when the falling waveform of the input pulse is shaped, and the comparison signal switching means sends the comparison reference value (for falling) to the signal output switching means. Is given. Further, a plurality of signal output switching means
The difference between the comparison reference values between each other, a large value is set to the transition beginning of the rise and fall of the input pulse, because the smaller value is set at the transition completion side, it a smooth waveform as the start transition .

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 4 is a circuit diagram of a waveform synthesis circuit according to the present invention. FIG. 5 is a circuit diagram illustrating an example of the delay circuit. FIG. 6 is an explanatory diagram showing a relationship between an input pulse and a comparison reference value. FIG. 7 is a diagram illustrating an actual measurement example of an output waveform of a transmitter circuit using the waveform synthesis circuit of FIG. FIG. 8 is a circuit diagram showing one embodiment of a transmitter circuit using the waveform synthesizing circuit of FIG. FIG. 9 is a circuit diagram showing an example of the current subtraction circuit and the first and second stage current amplification circuits of FIG.

First, the configuration of the waveform synthesizing circuit will be described with reference to FIG. The same components as those in the conventional example (FIG. 2) are denoted by the same reference numerals, and description thereof is omitted. The waveform synthesizing circuit includes current switching circuits a to e as signal output switching means.
And a collector multi-connection circuit 60 of the output transistors in the current switching circuits a to e as signal addition means, and a comparison signal switching circuit 65 as comparison signal switching means. Next, a detailed configuration of the current switching circuits a to e will be described with the current switching circuit e as a representative. The constant current circuit including the differential switching transistors TR1 and TR2, the transistor 29 connected to the emitter common terminal of the transistors TR1 and TR2, and the resistor 30 enables high-speed switching operation by so-called ECL (emitter coupled logic). An input pulse is directly applied to the base terminal of the transistor TR1,
A comparison reference value, that is, the comparison reference voltage Vre described in the conventional example is applied to the base terminal of R2, and the magnitudes thereof are compared by the differential switching transistors TR1 and TR2. The difference from the conventional example is that the comparative reference voltage Vre is provided by a diode switch circuit in which the emitter terminals of the transistor 17 and the transistor 26 are multi-connected. These transistors 17, 26
One of two comparison reference voltages, which will be described later, is applied to the base terminal, and the transistor having the higher comparison reference voltage is turned on in the forward direction to supply the comparison reference voltage Vre.

Next, for the rising transition and the falling transition
A description will be given of a comparison signal switching circuit 65 that provides two comparison reference voltages for transfer to the current switching circuits a to e. The comparison signal switching circuit 65 includes a resistance bleeder circuit, a reference voltage switching circuit, and a delay circuit 33. The resistor bleeder circuit includes a first resistor bleeder circuit in which resistors R1, R2, R3, R4, and R5 are connected in series, and resistors R6, R7, and R5.
8, R9, and R10 are connected in series with a second resistor bleeder circuit. The first resistor bleeder circuit is connected to the base terminals of the transistors 13 to 17 as described in the conventional example, and the second resistor bleeder circuit is connected to the second resistor bleeder circuit. The bleeder circuit is a transistor 22
To 26 base terminals. Each of the resistor bleeder circuits divides a voltage output from a reference voltage switching circuit, which will be described later, according to the value of each resistor.
And reference values to the transistors 22 to 26 (see the comparison reference).
Voltage) .

The reference voltage switching circuit has substantially the same circuit configuration as each of the above-described current switching circuits a to e as shown in FIG. 4, and includes differential switching transistors 34 and 35, an additional transistor 36, and a resistor 37. , And switches the voltage supplied to the resistance bleeder circuit. An input pulse delayed from the delay circuit 33 is applied to the base terminal of the transistor 34 from the IN2 terminal.
Is supplied with a reference voltage VREF for comparison with the input pulse voltage. In this example, the transistor 28
To which a forward voltage is applied between the base and the emitter of the
The comparison reference voltages on the sides 6 to R10 are fixed, whereas the comparison reference voltages on the resistors R1 to R5 are changed by the potential applied from the collector load resistor 27 of the switching transistor 34 via the emitter follower of the transistor 18 . It is possible.

The delay circuit 33 is constituted by a circuit as shown in FIG. 5, and is provided between the input terminal IN1 and the input terminal (IN2) 32 of the comparison signal switching circuit 65, and is inputted to the input terminal IN1. This is to input the same pulse as the input pulse to the input terminal IN2 with a delay of a predetermined time. Note that the delay circuit 33 using two inverters shown in FIG. 5 is merely an example, and the present invention is not limited to this. With the interposition of the delay circuit 33, the rising or falling transition waveform of the pulse input from the input terminal IN1 is given to the IN2 terminal with a predetermined delay. In addition,
The delay time of the signal by the delay circuit 33 is at least longer than the rise and fall times of the input pulse.

In this embodiment, the resistors R1 to R5 are connected to the input terminal IN.
1 and a reference voltage (hereinafter, for example, Vrer and finally r (ris
e)), and resistors R6 to R10 are used for comparison reference voltages (hereinafter, for example, adding Vref and f (fall) at the end) used at the falling transition of the input pulse.
Create FIG. 6 shows an example of the comparison reference voltage with respect to the input pulse. These are set to the following values in this example, for example. (1) At the time of rising of the input pulse Vrer = -5.950 volts Vrdr = -6.055 volts Vrcr = -6.220 volts Vrbr = -6.430 volts Vrar = -6.700 volts (2) The rising of the input pulse When falling Vref = -5.950 volts Vrdf = -6.195 volts Vrcf = -6.400 volts Vrbf = -6.565 volts Vraf = -6.700 volts Therefore, in this embodiment, the resistors R1 to R10 The values are set as follows: R1 = 0.625K ohm R2 = 0.525K ohm R3 = 0.825K ohm R4 = 1.050K ohm R5 = 1.350K ohm R6 = 0.525K ohm R7 = 1.225K ohm R8 = 1.025K ohm R9 = 0.825K ohm R10 = 0.675K ohm

Next, the operation of the comparison signal switching circuit 65 will be described. When there is no input at the input terminal IN2, the transistor 34 is turned off.
Since the comparison reference voltage on the side of .about.R5 is set to be higher than the comparison reference voltage on the side of the resistors R6 .about.R10, the comparison reference voltages Vrar .about.Vrer are switched via the switching transistors 13-17 to the current switching circuit a. To e. On the other hand, when an input pulse is applied to the input terminal IN2, the transistor 34 turns on, the output voltage of the emitter follower transistor 18 decreases, and the resistors R1 to R5
The potential of the comparison reference voltage on the side is lower than the potential of the comparison reference voltage on the sides of the resistors R6 to R10. This causes the comparison reference voltages Vraf to Vref to be
To 26 are supplied to the current switching circuits a to e. The reference voltage VREF serving as a reference for this switching operation is set to the midpoint potential of the pulse voltage in order to detect both the rise and fall of the input pulse. Therefore, when the input pulse applied to the input terminal IN1, and sometimes rising transition of the input pulse, the input terminal IN2 delay circuit 3
3, the pulses are input with a delay, so that the comparison reference voltages Vrar to Vrer are changed to the switching transistors 13 to 17.
Ru given current switching circuit a~e through. Therefore,
As the power pulse rises, the applied comparative reference
The current switching circuit b → c sequentially from the current switching circuit a having a low pressure
→ d → e, and turn on each current to output terminal 12.
The current of the transistor TR2 of the circuits a to e is superimposed,
A current signal having a waveform that increases stepwise is synthesized.
Also, at the time of the falling transition of the input pulse, the input terminal I
The delayed pulse is input to N2, and the comparison reference voltages Vraf to Vref are changed to the switching transistors 22 to 2 this time.
6 to the current switching circuits a to e. And
The comparison reference voltage given in reverse to the rising transition is high.
From the current switching circuit e to the current switching circuit d → c → b →
a, and the output terminal 12 is connected to each current switching circuit a.
To the transistor TR2 in the order of?
A decreasing current-combined current signal is output. And
This output terminal 12 is connected to the step by a low-pass filter.
Rising transition by smoothing the transition
Pulse waveform with smooth transitions
can get.

FIG. 7 shows an actual measurement example of an output current waveform according to the present invention. The lower waveform (b) in FIG. 7 is the input waveform, and the upper waveform (a) is the output waveform obtained by the waveform synthesizing circuit of the present invention. In FIG. 7, the horizontal scale is 50 ns / div, and the vertical scale is 0.5 V.
/ Div. Thus, according to the present invention, the input terminal I
R1 and R2 are set independently so that the closer to the rising and falling moments, which are the sharply changing points of the voltage of the input pulse input to N1, the greater the potential difference between the comparison reference voltages. Because
Thus, it can be seen that the steep portion is shaped into a smooth waveform. According to the present invention, the output current waveform is shown in FIG.
It is possible to approach the ideal current waveform shown in
As a result, it can be seen that higher harmonic components of the output current from the output terminal OUT12 can be removed and the waveform distortion is reduced as compared with the conventional example.

FIG. 8 shows a LAN connecting a coaxial cable and a terminal device using a waveform synthesizing circuit 38 according to the present invention.
1 shows an embodiment of a transmitter circuit for use in the present invention. In the transmitter circuit shown in FIG. 8, in addition to the waveform synthesizing circuit 38, a current subtracting circuit 39, a first current amplifier 40 as a current amplification output circuit, and a second current amplifier 41
Are used, and their detailed circuit diagrams are shown in FIG. Since the waveform synthesizing circuit 38 has already been described, the current subtracting circuit 39, the first current amplifying circuit 40, and the second current amplifying circuit 41 will be described with reference to FIG. The current subtraction circuit 39 shown in FIG. 9 operates using an operation reference voltage from a bias circuit formed by a plurality of transistors and resistors on the left and center of the circuit. It is formed by a constant current circuit including a resistor 43. The reference current is output via the buffer transistor 44 which functions to reduce the Miller effect due to the collector-base capacitance of the transistor 42.
8 is reduced, and the difference current is input to the first current amplification circuit 40 of the next stage. Therefore, the current drawn by the waveform synthesizing circuit 38 becomes an output current whose phase is inverted by the current subtracting circuit 39 and is level-converted to a predetermined level.

The first current amplifying circuit 40 in FIG. 9 and the second current amplifying circuit 41 at the next stage share an eight-fold current amplifying part which performs about 80-fold current amplification as a whole. This current amplification stage performs a so-called differential amplifier type current amplification, and a base terminal of the differential transistor 46 corresponding to the inverting input terminal of the differential transistors 45 and 46 is short-circuited with the output transistor 47 to form a so-called voltage follower. The output of the current subtraction circuit 39 is input to the base terminal of the differential transistor 45 corresponding to the non-inverting input terminal. Further, a resistor 48 is connected to the emitter terminal of the output transistor 47, a resistor 49 is connected to the non-inverting input terminal, and the other terminals of the resistor 48 and the resistor 49 are connected in common, so that the second current amplification of the next stage is performed. Output to the circuit 41. In this case, since the voltages of the non-inverting input terminal and the inverting input terminal of the voltage follower become equal, the resistance 48
And the resistance ratio of the resistor 49 determines the current amplification factor.
In this case, the resistance 48: the resistance 49 = 1: 7, and an eight-fold current amplification is performed. The capacitor 50 of the differential amplifier limits the band to prevent oscillation and the like, but acts equivalently as a low-pass filter and removes the harmonic component of the step-like output current waveform from the waveform synthesis circuit 38. To make a smooth waveform.

The second current amplifying circuit 41 of FIG. 9 shares the remaining current amplification factor of 10 times of the first current amplifying circuit 40.
The output current from the first current amplifying circuit 40 is converted into a current in a drawing direction by a so-called current mirror circuit including a transistor 51, a transistor 52, and a resistor 53. Here, the transistor 51 and the transistor 52
Is designed with an area ratio of 1 to 10 on the chip, so that the output current flows ten times as much as the input current. The final output stage is N by so-called Darlington connection.
The PN output transistor 54 is connected to the transmission cable with high impedance. The resistor 55 is a 25 ohm resistor equivalently representing the terminating resistor of 50 ohms at both ends of the transmission cable. As described above, various preferred embodiments of the present invention have been described. However, it is needless to say that the present invention is not limited to the above-described embodiments, and that many modifications can be made without departing from the spirit of the invention. .

[0020]

By using the waveform synthesizing circuit according to the present invention,
Since the comparison reference voltage is set separately for the rising and falling edges of the input pulse, the reference voltage can be set differently between the transition immediately after the rising edge of the input pulse and the transition immediately after the falling edge.
In this case , different waveform control can be performed on the stepped current signal that is output . In other words, the rising edge of the input pulse
At the falling edge of each of the plurality of signal output switching means.
An appropriate comparison reference value can be given,
Its the rise time and the output current waveform at the time of the fall respectively
A smooth waveform can be obtained. Therefore, a waveform synthesizing circuit with less high-frequency distortion can be realized . In particular,
When the configuration of claim 3 is adopted, communication via the transmission path is performed.
In general, the signals that occur are transitions (rising or falling).
The change immediately after
By increasing the predetermined difference between the initial comparative reference values,
Of the signals output by the signal output switching means
The superimposition time interval is longer than the interval near the end of the transition
Therefore, it is possible to mitigate the change immediately after the transition,
The effect of enabling smooth waveform shaping with less harmonics
There is fruit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of Ethernet.

FIG. 2 is a circuit diagram showing an example of a conventional waveform synthesis circuit.

FIG. 3 is a timing chart showing an input pulse (A), a current waveform (B) synthesized with a conventional waveform, and a current waveform (C) synthesized with an ideal waveform.

FIG. 4 is a circuit diagram showing one embodiment of a waveform synthesis circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating an example of a delay circuit.

FIG. 6 is an explanatory diagram showing a relationship between an input pulse and a comparative reference voltage.

7A is an output waveform obtained by the waveform synthesis circuit of FIG. 4, and FIG. 7B is an input waveform to the waveform synthesis circuit.

FIG. 8 is a circuit diagram of a transmitter circuit using the waveform synthesis circuit according to the embodiment.

FIG. 9 shows the current subtraction circuit of FIG. 8, a first current amplifier,
FIG. 4 is a circuit diagram of a second current amplifier.

[Explanation of symbols]

 a to e signal output switching means 60 signal addition means 65 comparison signal switching means

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takahiko Nakao Nagano Pref. In-house (56) References JP-A-4-291812 (JP, A) JP-A-53-27749 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 5/08

Claims (4)

(57) [Claims] 1. An input pulse rising and falling
A plurality of signal output switching means for outputting a voltage or current signal of a predetermined magnitude when the voltage or current value at the time of reading reaches a comparative reference value assigned to each of them in advance; Signal adding means for superimposing and outputting an output signal; detecting rising and falling edges of the input pulse; and detecting a rising edge to the plurality of signal output switching means as the comparison reference value. Is provided, and at the time of falling detection, a different value is provided to the plurality of signal output switching means from the first comparison reference value provided with a predetermined difference therebetween as a comparison reference value. A comparison signal switching means for providing a second comparison reference value. Wherein said comparing signal switching means, said comprising a delay means for generating a delay pulse which is delayed a predetermined time relative to the input pulse, the second comparison of the first comparison reference value by said delay pulse 2. The waveform synthesis circuit according to claim 1, wherein the reference value is switched. 3. The method according to claim 1, wherein the first comparison reference value and the second comparison reference value are mutually different.
The predetermined difference provided therebetween comparison reference values 2, prior
Waveform synthesis circuit according to claim 1 or 2, wherein the transition beginning of the rise or fall a large value and in the vicinity of the transition ends, characterized in that given the small value of the serial input pulse. 4. A waveform synthesizing circuit according to claim 1, 2 or 3, a current subtracting circuit for subtracting a current signal output from the signal adding circuit of the waveform synthesizing circuit from a predetermined current value, and outputting the subtracted signal. In order to amplify and output the current signal from the current subtraction circuit to a predetermined value to drive the signal transmission line, a current amplification output circuit configured using a current differential amplification circuit and a current mirror current amplification circuit is provided. A transmitter circuit, comprising: