JP2944261B2 - Current amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current amplifying circuit, and more particularly, to a first transistor through which a current to be amplified flows and an emitter connected to a reference potential to which the emitter of the first transistor is connected. And a second transistor for current amplification having a base connected to the base of the first transistor, and two Darlington-connected suppressing transistors for suppressing fluctuations in the collector potential of the second transistor. And a current amplifying circuit having:

[0002]

2. Description of the Related Art FIG. 7 shows a conventional current amplifier circuit. Note that the resistor 120 may be a relatively large resistor, or in an extreme case, infinite. This circuit is a current amplifying circuit called a mirror circuit. If the current flowing through the resistor 120 is ignored, for example, two first transistors 100 are connected in parallel, and ten second transistors 102 are connected in parallel. by connecting, to multiply the collector current I ₀ of the first transistor 100 to 5 times the amplified current I ₂ which is an object to be amplified current of current input from the input terminal iN. Two transistors 1 connected in Darlington
04,106 is a suppression transistor stabilize the current I ₂ by suppressing the variation in the collector potential of the second transistor 102. The resistor 120 is inserted for waveform shaping amplified current I _1.

[0003]

However, the above-described current amplifier circuit has the following problems. The amplified current I ₀ decreases by the base current I ₂ of the second transistor 102. When the current I ₀ decreases, the amplified current I
_{1 will} also decrease. As shown in the above example, the larger the current multiplication, such as 10 times, the larger the amplification current I due to the current I _2.
There is a problem that the decrease of ₁ becomes remarkable. Moreover, the magnitude of the current I ₂ is affected by variations in the current amplification factor of the second transistor 102, the current multiplication factor of the amplifying circuit increases when there is also a problem that the variation can not be neglected. Therefore, the present invention can suppress a decrease in the amplified current due to the base current of the second transistor,
An object of the present invention is to provide a current amplifier circuit that can suppress the influence of variations in current amplification factor.

[0004]

To solve the above-mentioned problems, the present invention has the following arrangement. That is, a current amplifying device in which the first transistor through which the current to be amplified flows, the emitter is connected to a reference potential to which the emitter of the first transistor is connected, and the base is connected to the base of the first transistor. A second transistor; two Darlington-connected suppressing transistors for suppressing fluctuations in the collector potential of the second transistor ;
Between the base and collector of the transistor
In the current amplification circuit and a third transistor having a base connected respectively between the emitters of the two suppression transistor, the collector and the emitter in a state in which the collector and base connected is connected 4 And a transistor.

[0005]

[Operation] The operation will be described. By connecting the third transistor between the base and the collector of the first transistor, the base current of the second transistor can be supplied by the amplified current of the third transistor. The current that flows as the base current may be small, and the decrease in the current to be amplified can be suppressed. Further, since the decrease in the current to be amplified due to the base current of the second transistor is suppressed, the influence of the variation in the current amplification factor of the second transistor can be reduced. In particular, the collector of the fourth transistor whose collector and base are connected between the emitters of the two suppression transistors
And the emitter, the oscillation caused by the third transistor can be prevented.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First, FIG. 4 shows a circuit diagram of a current amplifier circuit which is a premise proposed by the inventor of the present invention. In the figure, reference numeral 10 denotes a first transistor, and an input terminal IN
The collector current I ₀ of the input current input from the flow as the amplified current. The first transistor 10 has an arbitrary number of basic transistors (for example, two) in the circuit configuration.
They are connected in parallel. 12 is a second transistor flows a collector current I ₁ as amplified current. The second transistor 12 also has an arbitrary number (for example, 20) of basic transistors connected in parallel in the circuit configuration.
The multiplication factor (current I ₁ / current I ₀ ) of the amplification current I ₁ can be determined by the number of the first transistors 10 and the number of the second transistors 12. That is, if the current densities of the first transistor 10 and the second transistor 12 are equal, the current multiplication factor is equal to the ratio of the areas of the first transistor 10 and the second transistor 12. For example, if the number of the first transistors 10 is two and the second transistor If the number of transistors 12 is 20, the current multiplication factor is 10 times. The emitter of the second transistor 12 is the first
And the base of the second transistor 12 is connected to the base of the first transistor 10 while the emitter of the transistor 10 is commonly connected to the reference potential terminal VEE to which the emitter is connected.

[0007] Reference numerals 14 and 16 denote transistors for suppression, which are connected in a two-stage Darlington connection in order to suppress fluctuations in the collector potential of the second transistor 12. In this embodiment, two first-stage transistors 14 are connected in parallel, while ten second-stage transistors 16 are connected in parallel. The base voltage VA of the transistor 14
Is constant. Reference numeral 18 denotes a third transistor, which includes the first transistor 10 and the second transistor 12.
The bases are connected to the collectors of the first transistor 10. The third transistor 18 is a first transistor 1 which is a current to be amplified.
Current amplification is performed using a small current i shunted from the collector current I _{0 of 0} as a base current, and a current I ₂ that is a part of the amplified current I ₃ is supplied as a base current of the second transistor 12. As a result, the decrease in the amplified current I ₀ can be made as small as possible so as to be independent of the current amplification. Further, by making the base current of the second transistor 12 as small as possible by the third transistor 18, it is possible to eliminate the influence on the current multiplication factor due to the variation of the current amplification factor of the second transistor 12. it can. Resistor 20 is inserted for waveform shaping amplified current I _1.

Next, an embodiment of the present invention will be described with reference to FIG. The embodiment is an improvement of the circuit shown in FIG. 4, and the same components are denoted by the same reference numerals and description thereof will be omitted. In FIG. 4, since the third transistor 18 is provided, the input impedance at the input terminal IN may go in the negative direction. This is because the collector potential of the second transistor 12 also fluctuates due to the change in the current flowing through the resistor 22, and this fluctuation is fed back to the base of the transistor 12 by the parasitic capacitance between the base and collector of the transistor 12. In the present embodiment, this oscillation in FIG. 4 can be prevented. In FIG. 1, reference numeral 24 denotes a fourth transistor, whose base and collector are connected between the emitter of the transistor 14 and the base of the transistor 16 which are Darlington-connected, and whose emitter is connected to the emitter of the transistor 16 and the second transistor. Connected to the midpoint of the collector of transistor 12. Fourth transistor 2
4 are connected as described above, the resistor 22 shown in FIG.
Unlike this, the voltage fluctuation due to the current change is small, and the fluctuation of the emitter potential of the transistor 16, that is, the collector potential of the second transistor 12 can be suppressed. Therefore, the fourth transistor 24 can suppress the fluctuation of the collector potential of the second transistor 12 together with the suppression transistors 14 and 16, thereby preventing the oscillation.

FIG. 2 shows a graph (frequency in the range of 10 MHz to 1 GHz) comparing the input impedance of the circuit shown in FIG. As is clear from the graph, in the case of FIG. 4, the real part of the impedance sometimes partially enters the negative direction. Since the real part can be regarded as a substantial resistance, a negative resistance means generation of energy, and oscillation occurs in the circuit. On the other hand, in the embodiment, since the real part does not enter the negative direction, it is understood that oscillation can be prevented. Next, the dependency of the current amplification factor of the second transistor 12 in the embodiment (same in FIG. 4) will be described with reference to FIG. In the conventional circuit, the output voltage greatly changes due to the change in the current amplification factor. However, in the embodiment, since the change is small, the second transistor 1
It can be seen that the influence of the variation in the current amplification factor of No. 2 is extremely small.

Next, an example of a circuit using the current amplifying circuit of the embodiment will be described with reference to FIG. This circuit is a transceiver circuit for connecting a coaxial cable for forming a network and a terminal device connected to the coaxial cable in a communication network (LAN or the like). Reference numeral 50 denotes a waveform synthesizing circuit. When the voltage value of the input pulse reaches a comparative reference voltage assigned in advance, a plurality of current switching circuits 52 for switching a current of a predetermined magnitude are provided in parallel. This circuit superimposes and outputs the current output from the switching circuit 52. The comparison reference voltage is set by the magnitude of the voltage drop resistor 54 provided in each current switching circuit 52, and the potential difference between the comparison reference voltages is set small in order to reduce the rise and fall of the output. On the other hand, it is set to be large in order to make it large. As described above, the waveform synthesizing circuit 50 is required by international standards and the like to control the rising and falling edges and to make the waveform of the current to be transmitted smooth in order to prevent noise. Is what it is. The output current whose waveform has been synthesized by the waveform synthesis circuit 50 enters a current subtraction circuit 56 in the next stage, and a stable subtraction current is generated.
The current subtraction circuit 56 includes a transistor 58 for flowing a current to be subtracted.
A transistor 60 connected in series with the transistor 58, and the base of the transistor 60 has two voltage stabilizing transistors 62, 64 having different polarities from each other. And the emitter follower. Therefore, the voltage stabilizing transistor 6 is
Since the impedances in the 2,64 directions appear in parallel, they are small both for noise in the upward direction and noise in the downward direction. Therefore, even if the collector voltage of the transistor 60 fluctuates and the parasitic capacitance between the base and collector is charged and discharged, the base voltage of the transistor 60 can be stabilized, and the fluctuation of the subtraction current and the distortion of the current waveform can be prevented. Has become.

The current output from the current subtraction circuit 56 is amplified by a first-stage amplification circuit 66. In the example of FIG.
And 70 are set to 8: 1, so that an eight-fold amplification is performed. The current amplified by the first-stage amplifier circuit 66 is further amplified by a second-stage amplifier circuit 72 using the current amplifier circuit according to the embodiment of the present invention. In the second-stage amplifier circuit 72, the area ratio between the basic transistors 74 and 76 is 2:20 in this example, and 10-fold amplification is performed. Therefore, the first stage amplifier circuit 66 and the second stage amplifier circuit 72 perform a total of 80-fold current amplification, and a signal is sent from the output point 78 to the terminal device. FIG. 6 shows the waveform of the output current. Note that the circuit shown in FIG. 4 may be used as the second stage amplifier circuit 72 of the transceiver circuit as long as no oscillation occurs. As described above, various preferred embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention.

[0012]

When the current amplifier circuit according to the present invention is used,
By connecting the third transistor between the base and the collector of the first transistor, the base current of the second transistor can be supplied by the amplified current of the third transistor. The current that flows as the base current may be small, and the decrease in the current to be amplified can be suppressed. When the decrease in the amplified current due to the base current of the second transistor is suppressed, the influence of the variation in the current amplification factor of the second transistor on the current multiplication factor can be reduced. In particular, the effect of two suppression transistors
Collector and base connected between transmitters
And the collector of the fourth transistor of
Since the connection is made, it is possible to prevent the oscillation caused by the third transistor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a current amplifier circuit according to the present invention.

FIG. 2 is a graph comparing the input impedance of the embodiment and the circuit of FIG. 4;

FIG. 3 is a graph comparing the dependency of the output voltage and the current amplification factor of a second transistor between the example and the conventional example.

FIG. 4 is a circuit diagram showing a current amplification circuit which is a premise of the current amplification circuit according to the present invention.

FIG. 5 is a circuit diagram of a transceiver circuit using the current amplifier circuit of the embodiment.

FIG. 6 is a graph showing a waveform of an output current of the transceiver circuit.

FIG. 7 is a circuit diagram showing a conventional current amplifier circuit.

[Explanation of symbols]

10 first transistor 12 and the second transistor 14 transistor 18 transistor 16 inhibited for suppressing the third transistor 24 fourth transistor I ₀ be amplified current I ₁ amplified current

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takahiko Nakao Nagano Pref. In-house (56) References Japanese Utility Model Sho 56-152414 (JP, U) Special Table 57-501154 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03F 3/34- 3/36

Claims (1)

(57) [Claims] 1. A first transistor for flowing a current to be amplified, an emitter connected to a reference potential to which an emitter of the first transistor is connected, and a base connected to the first transistor.
Current amplification second connected to the base of the transistor
D between the two suppressing transistors Linton connected, the base and collector of said first transistor - and of the transistor, da order to suppress the fluctuation of the collector potential of the second transistor
A third transistor to which the mitter and the base are connected respectively
In the current amplification circuit and a motor, between the emitters of the two suppression transistor,
With the collector and base connected , the collector and emitter
And a fourth transistor connected to the current amplifier.