JP3106450B2 - Power measurement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring the power of an AC signal, and more particularly to a measuring apparatus for obtaining a power value by a sum-average method using a digital sampling method.

[0002]

2. Description of the Related Art When the power of an AC signal is measured by the sum averaging method using a digital sampling method, an error E occurs as shown in FIG. 3 when the measurement cycle is not an integral multiple of the cycle of the power waveform. In FIG. 3, T indicates a measurement period.

[0003] In order to remove the error caused by the difference between the measurement period and the waveform period of the signal under measurement, the following method has conventionally been adopted. A phase-locked oscillator that causes the sampling frequency generated in the measuring instrument to follow the frequency of the signal under measurement is used. The power measurement is performed over a number of periods of the signal under measurement to reduce errors. The period of the signal under measurement is measured, and the measurement period is determined. However, this means must use a high-quality phase-locked oscillator that operates over a wide frequency range. The other means has a longer measurement cycle, and the second means has no synchronization between the cycle of the signal under measurement and the power measurement period. Therefore, when the period of the signal under measurement changes, the measurement period does not become a positive multiple of the period of the signal under measurement. For example, the conventional solutions have not always been satisfactory.

SUMMARY OF THE INVENTION It is an object of the present invention to accurately measure electric power in a short measurement period without using a high-grade phase-locked oscillator or the like and even when the period of input AC changes. It is an object of the present invention to realize a measuring device that can perform the measurement.

[0004]

According to the present invention, there is provided an analog-to-digital converter for converting an AC voltage and a current to be measured into digital signals according to a sample clock, respectively. A signal corresponding to the period of the AC voltage or current is applied to its clock terminal to output a high-level signal for an integral multiple of the period of the AC voltage or current. , And the output signal of the flip-flop supplies a sample clock to the two analog-to-digital converters via a gate during a high level period.

[0005]

According to the present invention, the high-level period of the output signal of the flip-flop is an integral multiple of the period of the input voltage or current.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a circuit diagram of an embodiment of a power measuring device according to the present invention. In the figure, v is the voltage in the AC circuit to be measured,
i indicates a current. Reference numerals 1 and 2 denote input voltages v and currents i and voltage and current input circuits for converting currents i into appropriate values, respectively. An analog / digital converter (hereinafter, referred to as an A / D converter) that converts the signal into a signal. Reference numeral 5 denotes a digital signal processor for calculating the effective power by performing the operation of the following equation (1) by the sum average method based on the instantaneous output values of the A / D converters 3 and 4. (1 / n) ⁿ Σ _{n = 1} (vK · ik) (1) In equation (1), vK represents an instantaneous value of the input voltage v, and ik represents an instantaneous value of the input current i.

Reference numeral 6 denotes a microprocessor (hereinafter referred to as a microprocessor) for controlling the entire circuit and displaying the active power obtained by the digital signal processor 5 on a display unit 7.
CPU). 8 is a sample clock oscillator, and 9 is an AND gate. The output of sample clock oscillator 8 is applied as one input to gate 9;
The output of gate 9 is applied to A / D converters 3 and 4 as a sample clock. Reference numeral 10 denotes a switch whose input terminal is connected to the output terminals of the voltage / current input circuits 1 and 2, and reference numeral 11 denotes a waveform shaping circuit. The switch 10 is controlled by the CPU 6 and sends either the output signal of the voltage input circuit 1 or the output signal of the current input circuit 2 to the waveform shaping circuit 11. The waveform shaping circuit 11 outputs a square wave signal in which high (HIGH) and low (LOW) are inverted each time a signal inputted thereto crosses a predetermined level.

Reference numeral 12 denotes a tentative measurement time generator for outputting a high-level signal for a predetermined period. Reference numeral 13 denotes an output terminal of the waveform shaping circuit 11 connected to a clock (CK) terminal, and an output terminal of the tentative measurement time generator 12 to D. The output terminal Q is a D-type flip-flop connected to the other input terminal of the AND gate 9 (hereinafter, referred to as D-FF). The operation of the apparatus of the present invention having such a configuration will be described with reference to the waveform diagram of FIG.

FIGS. 2A and 2B show the waveforms of the AC voltage v and the AC current i to be measured. These AC voltage v and current i are applied to A / A via voltage and current input circuits 1 and 2, respectively.
After being converted into a digital signal by the D converters 3 and 4, the digital signal is applied to a digital signal processor 5, where a digital operation is performed, and an active power P is obtained. The switch 10 is driven under the control of the CPU 6 and passes either the voltage v or the current i. The output waveform of the waveform shaping circuit 11 when the voltage v is selected is shown in FIG. . The output of the waveform shaping circuit 11 is the CK of the D-FF 13
Added to terminal.

On the other hand, the provisional measurement time generator 12 generates a high-level signal for a certain period at a timing as shown in FIG.
Added to terminal. The D-FF 13 outputs the Q output waveform to the next waveform shaping circuit applied to the CK terminal after the output of the provisional measurement time generator 12 applied to the D terminal becomes high as shown in FIG. 11 goes high when the output rises, the output of the temporary measurement time generator 12 goes low, and then goes low at the next rise of the output of the waveform shaping circuit 11. The output of the D-FF 13 is applied to the AND gate 9 as a gate control signal.

The sample clock oscillator 8 oscillates a clock as shown in FIG. 2 (g), and this clock is applied to an AND gate 9. This clock is DF
While the Q output of F13 is at the high level, it passes through the gate 9 as shown in FIG. The clock that has passed through the gate 9 is applied to the A / D converters 3 and 4 as a sampling signal. The A / D converters 3 and 4 sample the outputs of the voltage input circuit 1 and the current input circuit 2 with this clock and convert them into digital signals.

Here, D is selected by the switch 10 and D
The signal applied to the CK terminal of the FF 13 corresponds to the cycle of the input AC voltage v (or current i) to be measured, and the AND gate 9 is opened for an integral multiple of this cycle to sample
Since the clock is given to the A / D converters 3 and 4 to perform digital conversion, the measurement cycle is an integral multiple of the power waveform shown in FIG. 2C, and the error E shown in FIG. Does not occur. The active power measured in this way is
It is displayed on the display 7 under the control of 6.

[0013]

According to the present invention, the sample clock is configured to be input to the analog-to-digital converter for a period that is an integral multiple of the period of the power waveform, so that the measurement period is an integral multiple of the period of the power waveform. Thus, it is possible to obtain a device that does not cause an error due to the measurement cycle. In addition, since an expensive phase-locked oscillator is not required, the measurement time is short, and the period measurement and the power measurement period are simultaneous, the measurement period is always an integral multiple of the power waveform period even if the power waveform period changes. The relationship will be maintained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a power measuring device according to the present invention.

FIG. 2 is a waveform chart for explaining the operation of the measuring apparatus of FIG.

FIG. 3 is a waveform diagram for explaining the operation of a conventional power measuring device.

[Explanation of symbols]

 3, 4 analog-to-digital converter 8 sample clock oscillator 10 switch 13 D-type flip-flop

Claims (1)

(57) [Claims] An apparatus having an analog-to-digital converter for converting an AC voltage and a current to be measured into a digital signal in accordance with a sample clock, and calculating power from outputs of the two analog-to-digital converters. A D-type flip-flop that outputs a high-level signal for an integral multiple of the AC voltage or current cycle when a signal corresponding to the AC voltage or current cycle is applied to its clock terminal; A power measuring apparatus, wherein a sample clock is supplied to both of the analog-to-digital converters via a gate while an output signal of a flip-flop is at a high level.