JP3104923B2 - Data side drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving circuit for supplying a video signal to a data line of a matrix type display device, and more particularly to a data driving circuit having a function of reducing a driving frequency of a horizontal driver and an aperture compensation function. It is about.

[0002]

2. Description of the Related Art As a conventional data-side drive circuit, for example, as described in Japanese Patent Application Laid-Open No. 59-29295, a circuit called a pre-sampling circuit composed of a plurality of sample and hold circuits is used. In some cases, the input video signal is subjected to serial / parallel conversion processing and guided to a horizontal driver, thereby reducing the driving frequency of the horizontal driver. Hereinafter, the configuration and operation of the data side driving circuit will be described with reference to FIGS.

FIG. 13 is a circuit diagram showing a conventional data-side driving circuit, and FIG. 14 is a waveform diagram showing waveforms of main signals in FIG. In FIG. 13, an active matrix type liquid crystal display device which is an active matrix type display device is used as the matrix type display device.

[0004] In FIG. 13, 10 is an active matrix type liquid crystal display device, the gate lines G _1, ..., G _n and the data lines L _1, ..., has a L _m (one drawer). Reference numeral 9 denotes a gate-side drive circuit. Reference numeral 50 denotes a pre-sampling circuit for performing a serial-parallel conversion process, and includes four sample-and-hold circuits 3 each including analog switches A to D, hold capacitors Ca to Cd, and buffer amplifiers 1A to 1D.
A to 3D and a four-phase clock generation circuit 2 for controlling the analog switches A to D. HD is a horizontal driver, and analog switches S ₁ ,.
_m and a shift register 8 for controlling the opening and closing of the analog switches S ₁ ,..., S _m . Note that the pre-sampling circuit 50 and the horizontal driver HD constitute a data-side driving circuit.

In FIG. 14, 2A to 2D each represent 4
The clock from the phase clock generation circuit 2 is shown, and 1U to 5U respectively show the sequential selection pulses from the shift register 8. When these signals are "H", the analog switches are turned on and "L" It turns off when.

The analog video signal input from the input terminal 1 is a clock 2A from time t ₁ to time t ₂ shown in FIG.
During the “H” period, the analog switch A in the sample-and-hold circuit 3A is turned on, sampled, held by the hold capacitor Ca, and then output as the sampling output signal 4A via the buffer amplifier 1A. . And the sampling output signal 4A is
Only during the period of "H" of the sequential selection pulse 1U from time t ₁ shown in FIG. 14 of t _4, by the analog switch S ₁ is turned on, is supplied to the data line L _1, and drives the data line L _1. Then, sequentially selected pulse 1U at time t ₄
There becomes "L", the analog switch S ₁ is turned off, the driving of the data line L ₁ is completed.

That is, by using the pre-sampling circuit 50, the video signal that has entered the period from the time t ₁ to the time t ₂ is held from the time t ₁ to the time t ₄ (that is, a period for four pixels). Therefore, the ON period T _max of the analog switch S ₁ can be set to a period corresponding to four pixels. Therefore, the ON period T of the analog switch S _1
max can be four times longer than when the presampling circuit 50 is not used.
Can be reduced by a factor of four. By repeating the above operation, all data lines L ₁ ,
..., is driving the L _m.

On the other hand, as the conventional aperture compensation circuit, there is the following one. Hereinafter, description will be made with reference to FIGS. FIG. 15 is a block diagram showing a conventional aperture compensating circuit, and FIG. 16 is a waveform diagram showing waveforms of main signals in FIG.

In FIG. 15, a video signal 36 input from an input terminal is input to a first signal delay circuit 37, and a delayed output signal 38 is supplied to a second signal delay circuit 39. Delayed output signal 40 of second delay circuit 39
Is added to the input video signal 36 by an adder 41 to obtain a signal 42. The signal 42 is output to a coefficient unit 43
For example, the amplitude is halved, and the output 4 of the coefficient unit 43 is
4 is added to the delay output signal 38 of the first delay circuit 37 by an adder 45, and thereafter, a high-frequency component such as noise is removed by a low-pass filter 46, and a contour component signal 47 is obtained. The contour component signal 47 is added by the adder 48 to the delayed output signal 38 of the first delay circuit 37,
A video signal 49 with a contour component is obtained. Such an aperture compensating circuit is disclosed in, for example,
No. 83 is described.

[0010]

By the way, in order to add an aperture compensation function to a conventional data-side drive circuit having a function of reducing the drive frequency of the horizontal driver (that is, having a pre-sampling circuit). In addition, the aperture compensation circuit described above must be provided separately, and there is a problem that the circuit scale becomes large. Therefore, an object of the present invention is to provide a data-side drive circuit having a function of reducing the drive frequency of a horizontal driver and an aperture compensation function without increasing the circuit scale.

[0011]

In order to achieve the above-mentioned object, the present invention comprises a plurality of sample-and-hold circuits for sequentially sampling input video signals and holding and outputting the samples for a predetermined period. A plurality of arithmetic processing units for inputting at least two or more output signals output from each sample-and-hold circuit in the pre-sampling circuit and multiplying by a predetermined coefficient and adding and outputting the signals; A coefficient adding circuit having a circuit, and a horizontal driver for sequentially supplying output signals output from each arithmetic processing circuit in the coefficient adding circuit to each data line of the matrix display device and driving each data line. , Constitute a data side drive circuit.

[0012]

According to the above construction, the output signals from the plurality of sample-and-hold circuits having a predetermined time lag (for one pixel) are subjected to coefficient addition by the coefficient addition circuit to form an aperture-compensated signal. By providing the data to the driver, a data-side drive circuit having an aperture compensation function can be realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. In each of the following embodiments, a case where a so-called window pattern signal is used as a waveform of an input video signal will be described as an example. FIG. 1 shows the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a data-side drive circuit as an example of FIG.

[0014] In FIG. 1, 10 is an active matrix type liquid crystal display device, the gate lines G _1, ..., G _n and the data lines L _1, ..., has a L _m (one drawer). Also,
9 is a gate side drive circuit. Reference numeral 50 denotes a pre-sampling circuit for performing a serial-parallel conversion process.
3D, and a four-phase clock generation circuit 2 for controlling the analog switches A to D. Reference numeral 5 denotes a coefficient adding circuit. HD is a horizontal driver, which includes analog switches S ₁ ,..., S _m and analog switches S ₁ ,
..., a shift register 8 for controlling the opening and closing of the S _m, in being configured. The pre-sampling circuit 50, the coefficient adding circuit 5, and the horizontal driver HD constitute a data-side driving circuit.

FIG. 2 is a circuit diagram showing an equivalent circuit of one pixel portion of the active matrix type liquid crystal display device 10 in FIG. In FIG. 2, LC is a liquid crystal, Tr MOS transistors, G ₁ denotes a gate line, L ₁ is a data line.

FIG. 3 shows a coefficient adding circuit 5 in FIG.
It is a block diagram which shows one specific example. In FIG. 3, 1
Numerals 3, 14, 15, and 16 denote arithmetic processing circuits, each comprising an adder 11 and a coefficient unit 12. FIG.
Is a circuit for realizing the effect of correcting a contour component (so-called preshoot) that emphasizes immediately before the change of the image change signal.

FIG. 4 is a waveform diagram showing waveforms of main signals in FIG. 1 when the coefficient adding circuit 5 in FIG. 3 is used. Next, the operation of this embodiment will be described.

In FIG. 4, reference numerals 2A to 2D denote clocks from the four-phase clock generation circuit 2, respectively. When these clocks are "H", the analog switches A to D are turned on, and when they are "L", they are turned off. Becomes

The video signal input from the input terminal 1 is
During the period of "H" of the clock 2A of t ₂ from time t ₁ shown in FIG. 4, by the analog switch A of the sample and hold circuit 3A is turned on, it is sampled, after being held in the hold capacitor Ca, the buffer amplifier 1A, as a sampling output signal 4A, a coefficient adding circuit 5
Output to Similarly, during the “H” periods of the clocks 2B, 2C, and 2D, the sample and hold circuits 3B, 3C, and 3D
When the analog switches B, C, and D in D are turned on, sampling is performed, and the hold capacitances Cb, Cc, and Cd are held.
Buffer amplifiers 1B, 1C, 1D
Are output to the coefficient adding circuit 5 as sampling output signals 4B, 4C, and 4D.

On the other hand, as shown in FIG.
Is divided into four processing circuits 13, 14, 15, and 16, each of which receives two sampling output signals that are temporally adjacent to each other. That is, the input signals are (4A, 4B), (4B, 4C),
The combination is (4C, 4D), (4D, 4A).

Here, taking the arithmetic processing circuit 13 in the coefficient adding circuit 5 as an example, the sampling output signal 4B is supplied to the coefficient unit 12, where it is multiplied by (−1 / K) by the coefficient unit 12 and then added. The signal is added to the sampling output signal 4A by the detector 11 to obtain an output signal 5A. Similarly, the arithmetic processing circuit 1
4, 15 and 16, the output signals 5B and 5
C and 5D are obtained.

[0022] Then, the output signal 5A formed by the arithmetic processing circuit 13 of the coefficient adder circuit 5, only the sequential period of "H" of the selection pulse 1U from the shift register 8, the analog switch S ₁ is turned on As a result, the data line L ₁
It is supplied to and drives the data line L _1.

Similarly, the output signals 5B, 5C and 5D generated by the arithmetic processing circuits 14, 15 and 16 are also analog-only during the "H" period of the sequential selection pulses 2U, 3U and 4U from the shift register 8. Switches S ₂ , S ₃ , S ₄
There by turning on, is supplied to the data line _{L 2, L 3, L 4} , and drives the data lines _{L 2, L 3, L 4} .

By repeating the above operation, the output signal 5A is output to the data lines L ₁ , L ₅ , L ₉ ,..., And the output signal 5B is output to the data lines L ₂ , L ₆ , L ₁₀ ,. 5C data lines _{L 3, L 7, L 11} , ... , the output signal 5D is a data line _{L 4, L 8, L 12} , ..., the L _m, are supplied to drive the respective data lines.

[0025] Here, when attention is focused on the output signal 5D, the voltage drops from time t ₁ during the t _4, it emphasizes the previous change of the image change signal preshoot voltage waveform occurs.
However, the pre-shoot, since only been held by three periods of pixels as shown in FIG. 4, the analog switches S _1, ..., ON period T _max of S _m is conventional as shown in FIG. 14 From the period corresponding to four pixels, as shown in FIG.
This is shortened to a period corresponding to pixels.

As described above, according to the present embodiment, when the coefficient adding circuit 5 shown in FIG. 3 is used, the sample output signals 4A to 4D from the four sample and hold circuits 3A to 3D are used.
Is effectively used, a correction effect of only the preshoot shown in the output signal 5D can be generated on the screen of the active matrix liquid crystal display device 10.

FIG. 5 shows the coefficient adding circuit 5 in FIG.
FIG. 13 is a block diagram showing another specific example of FIG. The coefficient adding circuit 5 shown in FIG. 5 is a circuit for realizing a correction effect of a contour component (so-called post-shoot) that emphasizes immediately after the change of the image change signal.

FIG. 6 is a waveform diagram showing waveforms of main signals in FIG. 1 when the coefficient adding circuit 5 in FIG. 5 is used. Next, the operation will be described.

The coefficient adding circuit 5 shown in FIG. 5 is different from the configuration shown in FIG. 3 in that four arithmetic processing circuits 13, 14, 15, and 16 in the coefficient adding circuit 5 each have a position equivalent to three pixels. The point is that two sampling output signals having a phase difference are input. That is, the input signals are (4A, 4D), (4B, 4A), (4C, 4B),
(4D, 4C).

Here, taking the arithmetic processing circuit 13 in the coefficient adding circuit 5 as an example, the sampling output signal 4D is supplied to the coefficient unit 12, where it is multiplied by (−1 / K) by the coefficient unit 12 and then added. The signal is added to the sampling output signal 4A by the detector 11 to obtain an output signal 5A. Similarly, the arithmetic processing circuit 1
4, 15 and 16, the output signals 5B and 5
C and 5D are obtained.

Thereafter, the output signal 5 formed by the arithmetic processing circuits 13, 14, 15, 16 in the coefficient adding circuit 5
A, 5B, 5C and 5D are connected to the data lines L ₁ and L ₂ by turning on the analog switch S ₁ only during the “H” period of the sequential selection pulses 1U, 2U, 3U and 4U from the shift register 8. , L ₃ , L ₄ and the data lines L ₁ ,
L _2, to drive the L _3, L _4.

By repeating the above-described operation, the output signal 5A is output to the data lines L ₁ , L ₅ , L ₉ ,..., And the output signal 5B is output to the data lines L ₂ , L ₆ , L ₁₀ ,. 5C data lines _{L 3, L 7, L 11} , ... , the output signal 5D is a data line _{L 4, L 8, L 12} , ..., the L _m, are supplied to drive the respective data lines.

Here, paying attention to the output signal 5A, the voltage rises during a specific period, and a post-shoot voltage waveform that emphasizes immediately after the change of the image change signal is generated. But,
Since this post-shoot is held only for a period of three pixels as shown in FIG. 6, the analog switch S
_1, ..., similarly to the on-period T _max of S _m is shown in FIG. 4,
This is reduced from the conventional period of four pixels to the period of three pixels.

As described above, according to this embodiment, when the coefficient adding circuit 5 shown in FIG. 5 is used, the sample output signals 4A to 4D from the four sample and hold circuits 3A to 3D are used.
Is effectively used, a correction effect of only the post-shoot shown in the output signal 5A can be generated on the screen of the active matrix liquid crystal display device 10.

Therefore, according to the present embodiment, by using the coefficient adding circuit 5 shown in FIG. 3 or FIG. 5, a correction effect of only one of the preshoot and the postshoot can be generated, and furthermore, the data output can be performed. analog switches S ₁ of use, ..., an effective on-period T _max of S _m can take up to a maximum period of three pixels.

FIG. 7 shows the coefficient adding circuit 5 in FIG.
It is a block diagram which shows another specific example of. The coefficient adding circuit 5 shown in FIG. 7 is a circuit for realizing the effect of correcting contour components (pre-shoot and post-shoot) that emphasize before and after the change of the image change signal. In FIG. 7, 17 and 19 are adders, and 18 is a coefficient unit.

FIG. 8 is a waveform diagram showing waveforms of main signals in FIG. 1 when the coefficient adding circuit 5 in FIG. 7 is used. Next, the operation will be described.

The difference between the coefficient adding circuit 5 of FIG. 7 and the configuration of FIG. 3 is that four arithmetic processing circuits 13, 14, 15, and 16 in the coefficient adding circuit 5 each output three sampling output signals. That is the input. That is, the input signals are (4A, 4B, 4C), (4
B, 4C, 4D), (4C, 4D, 4A), (4D, 4
A, 4B).

Here, taking the arithmetic processing circuit 13 in the coefficient adding circuit 5 as an example, the sampling output signals 4A and 4C are added by the adder 17, and the output signal of the adder 17 is (−) by the coefficient unit 18. 1 / K) times, then adder 1
9 and the sampling output signal 4B is added to obtain an output signal 5A. Similarly, the arithmetic processing circuits 14, 15, 16
, Output signals 5B, 5C and 5D are obtained, respectively.

Thereafter, the output signal 5 formed by the arithmetic processing circuits 13, 14, 15, and 16 in the coefficient adding circuit 5
A, 5B, 5C and 5D are connected to the data lines L ₁ and L ₂ by turning on the analog switch S ₁ only during the “H” period of the sequential selection pulses 1U, 2U, 3U and 4U from the shift register 8. , L ₃ , L ₄ and the data lines L ₁ ,
L _2, to drive the L _3, L _4.

By repeating the above operation, the output signal 5A is output to the data lines L ₁ , L ₅ , L ₉ ,..., And the output signal 5B is output to the data lines L ₂ , L ₆ , L ₁₀ ,. 5C data lines _{L 3, L 7, L 11} , ... , the output signal 5D is a data line _{L 4, L 8, L 12} , ..., the L _m, are supplied to drive the respective data lines.

Here, paying attention to the output signal 5C, the voltage drops during a specific period, and a preshoot voltage waveform that emphasizes immediately before the change of the image change signal is generated. Focusing on the output signal 5D, the voltage increases during a specific period,
A post-shoot voltage waveform is generated which emphasizes immediately after the change of the image change signal. However, since the pre-shoot and the post-shoot are held only for a period of two pixels as shown in FIG. 8, the analog switches S _{1 ,.}
The on-period T _max would be reduced from four periods of pixels in the period of two pixels.

As described above, according to this embodiment, when the coefficient adding circuit 5 shown in FIG. 7 is used, the sample output signals 4A to 4D from the four sample and hold circuits 3A to 3D are used.
Is used effectively, the pre-shoot and post-shoot correction effects shown in the output signals 5C and 5D can be generated on the screen of the active matrix liquid crystal display device 10.

[0044] Therefore, according to this embodiment, by using the coefficient addition circuit 5 shown in FIG. 7, the analog switches S ₁ for data output, ..., effective on-period T _max of S _m is the maximum 2 pixels However, from the viewpoint of aperture compensation, both the pre-shoot and post-shoot correction effects can be generated on the screen, and the horizontal driver HD As long as the operation speed is secured, an image with sharper image quality can be obtained.

Next, FIG. 9 is a circuit diagram showing a data-side drive circuit according to a second embodiment of the present invention. In this embodiment, it is possible to generate preshoot, the correction effect of both posts chute on the screen, further, the analog switch S ₁ for data output, ..., effective on-period of the S _m T
_max can be extended to a maximum of four pixels.

The present embodiment differs from the embodiment shown in FIG. 1 in that another presampling circuit 51 is added between the coefficient adding circuit 5 and the horizontal driver HD. Note that the coefficient adding circuit 5 uses the coefficient adding circuit 5 shown in FIG.

In FIG. 9, reference numeral 51 denotes a presampling circuit, which includes analog switches E to H and a hold capacitor Ce.
.. Ch and buffer amplifiers 1E to 1H, and a four-phase clock generation circuit 20 for controlling the opening and closing of the analog switches E to H.

FIG. 10 is a waveform diagram showing the waveform of the main signal of FIG. Next, the operation will be described. In response to the timing of the clocks 2E to 2H from the four-phase clock generation circuit 20, output signals 4A to 4
Assume that the timing of D is as shown in FIG. The waveforms of the output signals 5A to 5D output from the arithmetic processing circuits 13 to 16 in the coefficient adding circuit 5 are the same as those in FIG. 8, as shown in FIG.

Here, paying attention to the output signal 5C, FIG.
From the time t ₁ shown in 0 in a period of "H" of t ₂ clocks 2G, analog sample-and-hold circuit 6C switch G
By but turned on, the sampled preshoot component P3, after being held in the hold capacitor Cg, via a buffer amplifier 1G, horizontal as the sampling output signals 7C holding for a period of t ₃ that level from time t ₁ Output to the driver HD.

Similarly, for the other output signals 5A, 5B, 5D, during the "H" period of the clocks 2E, 2F, 2H,
When the analog switches E, F, and H in the sample and hold circuits 6A, 6B, and 6D are turned on, the respective signal components P1, P2, and P4 are sampled and held in the hold capacitors Ce, Cf, and Ch. Via the amplifiers 1E, 1F, and 1H, the signals are output to the horizontal driver HD as sampling output signals 7A, 7B, and 7D that hold the respective levels.

Thereafter, each of the sampling output signals 7A to 7D input to the horizontal driver HD is converted into an analog switch S
_1, ..., only the sequential period of "H" of the selection pulse 1U~4U from the shift register 8 for controlling the opening and closing of S _m, the analog switches S _1, S _2, S _3, by S ₄ is turned on,
The data lines L ₁ , L ₂ , L ₃ , L ₄ are led to the data lines L ₁ ,
L _2, to drive the L _3, L _4.

According to the present embodiment, by adding another pre-sampling circuit 51 between the coefficient adding circuit 5 and the horizontal driver HD, the effect of correcting both the pre-shoot and post-shoot is displayed on the screen. And an analog switch S ₁ for data output,
... can take effective ON period T _max of S _m up to four pixels.

Next, FIG. 11 is a circuit diagram showing a data-side drive circuit according to a third embodiment of the present invention. In FIG. 11, reference numeral 52 denotes a pre-sampling circuit, which includes four sample-hold circuits 3A including analog switches A to D, hold capacitors Ca to Cd, and buffer amplifiers 1A to 1D.
3D and a four-phase clock generation circuit 2 for controlling the analog switches A to D, and adders 21 to 24
And coefficient units 25 to 28.

In this embodiment, as in the embodiment shown in FIG. 9, both the pre-shoot and post-shoot correction effects can be generated on the screen, and the data output analog switches S ₁ , ..., it is possible to extend the effective on-time period T _max of S _m to a maximum of 4 pixels.

This embodiment is different from the embodiment shown in FIG. 9 in that instead of adding another pre-sampling circuit 51 between the coefficient adding circuit 5 and the horizontal driver HD, the coefficient adding circuit 5 The configuration is such that adders 21 to 24 and coefficient units 25 to 28 are further provided in the configuration of the sampling circuit 50 at the preceding stage to form a sampling circuit 52. Note that the coefficient adding circuit 5 uses the coefficient adding circuit 5 shown in FIG.

The coefficient unit 25 in the presampling circuit 52
28 to 28 output the signals sampled by the analog switches A to D in the sample and hold circuit at the preceding stage, multiplied by a coefficient. Further, the adders 21 to 24
The video signal from the input terminal 1 and the coefficient units 25 to
The signal multiplied by a coefficient from 28 is added. Its adder 2
The added output signals from 1 to 24 are input to analog switches A to D in sample and hold circuits 3A to 3D and are sampled.

According to this configuration, unlike the embodiment shown in FIG. 9, both the preshoot and the postshoot can be performed without providing another presampling circuit between the coefficient adding circuit 5 and the horizontal driver HD. the correction effect can be generated on the screen, further, the analog switch S ₁ for data output, ..., an effective on-period T _max of S _m can take up to four pixels.

FIG. 12 is a circuit diagram showing a data-side drive circuit according to a fourth embodiment of the present invention. This embodiment is an embodiment in which the data side driving circuit shown in FIG. 9 is replaced by analog processing to digital processing. That is, in FIG. 12, the four-phase clock generation circuit 2 and the latch circuit 52 correspond to the pre-sampling circuit 50, and the four-phase clock generation circuit 20 and the latch circuit 55 correspond to the pre-sampling circuit 51, respectively.

As shown in FIG. 12, a video signal digitized by the A / D converter 30 is subjected to serial / parallel conversion by a latch circuit 53 controlled by a four-phase clock generation circuit 2 and then digitally converted into a coefficient. It is supplied to a coefficient adding circuit 54 for performing addition. The output signals 5A, 5B, 5C, and 5D whose apertures have been corrected are input to a four-phase clock generation circuit 20.
The output signals are converted into analog video signals by the D / A converters 31 to 34 and input to the horizontal driver HD.

As described above, even when the video signal is digitally processed, the circuit operation and its contour correction effect can be made substantially the same as in the embodiment shown in FIG.

In each of the above embodiments, the case where four sample-and-hold circuits are used for the pre-sampling circuit has been described. However, even when the number of sample-and-hold circuits is other than four, the same effect can be obtained if three or more are used. Is clearly obtained.

A data-side drive circuit using a pre-sampling circuit mainly using a polarity-reversed video signal for reducing the driving frequency of the horizontal driver and preventing flicker, and a vertical lead-out of data lines, etc. By providing the coefficient adding circuit, an aperture correction function can be similarly added.

[0063]

As described above, according to the present invention,
By using a sampling output signal obtained by serial-to-parallel conversion of a video signal as an input signal of the coefficient addition circuit, a function of reducing the driving frequency of the horizontal driver and an aperture compensation function can be realized. Moreover, since it is not necessary to separately provide an aperture compensation circuit, the circuit scale does not increase. Further, the effective ON period of the analog switch for data output can be varied by the combination of the configuration of the coefficient addition circuit and the input signal thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a data side driving circuit as a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of one pixel portion of the active matrix liquid crystal display device 10 in FIG.

FIG. 3 is a block diagram showing a specific example of a coefficient adding circuit 5 in FIG.

FIG. 4 is a waveform chart showing waveforms of main signals of FIG. 1 when the coefficient adding circuit 5 of FIG. 3 is used.

FIG. 5 is a block diagram showing another specific example of the coefficient adding circuit 5 in FIG. 1;

FIG. 6 is a waveform chart showing waveforms of main signals of FIG. 1 when the coefficient adding circuit 5 of FIG. 5 is used.

FIG. 7 is a block diagram showing another specific example of the coefficient adding circuit 5 in FIG. 1;

8 is a waveform diagram showing waveforms of main signals of FIG. 1 when the coefficient adding circuit 5 of FIG. 7 is used.

FIG. 9 is a circuit diagram showing a data-side drive circuit as a second embodiment of the present invention.

FIG. 10 is a waveform chart showing waveforms of main signals of FIG. 9;

FIG. 11 is a circuit diagram showing a data side driving circuit as a third embodiment of the present invention.

FIG. 12 is a circuit diagram showing a data side drive circuit as a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a conventional data-side drive circuit.

FIG. 14 is a waveform chart showing waveforms of main signals of FIG. 13;

FIG. 15 is a block diagram showing a conventional aperture compensation circuit.

FIG. 16 is a waveform chart showing waveforms of main signals of FIG. 15;

[Explanation of symbols]

1 input terminal, 2, 20 4-phase clock generation circuit, 3A
~ 3D, 6A ~ 6D ... Sample hold circuit, Ca ~ C
h: hold capacity, 5, 54: coefficient addition circuit, 8: shift register, 10: active matrix liquid crystal display device, 12, 18, 25 to 28: coefficient unit, 11, 17, 1
9,21～24 ... adder, A to H, S _1, ..., S _m ... analog switches, HD ... horizontal driver, 30 ... A / D converter, 31 to 34 ... D / A converter, 50-52 ... presampling circuits, 53 and 55 ... latch circuits.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Toshihiko Kudo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Media Research Laboratory, Hitachi, Ltd. (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/66

Claims (4)

(57) [Claims] 1. A pre-sampling circuit having a plurality of sample-and-hold circuits for sequentially sampling input video signals, holding and outputting the video signals for a predetermined period, and outputting from each of the sample-and-hold circuits in the pre-sampling circuit. A coefficient adding circuit including a plurality of arithmetic processing circuits for inputting at least two or more output signals, multiplying by a predetermined coefficient, adding signals together, and outputting the signals; An output signal output from the processing circuit is sequentially supplied to each data line of the matrix type display device, and is configured by a horizontal driver that drives each data line, and the driving frequency of the horizontal driver can be reduced. A data side drive circuit capable of performing aperture compensation. 2. A first pre-sampling circuit including a plurality of sample-and-hold circuits for sequentially sampling input video signals, holding and outputting the video signals for a predetermined period, and each of the first pre-sampling circuits in the first pre-sampling circuit. A coefficient adding circuit having a plurality of arithmetic processing circuits for inputting at least two or more output signals output from the sample and hold circuit, multiplying the signals by a predetermined coefficient, and adding and outputting the signals; A second pre-sampling circuit including a plurality of sample-and-hold circuits for sequentially sampling output signals output from the respective arithmetic processing circuits in the adder circuit and holding and outputting the output signals for a predetermined period; The output signals output from each sample-and-hold circuit in the pre-sampling circuit are expressed in matrix form. A horizontal driver that sequentially supplies each data line of the display device and drives each data line, wherein the driving frequency of the horizontal driver can be reduced and aperture compensation can be performed. Drive circuit. 3. A plurality of arithmetic processing circuits each receiving a video signal and inputting at least one first output signal, multiplying a predetermined coefficient, and adding and outputting the signals. Each of the arithmetic processing circuits has a one-to-one correspondence, the output signals output from the corresponding arithmetic processing circuits are sequentially sampled and output as the first output signal, and the output signals are held for a predetermined period and the second output signals are held. A pre-sampling circuit having a plurality of sample-and-hold circuits for outputting as output signals, and at least two or more of the second output signals output from each of the sample-and-hold circuits in the pre-sampling circuit, and A coefficient adding circuit having a plurality of arithmetic processing circuits for multiplying coefficients and adding and outputting signals; And a horizontal driver for sequentially supplying output signals output from the respective arithmetic processing circuits in the circuit to the respective data lines of the matrix type display device and driving the respective data lines. A data-side drive circuit, which can reduce aperture and can perform aperture compensation. 4. An analog / digital converter for converting an input analog video signal into a digital video signal and outputting the video signal, and sequentially latching and outputting the video signal output from the analog / digital converter. A first latch circuit having a plurality of latch means, and at least two or more output signals output from each of the latch means in the first latch circuit, respectively, multiplying by a predetermined coefficient, and And a plurality of latch means for sequentially latching and outputting output signals output from the respective arithmetic processing circuits in the coefficient adding circuit. And a digital signal output from each latch means of the second latch circuit. A plurality of digital / analog converters for converting and outputting analog signals, and output signals output from the respective digital / analog converters are sequentially supplied to respective data lines of a matrix type display device, and each data is output. A horizontal driver for driving a line, wherein the driving frequency of the horizontal driver can be reduced and aperture compensation can be performed.