JP3104099B2 - Digital / analog conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog conversion circuit called a 1-bit digital / analog converter, and more particularly, to a digital / analog converter to which a mute circuit for muting an analog converted analog audio signal is added. It relates to an analog conversion circuit.

[0002]

2. Description of the Related Art Conventionally, a 1-bit digital / analog conversion circuit has been put to practical use as a digital / analog conversion circuit for converting a digital audio signal into an analog audio signal. This 1-bit digital / analog conversion circuit obtains a 1-bit series pulse signal whose number or width changes as a converted output.
An output in which the number or width of the pulse signal changes is supplied to a low-pass filter and averaged to obtain an analog audio signal. In this case, the pulse waveform output by the digital / analog conversion circuit has either a high level or a low level, and the pulse waveform that changes in number according to the input digital data is pulse number modulation ( PNM), and those in which the width of the pulse waveform changes are called pulse width modulation (PWM). According to the digital / analog conversion circuit of such a system, the distortion generated at the time of conversion can be minimized, and it can be converted into a good analog audio signal without distortion.

The actual configuration of this type of 1-bit type digital / analog conversion circuit will be described with reference to FIG. 5. In FIG. 1, reference numeral 1 denotes a digital signal supplied with digital audio data reproduced from a compact disk (CD). An audio data input terminal is provided, and digital audio data having a predetermined number of bits (for example, 16 bits per sample) obtained at the input terminal 1 is supplied to a digital filter 2. The digital filter 2 performs oversampling of the supplied digital audio data to increase the sampling frequency to an integral multiple. Then, the digital audio data oversampled by the digital filter 2 is supplied to the noise shaper 3 to perform a process of compressing the number of bits per sample. For example, a process of compressing 16 bits into 4 bits by the noise shaper 3 is performed, and the quantization step is 0, ± 0.25, ± 4 bits as 4-bit data bit-compressed by the noise shaper 3.
Nine values of 0.5, ± 0.75, ± 1.0 are used.

[0004] The bit-compressed digital audio data is supplied to the pulse converter 4 and is converted into one bit (2 bits).
Value) pulse data. By this conversion, pulse number modulation in which the number of pulse waveforms changes or pulse width modulation in which the width of the pulse waveform changes is performed, and the converted pulse data is supplied to an analog filter (low-pass filter) 5. Smoothing is performed to obtain an analog audio signal in which a change in audio level and a change in signal waveform match.

Here, depending on the configuration of the digital / analog conversion circuit, an analog mute circuit for muting the converted analog audio signal at a predetermined time may be connected to the subsequent stage of the analog filter. That is, in the example of FIG. 5, an analog mute circuit 6 is connected to the subsequent stage of the analog filter 5 for smoothing the output pulse, and the output of the analog mute circuit 6 is used as an analog audio signal from the output terminal 7 to the analog audio reproduction circuit. (Not shown). Here, the analog mute circuit 6
When the mute operation is controlled by a mute control signal supplied from the outside via the terminal 8 and the output audio signal is to be muted (ie, silence),
A mute operation (that is, an operation of setting the output level to 0 V level) is performed, and another state (that is, a state in which the mute is not performed) is performed.
Then, the analog audio signal supplied from the analog filter 5 is output as it is.

When a mute operation is performed by the analog mute circuit 6, the mute control signal obtained at the terminal 8 is also supplied to the other circuits constituting the digital / analog conversion circuit, so that the pulse conversion unit 4 50%
May be output. The pulse having the duty of 50% becomes 0 V level by the smoothing in the analog filter 5, the mute operation is also performed by the digital data processing, and the mute operation in the analog mute circuit 6 is performed, so that the reliable mute is performed. To be done.

Since such an analog mute circuit is connected to the digital / analog conversion circuit, a mute operation for temporarily forcibly setting the output audio signal to a silent state can be easily performed.

[0008]

When a mute operation is performed by such a circuit, a mute operation by digital processing in a pulse converter or the like and a mute operation by an analog mute circuit are performed by the same mute control signal. In this case, the timing at which the mute operation is performed is shifted, and there is a problem that a click sound is temporarily generated as noise at the start of the mute operation.

That is, FIG. 6 shows the timing when the mute operation is performed in this type of circuit. The mute operation is performed when the reset signal shown in FIG. 6A changes from a high level to a low level. At this changing timing t1, the mute operation by the digital processing is immediately performed, and the output pulse of the pulse conversion unit is switched to a pulse having a duty of 50% as shown in FIG. 6C. On the other hand, the mute operation by analog processing in the analog mute circuit 6 starts to operate at a timing t2 delayed from the timing t1 as shown in B of FIG. 6 (the high-level period of B in FIG. 6 is during the mute operation). . This delay in timing is due to poor response of a switch element such as a transistor included in the analog mute circuit 6. In addition,
Here, the reset signal is a mute control signal.

As described above, the timing t1 at which the pulse with the duty of 50% starts to be output and the analog mute circuit 6
Is different from the timing t2 at which the analog output is muted, a click sound is output to the analog output as noise until the analog output is completely muted (that is, between timings t1 and t2). There was a possibility. The click noise is generated as a transient response when the output is instantaneously switched to a pulse having a duty of 50% in the pulse converter.

In view of the above, an object of the present invention is to provide a 1-bit digital / analog conversion circuit that does not output noise such as a click sound during a mute operation.

[0012]

According to the present invention, as shown in FIG. 1, for example, digital audio data is oversampled by a digital filter 2, the oversampled data is bit-compressed by a noise shaper 3, and The compressed data is converted into 1-bit data in which the number or width of output pulses changes by a pulse conversion unit 4, and the converted 1-bit data is smoothed by an analog filter 5 to obtain analog data. In a digital / analog conversion circuit for muting and outputting at a predetermined time by a mute circuit 6, a first mute control signal and a second mute control signal whose timing is delayed from the first mute control signal in response to the response time of the analog mute circuit 6 And a first mute control signal. The chute control signal is supplied to the analog muting circuit 6, in which so as to provide a second mute control signal at least to the pulse converter 4.

[0013]

With this arrangement, when the mute operation is performed, the first mute control signal is first supplied to the analog mute circuit, and the analog mute circuit is delayed based on the first mute control signal. Almost simultaneously with the muting operation, the second muting control signal is supplied to the pulse converter and the like, and the muting operation is performed digitally, and the analog muting operation and the digital muting operation are performed. Are performed almost simultaneously, and noise such as a click sound is not output.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In FIGS. 1 to 4, parts corresponding to FIGS. 5 and 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the present invention is applied to the above-described 1-bit digital / analog conversion circuit, and is configured as shown in FIG. That is, in this example, the input terminal 8
Is supplied to the analog mute circuit 6 as it is, and the reset signal obtained at the input terminal 8 is delayed by a count operation by the count circuit 10 to thereby provide the digital filter 2, the noise shaper 3, and the pulse converter. And 4. Here, the counting circuit 1
The delay time at 0 is slightly longer than the time from when the reset signal is supplied to the analog mute circuit 6 until the mute operation is actually performed. The reset signal obtained at the input terminal 8 is output from a central control unit (not shown) of the audio device when the output signal of the audio device incorporating the digital / analog conversion circuit is to be muted. Signal.

Here, the configuration of the count circuit 10 is shown in FIG. 2. When a reset signal obtained at a terminal 8 is supplied to a D input terminal of a D flip-flop 12, a reset signal is supplied to a terminal 1
1 is a signal synchronized with the system clock of this audio device. Then, the D flip-flop 12
Is supplied to the D input terminal of the D flip-flop 13 and the falling detection circuit 14. In the fall detection circuit 14, a signal obtained by inverting the reset signal obtained at the terminal 8 by the inverter gate 15 and the Q output of the D flip-flop 12 are supplied to the NAND gate 16, and the logical operation at the NAND gate 16 is performed. To detect the fall. Then, the output of the NAND gate 16 is supplied to the reset signal input R of the counter 17 as the output of the falling detection circuit 14. This counter 17 has a terminal 1
The process of dividing the system clock from 1 is performed,
The frequency division operation is started by the falling detection signal obtained at the reset signal input R, and the frequency-divided clock Qn is obtained. Then, the divided clock Qn is supplied to the clock input terminal CLK of the D flip-flop 13.

The D input terminal of the D flip-flop 13 is supplied with the Q output of the D flip-flop 12 (reset signal synchronized with the clock). The reset signal is output as a signal that rises at a timing synchronized with the frequency-divided clock Qn. Then, the Q output of the D flip-flop 13 is supplied to one input terminal of the OR gate 18, and the reset signal obtained at the terminal 8 is supplied to the other input terminal of the OR gate 18. The output is supplied to an output terminal 19.

The operation of the count circuit 10 thus configured will be described with reference to FIG. 4. For example, it is assumed that a reset signal shown at A in FIG. It is assumed that the reset signal changes from a high level to a low level at an arbitrary timing, and an instruction to mute is issued. At this time, the reset signal is synchronized with the system clock (C in FIG. 4) by the D flip-flop 12, and becomes a signal shown in B in FIG. And
The fall detection circuit 14 performs a logical operation on the input reset signal and the clock synchronous reset signal, and obtains D in FIG.
Is obtained. This By falling detection signal is supplied to the reset signal input R of the counter 17, the output of the frequency-divided clock obtained by frequency-dividing the system clock (E in FIG. 4) is started, first the divided clock
When the period elapses, a process of changing the reset signal is performed by the D flip-flop 13, and the logical sum of the reset signal (F in FIG. 4) and the input reset signal is obtained, whereby the output shown in G in FIG. A reset signal is obtained.

Accordingly, the output reset signal shown in FIG. 4G has a signal whose delay is delayed by a predetermined time ta compared to the input reset signal shown in FIG. 4A. In addition,
Since the output reset signal is ORed with the input reset signal by the OR gate 18, the rise of the reset signal obtained at the terminal 8 is added to the output reset signal at the same timing.

In this embodiment, the input reset signal obtained at the terminal 8 is directly used as the analog mute circuit 6
And a reset signal whose falling timing is delayed by the count circuit 10 is supplied to the digital filter 2, the noise shaper 3, and the pulse converter 4 as a second reset signal.

The other parts are configured in the same manner as the conventional one-bit digital / analog conversion circuit shown in FIG.

Next, a description will be given of the operation of the digital / analog conversion circuit of this embodiment at the time of mute. When a mute operation is performed by supplying a reset signal as a mute control signal, as shown in FIG. A reset signal that changes from a high level to a low level is supplied to the terminal 8.
At this time, this reset signal is supplied as it is to the analog mute circuit 6 as a first reset signal, and since the response of the transistors constituting the analog mute circuit 6 is slow, the analog mute circuit 6 is delayed by a predetermined time tb. Perform mute operation. Here, C in FIG.
The operation state of the analog mute circuit 6 is shown, and the high level period indicates a period during which the mute operation is performed.

The reset signal obtained at the terminal 8 is a second reset signal whose timing of falling by the count circuit 10 is delayed by ta as shown in FIG. 3B. Then, at the timing when the second reset signal falls, the normal pulse conversion operation (the pulse conversion operation corresponding to the input digital audio data) in the pulse conversion unit 4 is stopped, and the pulse having the duty of 50% is continuously output. (See D in FIG. 3).

Here, in this example, the time ta at which this timing is delayed is longer than the response time tb of the analog mute circuit 6, so that the pulse conversion is performed after the analog mute circuit 6 is completely operated. A pulse having a duty of 50% is output from the section 4, and click noise generated when the output of the pulse conversion section 4 is switched to a pulse having a duty of 50% is muted by the mute operation of the analog mute circuit 6. The click noise is not output to the analog audio signal output terminal 7. Therefore, when the muting control is performed, no click noise is output at the start of the muting, and a good muting operation is performed.

In this case, in this embodiment, the counting circuit 1
Since the reset signal (second reset signal) to be supplied to the digital processing unit such as the pulse conversion unit 4 is generated by the count operation using 0, the integrated circuit configuring the digital processing unit such as the pulse conversion unit 4 can be used. Count circuit 10
Can be integrated, and the configuration can be simplified as compared with a case where a delay circuit is assembled by circuit components such as a resistor and a capacitor. Therefore, the device can be configured at low cost, and the mounting area of the circuit components on the circuit board can be reduced.

In the processing of the reset signal by the counting circuit 10 of the present embodiment, when the reset signal rises (ie, when the mute state is released), the reset signal is not delayed. The release of the mute state in the digital processing unit is immediately performed based on the reset signal obtained at the terminal 8, and the analog audio signal is output from the output terminal 7 at the same time when the mute operation in the analog mute circuit 6 is released. As a result, there is no delay in releasing the mute operation.

In the above embodiment, the reset signal delayed by the count operation of the count circuit is also supplied to the digital filter and the noise shaper so that these circuits are reset.
If at least the reset signal is supplied from the count circuit to the pulse conversion unit, the operation at least necessary for the mute operation is performed.

The count circuit for generating the delayed reset signal (mute control signal) is an example in the above-described embodiment, and may have another circuit configuration.

[0029]

According to the present invention, when a mute operation is performed, an analog muting operation and a digital muting operation are performed almost simultaneously, and a smooth mute without noise such as a click sound. Switching to the state is performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram showing a main part of one embodiment.

FIG. 3 is a timing chart for explaining one embodiment.

FIG. 4 is a timing chart for explaining one embodiment;

FIG. 5 is a configuration diagram illustrating a conventional 1-bit digital / analog conversion circuit.

FIG. 6 is a timing chart for explaining the example of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 digital audio data input terminal 2 digital filter 3 noise shaper 4 pulse converter 5 analog filter 6 analog mute circuit 7 analog audio signal output terminal 10 count circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-119920 (JP, A) JP-A-62-277814 (JP, A) JP-A-63-191418 (JP, A) JP-A-2- 20928 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 3/02

Claims (5)

(57) [Claims] 1. A pulse signal conversion means for converting a digital audio signal into a 1-bit pulse signal, and the 1-bit pulse signal supplied from the pulse signal conversion means is smoothed and output as an analog audio signal. A mute means for muting the analog audio signal supplied from the smoothing means after a required response time in response to a mute control signal supplied from outside; A digital / analog conversion circuit comprising: control signal delay means for delaying a mute control signal in accordance with the required response time and supplying the delayed signal to the pulse signal conversion means as a delayed mute control signal. 2. The control signal delay means delays the externally supplied mute control signal for a time longer than the required response time and supplies the delayed mute control signal to the pulse signal conversion means as a delayed mute control signal. The digital / analog conversion circuit according to claim 1, wherein 3. The pulse signal converting means converts the digital audio signal from a 1-bit pulse signal converted to a voltage of zero volts after smoothing by the smoothing means in accordance with the delay mute control signal. 2. The digital / analog conversion circuit according to claim 1, wherein the digital / analog conversion circuit outputs the pulse signal by switching to a bit pulse signal. 4. A signal which is outputted from said pulse signal converting means and which becomes zero volt after smoothing by said smoothing means.
4. The digital / analog conversion circuit according to claim 3, wherein the pulse signal of the bit system has a duty of 50%. 5. An oversampling unit for oversampling an input digital audio signal, and a bit to be supplied to the pulse signal conversion unit after compressing the number of bits of the oversampled digital audio signal from the oversampling unit. 2. The digital / analog conversion circuit according to claim 1, further comprising a number compression unit, wherein the delay mute control signal is supplied to the oversampling unit and the bit number compression unit.