JP3099564B2 - Data compression / decompression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression / expansion apparatus used for compression processing of image data, and more particularly to a data compression / expansion apparatus capable of performing data compression with a small circuit scale.

[0002]

2. Description of the Related Art A DCT (Discrete Cos
ine Transform (Discrete Cosine Transform) is becoming the mainstream of high efficiency coding technology. If the average number of bits per pixel is reduced by performing high-efficiency encoding without being limited to the DCT, the quality of the image is reduced, and if the compression ratio is increased, the image quality is deteriorated. For example, if the current standard television signal is 1.5 Mbit /
Problems that occur when compression is performed in seconds are deterioration of contour portions and block distortion generated in units of blocks (for example, 8 × 8 pixels) processed by DCT. When a pixel is reproduced by performing an inverse transformation, all the DCT outputs in the block are linearly summed. However, if any one of 64 DCT outputs of a block including 8 × 8 pixels has information loss, Degradation occurs in the reproduced pixels in the entire block.

[0003] Here, the DCT transform is one of orthogonal transforms, and is called a transform method having the highest energy concentration along with the Karnen-Loeve transform.

Now, a signal f (j) (j = 0, 1,...,
N-1) Result F (u) by one-dimensional DCT transform
(U = 0, 1,..., N−1) is defined by Expression 1.

[0005]

(Equation 1) The inverse DCT transform is defined by Expression 2.

[0006]

(Equation 2) By performing such DCT transformation on an image,
Since energy concentration can be obtained, it is possible to encode only a component having a large amount of energy, thereby compressing image data.

By the way, not only the data compression / expansion apparatus having the DCT but also a normal data compression / expansion apparatus performs data conversion (FFT, DCT, etc.) on a numerical sequence,
After that, quantization is performed.

FIG. 11 is a block diagram of a conventional data compression / decompression device. A data storage device 10 stores two-dimensional data to be compressed in the form of parallel data. Data storage device 10
(For example, image data) stored in the parallel-to-serial conversion device 11, which converts the parallel data read from the data storage device 10 into serial data to convert the data into a serial data. 12 is output. The data conversion operation device 12 performs a one-dimensional DCT operation on the data output from the parallel-serial conversion device 11 in the form of a serial operation. The data subjected to the serial DCT operation is output to the serial-to-parallel converter 13, which converts the serial data output from the data converter 12 into parallel data and writes it to the data storage device 10. The above example is a one-dimensional case, and in the case of a two-dimensional image or the like, the above-described processing is performed in the vertical and horizontal (in any order) two-dimensional as shown in FIG. Also, the quantization device 14
Performs a quantization operation by dividing (or multiplying by a reciprocal number) the data after the data conversion operation stored in the data storage device 10 by, for example, a value of a quantization table as shown in FIG. . The operation of each unit is controlled by a control device 15 that controls the entire data compression / decompression device.

The serial DCT operation executed by the data conversion operation device 12 is performed by the serial operation described below.

First, as a basic idea, the value of the COS coefficient is raised to a power of 2 (that is, 2 to the power of n) as shown in Expression 3.
The sum or difference of The reason for expressing the numerical value by a power of 2 as shown in Equation 3 is to realize an operation by a serial circuit. That is, in FIG. 14, reference numeral 21 represents a one-time delay unit composed of an FF (flip-flop) that responds to a clock input signal and outputs the input signal one clock delayed, and the one time delay unit 21 is Comparing the output coming through and the output coming directly without passing through one time delay unit 21, the former is one clock later than the latter. Here, the one time delay unit 21 has a structure in which shift registers are arranged side by side. For example, if data is sequentially input from the LSB side, the fact that one clock delay comes out is doubled. means. Similarly,
When to be eight times is 8 times 2 ³ If to delay three side by side three clocks, as shown in FIG. 15 the one time delay unit 21. In this embodiment, a serial operation circuit is realized by performing addition and subtraction by combining the above units.

FIG. 16 shows a serial operation configuration of the multiplication unit. FIG. 16 shows an example in which input data is multiplied by 38. First, 38 is decomposed into the form of Equation 4.

In Expression 4, to multiply a certain numerical value x by 32 means to shift x five times to the left (in the MBS direction). In FIG. It is realized by. Also,
Since 2 × (2 + 1) shown in Expression 4 is actually 6, it may be expressed as 4 + 2. However, since the full adder 22 in FIG. 16 has one time delay unit and doubles the input data, an expression form of 2 × (2 + 1) can be adopted. The output of the unit itself in FIG.
It is 6 times, but 38 times is realized by delaying the fetch timing of the next stage by one clock.

The data compression / expansion apparatus will be described below with reference to the drawings.

FIG. 17 is a diagram showing a circuit configuration of the data conversion operation device 12 for executing the serial DCT operation, and is composed of stages I to IV.

In FIG. 17, reference numeral 31 denotes a stage I operation circuit, 32 denotes a stage II operation circuit, and 33 denotes a stage II operation circuit.
The I operation circuit 34 is a stage IV operation circuit. The operation circuits 31 to 34 of these stages I to IV are configured to be connected in series via switches 35 to 39, respectively. In this case, in the DCT operation processing, the operation circuits 31 to 34 are connected in series in the order shown in FIG. It is connected directly. Then, the result of the DCT or inverse DCT operation on the input data supplied to the input terminal 40 is output from the output terminal 41. In this case, the input data consists of eight serial lines.

FIG. 18 is a diagram showing a circuit configuration of the operation circuit 31 of the stage I. The arithmetic circuit 31 executes the above-described serial arithmetic operation, and includes
c, 1d and subtracters 1e, 1f, 1g, 1h.

FIG. 19 is a diagram showing a circuit configuration of the operation circuit 32 of the stage II. The arithmetic circuit 32 executes the above-described serial operation, and includes shifters 2a to 2f and CO
It is composed of COS (4/16) π calculators 2g and 2h for performing S (4/16) π calculation (see Equation 1). Here, the shifter 2
Reference numerals a to 2f denote serially connected ten flip-flops, which are configured to output input data with a predetermined delay. Also, the above COS (4/16)
The π computing unit 2g calculates the approximate expression 1 in the case of N = 4 of COS (N / 16) π
81 = (16-1) × (2 + 1) × 4 + 1
An adder 2g1, a shifter 2g2 composed of four flip-flops for shifting the output of the adder 2g1, a subtractor 2g3 for subtracting the output from the adder 2g1 from the output of the shifter 2g2, and shifting the output of the subtracter 2g3 A shifter 2g4 composed of one flip-flop, and this shifter 2g4
Adder 2g for adding the output of the above-described subtractor 2g3
5. An adder 2g6 for adding the output of the adder 2g5 and the output of the adder 2g1. Also, the above C
The OS (4/16) π calculator 2h also realizes the calculation of the approximate expression 181 = (16-1) × (2 + 1) × 4 + 1 when N = 4 of COS (N / 16) π A shifter 2h2 composed of four flip-flops for shifting the output of the subtractor 2h1, a subtractor 2h3 for subtracting the output of the subtractor 2h1 from the output of the shifter 2h2, and an output of the subtractor 2h3. Shifter 2h4 composed of one flip-flop for shifting
adder 2h for adding the output of h4 and the output of subtractor 2h3
5, an adder 2h6 for adding the output of the adder 2h5 and the output of the subtractor 2h1.

FIG. 20 is a diagram showing a circuit configuration of the arithmetic circuit 33 of the stage III. The arithmetic circuit 33 executes the above-described serial operation, and includes adders 3a and 3b, subtractors 3c and 3d, and adders 3e and 3f, and a subtractor 3g.
3h.

FIG. 21 is a diagram showing a circuit configuration of the arithmetic circuit 34 of the stage IV. The arithmetic circuit 34 executes the above-described serial arithmetic operation, and performs COS coefficient arithmetic operations.
OS (4/16) π arithmetic units 4a, 4b, COS (2/16) π and COS (6
/ 16) π calculators 4c, 4d, COS (1/16) π and COS (7/16)
π calculators 4e and 4f, COS (3/16) π and COS (5/16) π calculators 4g and 4h. In this case, the above CO
The S (4/16) π arithmetic units 4a and 4b are the same as the COS (4/16) π arithmetic units 2g and 2h of the stage II arithmetic circuit 32 described above. The description is omitted by attaching the reference numerals.

The above COS (2/16) π and COS (6/16) π
The arithmetic unit 4c calculates the approximate expression 23 in the case of N = 2 of COS (N / 16) π.
6.5 = 4 × (64-4-1) +1/2 and 98 = 2 × (32 + 1 when N = 6)
6 + 1), and among them, the COS (2/16) π operation is realized by a shifter 4c1 comprising seven flip-flops, and a third shifter 4c1 output from the shifter 4c1. Subtractor 4 for subtracting the output of the flip-flop of
c2, a subtractor 4c3 for subtracting the output of the second flip-flop of the shifter 4c1 from the output of the subtractor 4c2, and an adder 4 for adding the output of the subtractor 4c3 and the output of the adder 3a.
An adder 4c5 for adding the output of the sixth flip-flop of the shifter 4c1 and the output of the fifth flip-flop of the shifter 4c1, Output of adder 4c5 and shifter 4c
It comprises an adder 4c6 for adding the output of the first second flip-flop. On the other hand, the above COS (2/16) π and
The COS (6/16) π operation unit 4d is the same as the operation circuit 4c described above, and the description is omitted here by attaching the same reference numerals instead of the subscript c to d. The outputs of the adders 4c4 and 4d6 are added by an adder 4c7.
The output of the adder 4d4 is subtracted from the output of 6 by the subtractor 4d7.

On the other hand, COS (1/16) π and COS (7/16) π
The arithmetic unit 4e calculates the approximate expression 251 in the case of N = 1 for COS (N / 16) π.
= (128-2) × 2-1 and 50 = 2 × (16 + 8 + 1) when N = 7, of which COS (1/16) π is realized These are a shifter 4e1 composed of seven flip-flops, a subtractor 4e2 for subtracting the output of the first flip-flop of the shifter from the output of the shifter 4e1, and an adder of the operation circuit 33 of the stage III from the output of the subtractor 4e2. 3
e = subtractor 4e3, and COS (7/16) π
The third and fourth shifters 4e1 realize the operation.
Adder 4e for adding the output of the flip-flop
4, an adder 4e5 for adding the output of the adder 4e4 and the output of the first flip-flop of the shifter 4e1. In addition, COS (1/16) π and COS (7/16) π arithmetic unit 4
f is the same as that of the arithmetic unit 4e described above, and the description is omitted here by attaching the same reference numeral instead of the subscript e.
The outputs of the subtractor 4e3 and the adder 4f5 are added to the adder 4e.
The output of the adder 4e6 is generated via the shifter 4e7. The output of the adder 4e5 is subtracted from the output of the adder 4f3.
Is subtracted by a subtractor 4f6 to generate the output via a shifter 4f7. In addition, the above COS (5/16) π and C
The OS (3/16) π calculator 4g calculates the approximate expression 142 = 2 × (64 + 8−1) when C = N = 5 of COS (N / 16) π and the approximate expression 2 when N = 3.
13 = (2 + 1) × (64 + 8-1)
The one that realizes the operation of COS (5/16) π is a shifter 4g1 composed of five flip-flops, an adder 4g2 that adds the output of the shifter 4g1 and the output of the second flip-flop of the shifter 4g1, and an adder. Stage III from 4g2 output
Subtracter 4g for subtracting the output of the subtractor 3g of the arithmetic circuit 3
3. A shifter 4g4 composed of two flip-flops for shifting the output of the subtractor 4g3, and which realizes the operation of COS (3/16) π, in addition to the above-described configuration, includes a subtractor 4g3 and a shifter 4g4. It comprises an adder 4g5 for adding the output of the first flip-flop. Also, COS (5/16) π
And COS (3/16) π arithmetic unit 4h is the above-described arithmetic unit 4g
Here, the same reference numerals are used instead of the subscript g for h, and the description is omitted. The output of the shifter 4g4 and the output of the adder 4h5 are added by the adder 4g6, and the output of the shifter 4h4 is subtracted from the output of the adder 4g5 by the subtractor 4h6.

The arithmetic circuits 31 to 34 of the stages I to IV shown in FIGS. 18 to 21 are connected as shown in FIG. 22 in the case of DCT arithmetic processing. 23 to 25 are diagrams showing each unit in FIG. 22,
FIG. 23 shows a one time delay unit 21 composed of FFs.
24 shows a one time delay unit full adder (internal carry type) 22 for performing addition (a + b), and FIG.
Indicates one time delay unit full subtractor (internal Borrow type) 23 for performing subtraction (ab).

Next, the operation of the data conversion arithmetic unit 12 configured as described above will be described.

First, the case of DCT operation processing will be described.
Here, the adder 1 is used in the arithmetic circuit 31 of the stage I.
a, input data f (0) and f (7), adder 1b input data f (3), f (4), adder 1c input data f
(1), f (6), input data f (2) to adder 1d,
f (5), input data f (0), f
(7), the input data f (3), f (4),
The input data f (1), f (6) and the subtractor 1
Input data f (2) and f (5) are input to h. As a result, the adder 1a outputs the addition result of the input data f (0) and f (7), and the adder 1b outputs the input data f (3) and f (7).
The addition result of (4) is output, and the adder 1c outputs the input data f
The addition result f (1) + f (6) of (1) and f (6) is output, and the adder 1d outputs the addition result of the input data f (2) and f (5). The subtractor 1e outputs the result of subtraction of the input data f (0) and f (7),
f outputs the subtraction result of the input data f (3) and f (4), the subtractor 1g outputs the subtraction result of the input data f (1) and f (6), and the subtractor 1h outputs the input data f ( 2) and f
The subtraction result of (5) is output. The input data in this case is composed of 8 bits of 7 bits and 1 bit of sign bit as shown in FIG. The output data is composed of 7 + 1 bits and 1 bit sign bit as shown by I in FIG. Here, the output data is 7+
The reason why the number of bits is 1 is that the result of addition by the adders 1a to 1d is considered.

Next, the operation proceeds to the operation circuit 32 of the stage II. In this arithmetic circuit 32, the arithmetic circuit 31 of stage I
The output of the adder 1a is given to the shifter 2a. Hereinafter, similarly, the output of the adder 1b is the shifter 2c, the output of the adder 1c is the shifter 2b, the output of the adder 1d is the output of the shifter 2d, and the output of the subtractor 1e. Are supplied to the shifter 2e, the output of the subtractor 1f is supplied to the shifter 2f, and the outputs of the subtractors 1g and 1h are supplied to the adder 2g1 and the subtractor 2h1, respectively. In this case, FIG.
The output data is generated from the shifters 2a to 2e with a delay of ten flip-flops as shown in FIG. That is, the shifter 2a outputs the output of the adder 1a, the shifter 2b outputs the output of the adder 1c, the shifter 2c outputs the output of the adder 1b, the shifter 2d outputs the output of the adder 1d, and the shifter 2e outputs the output of the adder 1e. To
The shifter 2f outputs the output of the adder 1f with a delay of a predetermined time.

On the other hand, the COS (4/16) π computing units 2g, 2h
Then, the approximate expression 181 = (16-1) when C = N = 4 of COS (N / 16) π
Perform the operation of × (2 + 1) × 4 + 1. In this case, the arithmetic unit 2g
, The outputs of the subtracters 1g and 1h are given as input data, and the adder 2g1 adds these input data.
Then, the output of the adder 2g1 is given to the shifter 2g2,
When the output of the adder 2g1 is subtracted by the subtractor 2g3 from the output obtained from the shifter 2g2, (16-1) is obtained.
The output of the subtracter 2g3 and the output of the shifter 2g4 are added to the adder 2g5
(16-1) × (2 + 1) is obtained by adding The output of the adder 2g5 and the output of the adder 2g1 are added by the adder 2g6 to obtain an approximate value (16-1) × (2 + 1) in the case of N = 4 of COS (N / 16) π. × 4 + 1 will be required. In this case, the input data shown in FIG.
The COS (4/16) π calculator 2g generates the above-described calculation result as output data at the timing shown in FIG.

Next, the operation proceeds to the operation circuit 33 of the stage III. The operation circuit 33 includes a stage II operation circuit 32
Output from the shifters 2a and 2c are the adder 3a and the subtractor 3
c, and similarly the outputs of shifters 2b and 2d are provided to adder 3b and subtractor 3d.
e and the output of the COS (4/16) π operation unit 2g are provided to the adder 3e and the subtractor 3g, and the outputs of the shifter 2f and the COS (4/16) π operation unit 2h are provided to the adder 3f and the subtractor 3h. . Thereby, the adder 3a outputs the result obtained by adding the outputs of the shifters 2a and 2c of the stage II operation circuit 32, and the adder 3b outputs the result of adding the outputs of the shifters 2b and 2d of the stage II operation circuit 32. And the subtractor 3c outputs the stage II
The subtracter 3d outputs the result obtained by subtracting the output of the shifter 2d from the output of the shifter 2b of the operation circuit 32 of the stage II. become. Adder 3
e is a shifter 2e of the operation circuit 2 of the stage II and an operation unit 2g.
Is output, and the adder 3f outputs the result of the stage.
The result of adding the output of the shifter 2f of the II operation circuit 2 and the output of the adder 2h is output, and the adder 3g outputs the result of subtracting the output of the operation unit 2g from the output of the shifter 2e of the stage II operation circuit 32. , The subtractor 3h is a stage II arithmetic circuit 3
The result of subtracting the output of the arithmetic unit 2h from the output of the second shifter 2f is output. In this case, the adders 3a, 3b, 3e, and 3f and the subtractors 3c, 3d, 3g, and 3h output the respective calculation results at the timings shown in FIG. Become.

Next, the operation proceeds to the operation circuit 34 of the stage IV. In this arithmetic circuit 34, the arithmetic circuit 3 of stage III
The output of the adders 3a and 3b is COS (4/16) π arithmetic unit 4.
a, 4b, and similarly, the subtracters 3c, 3d
S (2/16) π and COS (6/16) π arithmetic units 4c and 4d are given separately, and the outputs of adders 3e and 3f are subjected to COS (1/16) π and COS (7/16) π arithmetic The outputs of the subtracters 3g and 3h are respectively given to COS (5/16) π and COS (3/16) π
The arithmetic units 4g and 4h are individually given. In this case, FIG.
COS (4/16) π arithmetic unit 4a, 4b
Then, the approximate value of COS (N / 16) π when N = 4 is (6-1) × (2+
1) × 4 + 1 operation is performed, and at the timing shown in FIG.
The calculation results are generated as output data F (0) and F (4). Similarly, for COS (2/16) π and COS (6/16) π arithmetic units 4c and 4d, the approximate value 4 × (64-4-1) + when COS (N / 16) πN = 2 The calculation of the approximate value 2 × (32 + 16 + 1) in the case of N = 6 of 1/2 and COS (N / 16) π is executed, and the calculation result is output data F at the timing shown in FIG. (2), F
(6), and the COS (1/16) π and COS (7/16) π calculators 4e, 4f also have an approximate value of 251 = (128−128) when N = 1 for COS (N / 16) π. 2) × 2-1 and N = 7 of COS (N / 16) π
Is performed, and the result of the calculation is output data F at the timing shown in FIG.
(1), generated as F (7), and COS (5/16) π
And COS (3/16) π calculators 4g and 4h also have COS (N / 1
6) Approximate value of 2 × (64 + 8-1) and COS (N / 1
6) Calculate the approximate value (2 + 1) × (64 + 8-1) in the case of N = 3 of π, and output the calculation result to the output data F (5), at the timing shown in FIG. F (3).

The above explanation is for the DCT operation, but the inverse DCT operation is the same as described above.

In this case, the input data is given in the order of the stage IV arithmetic circuit 34 to the stage I arithmetic circuit 31.

FIG. 26 is a timing chart from the input to the output of the data conversion operation device 12, and shows the timing of the stage I.
4 shows a timing chart when the operations of the arithmetic circuits 31 to 34 of the stage IV are integrated. In the figure, I, II, III, and IV represent the respective stages I, I in FIG.
The output of I, III, and IV is shown. In FIG. 26, consideration has been given to avoid overlapping of processing with the next data. When 8-bit data is input as a whole, a processing cycle per line requires 28 clocks. The processing in this case is the case of DCT processing of 8 bits of input data. However, when the number of bits of input data is different or in the case of inverse DCT processing, 1 processing is performed.
The processing cycle per data also changes.

As described above, in the discrete cosine transform processing based on the flow graph composed of the stages I to IV, each stage is configured to be serially processed, so that the input data is processed by the arithmetic circuit of each stage. , Serial processing is performed sequentially, and the circuit scale can be reduced and high-speed processing can be achieved compared to a conventional memory in which an arithmetic unit consisting of registers, shifters, and adders / subtractors is provided in parallel. can do.

[0033]

However, in a data compression / decompression device that performs such a serial DCT operation, the DCT operation is realized on a serial processing circuit as it is. Although the circuit scale can be significantly reduced as compared with the DCT operation device which performs the operation in parallel, as shown in FIG. However, there is a disadvantage that the circuit size is still large. In addition, there is a demand for speeding up the operation by reducing the number of operation stages because the delay is one clock each time one stage passes through the FF or the like.

Accordingly, an object of the present invention is to provide a data compression / decompression apparatus capable of compressing data at high speed with a small circuit scale.

[0035]

According to the first aspect of the present invention,
To achieve the above object, data storage means for storing predetermined data, data conversion operation means for performing a data conversion operation by serial operation based on a predetermined coefficient on the data output from the data storage means, Quantization means for performing a quantization operation on the data after data conversion by the data conversion operation means, the data storage means,
What is claimed is: 1. A data compression / decompression device comprising: a data conversion operation unit; and a control unit for controlling the quantization unit, wherein the data conversion operation expression is expanded by the data conversion operation unit, and the data conversion operation Means.

According to a second aspect of the present invention, there is provided a data storage means for storing predetermined data, and a data for executing a data conversion operation by a serial operation based on a predetermined coefficient with respect to the data outputted from the data storage means. Conversion operation means, quantization means for performing a quantization operation on the data after data conversion by the data conversion operation means, and control for controlling the data storage means, the data conversion operation means, and the quantization means A data compression / expansion apparatus comprising: In addition, the data conversion operation expression is expanded, and the data conversion operation means is configured according to the expanded expression.

According to a third aspect of the present invention, there is provided a data storage means for storing predetermined data, a parallel-serial conversion means for converting data in the data storage means from parallel data to serial data, and A data conversion operation unit for performing a data conversion operation by a serial operation on the output data based on a predetermined coefficient, and converting the serial data output from the data conversion unit into parallel data, Serial-parallel conversion means for writing, quantization means for performing a quantization operation on the data after the data conversion by the data conversion operation means, the data storage means, the parallel-serial conversion means, and the data conversion operation means Controlling the serial-parallel conversion means and the quantization means. A data compression / expansion device comprising: a control unit that replaces a coefficient of the data conversion operation unit with an integer ratio, and adjusts a change in gain caused by replacing the coefficient with the integer ratio by the quantization unit. In addition, a data conversion operation expression is developed, and the data conversion operation means is configured according to the expanded expression.

According to a fourth aspect of the present invention, there is provided a data storage means for storing predetermined data, and a data for executing a data conversion operation by a serial operation on the data output from the data storage means based on a predetermined coefficient. Conversion operation means, quantization means for performing a quantization operation on the data after data conversion by the data conversion operation means, and control for controlling the data storage means, the data conversion operation means, and the quantization means Means for expressing a coefficient value of a data conversion operation expression of the data conversion operation means by a power of 2 and a value which is not less than a predetermined value when expressing the value of the coefficient by a power of 2 For the portion where the number of bits is large, the coefficient is replaced with an integer ratio, and the change in gain caused by replacing the integer ratio is
In addition to the adjustment by the quantization means, a data conversion operation expression is developed, and the data conversion operation means is configured according to the expanded expression.

The data conversion operation means expands the data conversion operation expression so that a predetermined coefficient appears at each input, and a coefficient part of the expanded data conversion operation expression. And a second serial operation unit that adds and subtracts the output of the first serial operation unit and executes the operation of the expanded data conversion operation expression. The first serial operation unit may express the coefficient of the expanded data conversion operation expression in a form obtained by multiplying a numerical value by a power of two, as described in claim 6, for example. May be constituted by a serial circuit that performs a serial operation on a numerical value part when the numerical value is expressed by multiplying a numerical value by a power of 2. The second serial operation unit may be configured, for example, as described in claim 7. A plurality of adder / subtracters for adding and subtracting the numerical value output from the first serial operation unit and outputting the result. The coefficients of the expanded data conversion operation expression are multiplied by a power of two. The power of 2 in the case of expression may be adjusted by the input position to each adder / subtractor.

Further, the data conversion operation means may be orthogonal transformation means for executing orthogonal transformation by serial operation on data, for example, as set forth in claim 8. Is, for example, claim 9
, A discrete cosine transform unit that executes a discrete cosine transform (DCT) by serial operation on data may be used. Further, the data conversion operation means may be, for example, as described in claim 10.
The data conversion operation unit may be configured to include a serial operation unit that sequentially moves input data in response to a predetermined clock, wherein the data conversion operation unit includes, for example, a data conversion operation expression May be configured by a serial circuit expressing the value of the coefficient by a power of 2, and the data conversion operation may be performed by a serial operation by the serial circuit.
For example, as described in claim 12, when a value of a coefficient of a data conversion operation expression is expressed by a power of 2, and when the value of the coefficient is expressed by a power of 2, a portion where the number of bits becomes larger than a predetermined value is considered. May be constituted by a serial circuit in which the coefficient is replaced by an integer ratio, and a data conversion operation may be executed by a serial operation by the serial circuit.

In the data conversion operation expression used in the data conversion operation means, for example, the coefficients of the data conversion operation expression are used for the quantization operation of the quantization means. The gain may be adjusted so as to be included in the quantization coefficient, and the adjustment of the gain by the quantization means may be performed, for example, by changing the coefficient of the data conversion operation means to an integer ratio, as described in claim 14. May be performed by a quantization table configured to absorb the gain change caused by the above. Further, the replacement of the coefficient by the data conversion operation means with an integer ratio may be performed by replacing the coefficient with an integer value, for example.

[0042]

The function of the present invention is as follows.

According to the first aspect of the present invention, a data conversion operation expression of the data conversion operation means is expanded for each term, and a serial circuit is configured according to the expanded expression. In this case, the serial circuit configured according to the expanded equation
For example, a first serial operation unit that serially operates on a coefficient portion when a data conversion operation expression is expanded so that a coefficient common to each input appears, and a data conversion operation that is expanded by adding and subtracting the output of the serial operation unit And a second serial operation unit for executing the operation of the expression. When each input is input to the serial circuit, the first serial operation unit serially operates each input to obtain a coefficient. The second serial operation unit performs addition and subtraction on the coefficients created as described above, and executes an operation of a data conversion operation expression developed.

Therefore, by configuring a serial circuit in accordance with the developed data conversion operation formula, the number of serial circuits such as a shift register can be reduced, the number of clocks can be reduced, and the processing speed can be improved.

Claims 2, 3, 4, 5, 6, 7, 8, 9,
In the inventions described in 10, 11, 12, 13, 14 and 15, the coefficients of the data conversion operation means are replaced by integer ratios, the change in the gain is adjusted by the quantization means, and the data conversion operation expression is developed. Then, the serial circuit is configured according to the developed formula. in this case,
The serial circuit includes, for example, a first serial operation unit that performs a serial operation on a numerical value part in a case where a coefficient of an expanded data conversion operation expression is multiplied by a power of 2 and a serial operation unit that is output from the serial operation unit A second serial operation unit comprising a plurality of adders / subtracters for adding and subtracting numerical values and outputting the result. When each input is input to this serial circuit, the first serial operation unit serially operates each input to obtain a coefficient. The second serial operation unit performs addition and subtraction on the coefficients created in this way, and the expansion of the data conversion expression is performed. At this time, when a coefficient of the developed data conversion operation expression is expressed in a form obtained by multiplying a power of 2 by a numerical value, a power of 2 is adjusted by an input position to each adder / subtractor.

Further, a data conversion operation expression is prepared so that the coefficients of the data conversion operation expression are included in the quantized coefficients used for the quantization operation, and the coefficients of the data conversion operation expression thus generated are calculated. The value is expressed by a power of 2 to form a serial circuit. At this time, if the value of the coefficient is to be expressed by a power of 2, for a portion where the number of bits becomes larger than a predetermined value, the coefficient is replaced with an integer ratio, and the gain caused by the replacement with the integer ratio is generated. The change is adjusted by the quantization means.

Therefore, as compared with the case where a serial circuit is simply realized, the circuit scale can be greatly reduced, and the number of clocks can be reduced by reducing the number of serial circuits such as shift registers. Speed can be improved, and it can be used for data compression of images and the like.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Explanation of Principle (I) First, the basic concept of this embodiment will be described. In the conventional data compression / decompression device shown in FIG. 11, a butterfly operation is directly represented on a serial circuit in order to realize a DCT operation by a serial operation. In particular,
Since the serial DCT operation circuit as shown in FIG. 22 was realized by expressing the COS coefficient value by a power of 2,
If the coefficients of the DCT operation expression are all expressed by powers of two, the number of bits becomes large, and therefore the number of stages such as FFs constituting the serial circuit becomes large.

By the way, the image data subjected to the DCT operation is quantized by a quantizing unit (for example, the quantizing device 14 in FIG. 11) in the subsequent stage.

By paying attention to this point, the present inventor expresses a part which can be expressed by a power of 2 as an exponent and uses it for capturing. Instead of dare to express the power, the operation coefficient of the DCT is replaced with an integer ratio (or an integer value) without being bound to the power of 2, and the gain change is absorbed by the quantization unit. This makes it possible to greatly reduce the circuit scale and improve the processing speed by reducing the number of serial stages, as compared with a case where a serial circuit is realized by a power of two.

(II) Further, even when the above-described DCT operation expression is constituted by a serial circuit, since the DCT operation expression is realized by using addition / subtraction and butterfly operation, it is difficult to reduce the number of stages such as FFs to a certain extent. In order to improve the speed, it has been required to further reduce the number of stages such as FFs.

Therefore, in the present embodiment, the coefficients are divided so that a common coefficient (not necessarily common) appears in each input by expanding the DCT arithmetic expression, and the DCT arithmetic expression thus expanded is developed. The hardware is used as it is without being bound by butterfly operations. For this reason, first, the calculation of the coefficients used for each input is performed in the preceding serial circuit, and the addition and subtraction including the sign in the output direction is performed on the coefficient output calculated in the subsequent serial circuit. Then, the DCT operation expression is directly converted into hardware. Thus, the number of stages such as FFs can be reduced, and the number of clocks (time) can be reduced.

For example, as shown in FIG. 1, if the DCT arithmetic expression is expanded to obtain coefficients 17, 85, 48, and 72 common to each input, first, the DCT operation is performed by the serial circuit in the preceding stage.
A part corresponding to the coefficient of the arithmetic expression is created. In this case, the coefficients 17, 85, 48, and 72 are expressed in a form multiplied by a power of 2, and a portion of the numerical value (see a numerical value in a broken line in FIG. 1) is configured by a serial circuit. The power of 2 is adjusted by the input position to the serial circuit at the subsequent stage. That is, as shown in FIG. 1, the serial circuit at the subsequent stage is an adder (including a subtractor).
Are connected so that each adder is
Each time a step is passed, x2 is entered. The part expressed by a power of 2 of the above coefficients is adjusted by the connection method to each adder. Here, the coefficients 17, 85, 48, 7
Of the two, the addition of the odd number (coefficients 17, 85) is basically performed first for the following reason. That is, it is difficult to generate odd-numbered coefficients due to the structure of the serial circuit in which the clock is delayed by one clock each time it is added once, and an operation of adding 1 to generate odd-numbered coefficients is required. For this reason, first, the complicated odd coefficients are added in advance. In FIG.
Considering that the coefficient 85 is 42 × 2 ¹ +1 and the coefficient 17 is 16 + 1, one of these odd coefficients is added once beforehand. As a result, it becomes × 2 times delayed by one clock. Next, another clock is required to add the sum of the other parts to the sum of the odd ones, which is × 4 times as a whole. That is,
If there are two or more odd coefficients, it is necessary to pass through the adder twice, and x4 is the minimum form. If the odd numbers are eliminated, the calculation accuracy decreases.

In FIG. 1, the coefficient 17 is 2 × 2 ³ +
1, the coefficient 48 is represented by 6 × 2 ³ , and the power of 2 is the same 2 ³
Therefore, this part is added by the first-stage adder. Thereafter, the coefficient is doubled each time it passes through one step of the adder, so that the result of addition of the coefficients is completed in the third step of the adder. Also, since the coefficient 72 is represented by 18 × 2 ² and the coefficient 85 is represented by 42 × 2 ¹ +1, the 18 of the coefficient 72
In the second adder, 42 of the coefficient 85 is input to the third adder.

As described above, the number of stages such as FFs can be reduced and the number of clocks (time) can be reduced by using the DCT arithmetic expression as hardware as it is.

Embodiment FIGS. 2 to 10 are views showing an embodiment of a data compression / expansion apparatus based on the above basic principle. FIGS. 2 to 5 are diagrams showing a data compression / expansion apparatus based on the above basic principle (I). 6 to 10 are views for explaining a data compression / decompression device based on the above basic principle (II).

First, the configuration of the data compression / decompression device based on the basic principle (I) will be described.

FIG. 2 is a block diagram of the data compression / expansion device, and corresponds to the data compression / expansion device of FIG. The same components as those of the conventional example are denoted by the same reference numerals. In FIG. 2, a data compression / decompression device is a data storage device 10 for storing two-dimensional data to be compressed and data after a data conversion operation in the form of parallel data.
And a parallel-serial converter 11 for converting parallel data read from the data storage device 10 into serial data, and a simple integer ratio (or,
A data conversion operation device 50 configured by a serial circuit in a form changed to an integer value and performing one-dimensional DCT operation on the data output from the parallel-serial conversion device 11 in the form of a serial operation; A serial-to-parallel converter 13 for converting the serial data into parallel data and writing the parallel data to the data storage device 10;
The data after the data conversion operation stored in the data storage device 10 is divided by a value of a quantization table configured to absorb a gain change caused by changing a DCT operation coefficient to an integer ratio (or Quantization device 51 that performs a quantization operation by performing a reciprocal multiplication.
And a control unit 52 for controlling the operation of each of the above-described units as a whole of the data compression / decompression apparatus.

FIG. 3 is a diagram showing a circuit configuration of the data conversion operation device 50 for executing the serial DCT operation, and is composed of stages I to IV.

In FIG. 3, reference numeral 61 denotes a stage I operation circuit, 62 denotes a stage II operation circuit, and 63 denotes a stage III operation circuit.
Is an operation circuit of stage IV, and operation circuits 61 to 64 of these stages I to IV are configured to be connected in series via switches 65 to 69, respectively. In this case, in the DCT operation processing, the operation circuits are connected in series in the order of the operation circuits 61 to 64 as shown in FIG. 2, and in the processing of the inverse DCT operation, the operation of the switches 65 to 69 is performed in the order of the operation circuits 64-61. It is connected directly. Then, the DCT or inverse DCT operation result for the input data supplied to the input terminal 70 is output from the output terminal 71. In this case, the input data consists of eight serial lines.

FIG. 4 is a circuit diagram of a data conversion operation device 50 of the data compression / decompression device based on the basic principle (I).
FIG.

In FIG. 4, the operation circuit 61 of stage I
Performs the above-described serial operation, and includes adders 81a, 81b, 81c, 81d and subtracters 81e, 81d.
f, 81g and 81h. The configuration of the operation circuit 61 of this stage I is the same as that of the conventional example, but the input of the input data f0 to f7 is different.

The operation circuit 62 of the stage II executes the serial operation described in the principle explanation (I). The serial operation unit 82a performs the DCT serial operation when the coefficient is approximated to a simple integer ratio. ~ 82h. Here, the arithmetic unit 82a includes an adder 81
adder 82 that adds the output of a and the output of adder 81d
a1, a shifter 82a2 composed of three flip-flops (FF) for shifting the output of the adder 82a1. The arithmetic unit 82b is provided with an adder 81b.
Adder 82b that adds the output of the adder 81c and the output of the adder 81c
1. The shifter 82b2 comprises three flip-flops (FF) for shifting the output of the adder 82b1. The arithmetic unit 82c is a subtractor 82c that subtracts the output of the adder 81c from the output of the adder 81b.
1, a shifter 82c2 composed of three flip-flops for shifting the output of the subtractor 82c1, and a shifter 82c2
Of the first flip-flop and shifter 82c2
Of the adder 82c3 and the second shifter 82c2
An adder 82c4 adds the output of the flip-flop and the output of the adder 82c3. Similarly, the arithmetic unit 82d includes a subtractor 82d1 for subtracting the output of the adder 81d from the output of the adder 81a, a shifter 82d2 composed of three flip-flops for shifting the output of the subtractor 82d1, and a shifter 82d2. The adder 82d3 adds the output of the first flip-flop and the output of the shifter 82d2, and the adder 82d4 adds the output of the second flip-flop of the shifter 82d2 and the output of the adder 82d3.

The arithmetic unit 82e is provided with a shifter 8 composed of five flip-flops for shifting the output of the subtractor 81e.
2e1, an adder 82e2 for adding the output of the third flip-flop of the shifter 82e1 and the output of the fourth flip-flop, a shifter 82e3 for shifting the output of the adder 82e2, and a first flip-flop of the shifter 82e1. And the adder 82e4 for adding the output of the fifth flip-flop. The arithmetic unit 82f includes a subtractor 82f1 for subtracting the output of the subtractor 81f from the output of the subtractor 81g, a shifter 82f2 including four flip-flops for shifting the output of the subtractor 82f1, and a second shifter 82f2. The adder 82f3 for adding the output of the second flip-flop and the output of the third flip-flop, the output of the subtractor 82f1 and the shifter 82
It comprises an adder 82f4 for adding the output of f2. The arithmetic unit 82g includes an adder 82g1 for adding the output of the subtractor 81f and the output of the subtractor 81g, a shifter 82g2 composed of four flip-flops for shifting the output of the adder 82g1, and a second shifter 82g2. It comprises an adder 82g3 for adding the output of the second flip-flop and the output of the third flip-flop, and an adder 82g4 for adding the output of the adder 82g1 and the output of the shifter 82g2. The arithmetic unit 82h shifts the output of the subtractor 81h by five flip-flops, and adds the output of the third flip-flop and the output of the fourth flip-flop of the shifter 82h1. It comprises an adder 82h2, a shifter 82h3 for shifting the output of the adder 82h2, and an adder 82h4 for adding the output of the first flip-flop and the output of the fifth flip-flop of the shifter 82h1.

The operation circuit 63 of the stage III executes the serial operation described in the principle explanation (I). The adder 83a adds the output of the operation unit 82a and the output of the operation unit 82b2, and the subtractor From the output of 82a,
A subtractor 83b for subtracting the output of b, a subtractor 83c for subtracting the output of the adder 82c4 of the arithmetic unit 82c from the output of the adder 82d3 of the arithmetic unit 82d, and an adder 82 for the arithmetic unit 82c
An adder 83d that adds the output of c3 and the output of the adder 82d4 of the calculator 82d, an adder 83e that adds the output of the adder 82e4 of the calculator 82e and the output of the adder 82f3 of the calculator 82f, A subtractor 83f for subtracting the output of the adder 82f4 of the arithmetic unit 82f from the output of the shifter 82e3, and a subtracter 83 for subtracting the output of the adder 82f4 of the arithmetic unit 82g from the output of the adder 82h3 of the arithmetic unit 82h.
g, the output of the adder 82g3 of the arithmetic unit 82g and the arithmetic unit 82
An adder 83h adds the output of the adder 82h4 of h.

The operation circuit 64 of the stage IV executes the serial operation described in the principle explanation (I). The serial operation unit 84a performs the DCT serial operation when the coefficient is approximated to a simple integer ratio. ~ 84h. Here, the arithmetic unit 84a includes an adder 83
a shifter 84a1 composed of six flip-flops for shifting the output of a, an adder 84a2 for adding the output of the fifth flip-flop of the shifter 84a1 and the output of the sixth flip-flop, and the output of the adder 84a2. The shifter 84a1 includes a subtractor 84a3 that subtracts the output of the third flip-flop of the shifter 84a1 and outputs the result as output data F0. The arithmetic unit 84b includes a subtractor 8
A shifter 84b1 comprising six flip-flops for shifting the output of 3b, an adder 84b2 for adding the output of the fifth flip-flop of the shifter 84b1 and the output of the sixth flip-flop, and the output of the adder 84b2 The shifter 84b1 includes a subtracter 84b3 that subtracts the output of the third flip-flop of the shifter 84b1 and outputs the result as output data F4. The arithmetic unit 84c shifts the output of the subtractor 83c by five flip-flops, and adds the output of the third flip-flop and the output of the fifth flip-flop of the shifter 84c1. Adder 8 which outputs as output data F6
4c2. Further, the computing unit 84d
Is a shifter 84d1 composed of five flip-flops for shifting the output of the adder 83d, and outputs the output of the third flip-flop and the output of the fifth flip-flop of the shifter 84d1 and outputs the result as output data F2. And an adder 84d2.

The arithmetic unit 84e includes a shifter 8 composed of two flip-flops for shifting the output of the adder 83e.
4e1, an adder 84e2 for adding and outputting the output of the adder 83e and the output of the shifter 84e1, and a shifter 84h1 described later.
From the output of the first flip-flop of the adder 8
A subtractor 84e3 for subtracting the output of 4e2, a subtractor 84e3
Shifter 84e4 composed of two flip-flops for shifting the output of
It comprises a subtractor 84e5 which subtracts the output of e3 and outputs it as output data F7. Further, the computing unit 84
f is a shifter 84f1 composed of two flip-flops for shifting the output of the subtracter 83f, an adder 84f2 for adding the output of the subtractor 83f and the output of the first flip-flop of the shifter 84f1, and an adder g2 to be described later. Subtracter 84f3 for subtracting the output of shifter 84f1 from the output of
It comprises a shifter 84f4 composed of two flip-flops for shifting the output of the subtractor 84f3, and a subtractor 84f5 for subtracting the output of the shifter 84f4 from the output of the subtractor 84f3 and outputting it as output data F3. The arithmetic unit 84g includes a shifter 84g1 composed of two flip-flops for shifting the output of the subtractor 83g, and a subtractor 8g.
An adder 84g2 for adding the output of 3g and the output of the first flip-flop of the shifter 84g1, an adder 84g3 for adding the output of the adder f2 and the output of the shifter 84g1,
The shifter 84g4 comprises two flip-flops for shifting the output of the adder 84g3, and a subtractor 84g5 for subtracting the output of the adder 84g3 from the output of the shifter 84g4 and outputting the result as output data F5. The arithmetic unit 84h includes a shifter 84h1 composed of two flip-flops for shifting the output of the adder 83h,
The adder 84h2 adds the output of the shifter 84h1 and the output of the shifter 84h1, and outputs the result. The adder 84h3 adds the output of the first flip-flop of the shifter 84e1 and the output of the adder 84h2, and shifts the output of the adder 84h3. Shifter 84h4 and shifter 84 composed of two flip-flops
It comprises a subtractor 84h5 that subtracts the output of the adder 84h3 from the output of h4 and outputs the result as output data F1.

Next, referring to FIGS. 6 to 8, the basic principle (I
The configuration of the data compression / decompression device based on I) will be described.

It is considered that the concept of the basic principle (II) is applied to the data conversion operation device 50 shown in FIG. FIG.
Looking at the structure of each of the stages I to IV of the data conversion operation device 50, the structure of the stage I has a simple form, and the final stage on the output side of the stage IV has a simple form of only addition and subtraction. Have difficulty. Stage I
Each of I, III, and IV has a butterfly operation unit and has a complicated structure. In addition, a timing-matching FF exists on the even (even number) side of the stage IV. In particular, the stages II, III, and IV on the odd (odd) side have a two-stage butterfly operation unit. By simplifying the butterfly operation unit on the odd side, the operation execution speed of the entire data conversion operation device 50 can be reduced. Can be improved. In this embodiment, the concept of the basic principle (II) is applied to the odd side of the data conversion operation device 50.

FIG. 6 is a circuit diagram of a data conversion operation device 50 of the data compression / decompression device, which is the same as the data conversion operation device 50 shown in FIG. FIG.
Data conversion operation device 50 when bit data is input
5 is a timing chart from input to output of the system. FIG.
Attention is focused on the odd side of the data conversion operation device 50, whose structure is difficult to simplify, and as shown by the broken line in FIG. Are simplified, and the concept of the basic principle (II) is applied to this portion for simplification.

FIG. 7 is a circuit diagram of a data conversion operation device 90 of the data compression / decompression device based on the basic principle (II), and corresponds to the data conversion operation device 50 shown in FIG. The data conversion operation device 90 shown in FIG. 7 is configured to improve the speed of the entire data conversion operation device 90 by configuring the inside of the broken line in FIG. 6 as shown in FIG. In describing FIGS. 7 and 8, the same components as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 7, a data conversion operation device 90 is composed of stages I to III, and an operation circuit 91 of stage I includes adders 81a and 81 for executing serial operations.
b, 81c, 81d and subtractors 81e, 81f, 81g,
81h.

The operation circuit 92 of the stage II executes the serial operation described in the principle explanation (I) on a serial circuit in which the DCT operation expression described in the principle explanation (II) is directly converted into hardware. The even side is composed of serial computing units 92a to 92d for performing DCT serial computation by approximating the coefficient to a simple integer ratio, and the odd side is composed of a serial circuit 100 (FIG. 8) in which the DCT computation expression is directly converted into hardware. It is configured.

Further, the serial computing units 92a to 92d
Are serial operation units 82a to 82d for performing DCT serial operation, and addition and subtraction units 83a to 83 for adding and subtracting the outputs of these operation units 82a to 82d by butterfly operation.
3d, and the even-side stage of FIG.
It is equivalent to the combination of II and Stage III. here,
The arithmetic unit 82a is provided with the output of the adder 81a and the adder 81
adder 82a1 for adding the output of the
three flip-flops (F
F). The arithmetic unit 82b includes an adder 82b1 for adding the output of the adder 81b and the output of the adder 81c, and three flip-flops for shifting the output of the adder 82b1. And a shifter 82b2 composed of a flip-flop (FF). The arithmetic unit 82c includes a subtracter 82c1 for subtracting the output of the adder 81c from the output of the adder 81b, a shifter 82c2 including three flip-flops for shifting the output of the subtractor 82c1, and a second shifter 82c2. Adder 8 for adding the output of the first flip-flop and the output of shifter 82c2
2c3, an adder 82c4 for adding the output of the second flip-flop of the shifter 82c2 and the output of the adder 82c3. Similarly, the arithmetic unit 82d includes a subtractor 82d1 for subtracting the output of the adder 81d from the output of the adder 81a, a shifter 82d2 composed of three flip-flops for shifting the output of the subtractor 82d1, and a shifter 82d2. An adder 82d3 for adding the output of the first flip-flop and the output of the shifter 82d2;
The output of the second flip-flop of d2 and the adder 82
It comprises an adder 82d4 for adding the output of d3. The subsequent stages of the serial computing units 92a to 92d execute the serial computation described in the principle explanation (I), and include an adder 83a for adding the output of the computing unit 82a and the output of the computing unit 82b2, Subtractor 83b for subtracting the output of arithmetic unit 82b from the output of 82a, arithmetic unit 82c
From the output of the adder 82c4 to the adder 82 of the arithmetic unit 82d.
It comprises a subtracter 83c for subtracting the output of d3, and an adder 83d for adding the output of the adder 82c3 of the arithmetic unit 82c and the output of the adder 82d4 of the arithmetic unit 82d.

The odd of the operation circuit 92 of the stage II
The configuration of the serial circuit 100 on the side will be described later with reference to FIG.

The operation circuit 93 of the stage III executes the serial operation described in the principle explanation (I). To 93h.

Here, the arithmetic unit 93a is provided with an adder 83
a shifter 93a1 composed of three flip-flops for shifting the output of a, an adder 84a2 for adding the output of the second flip-flop of the shifter 93a1 and the output of the third flip-flop, and the output of the adder 84a2. It comprises a subtractor 84a3 which subtracts the output of the adder 83a and outputs it as output data F0. The arithmetic unit 93b shifts the output of the subtracter 83b by three flip-flops, and adds the output of the second flip-flop and the output of the third flip-flop of the shifter 93b1. Adder 84b
2. It comprises a subtractor 84b3 that subtracts the output of the subtractor 83b from the output of the adder 84b2 and outputs it as output data F4. The arithmetic unit 93c includes a subtractor 83
The shifter 93c1 is composed of two flip-flops for shifting the output of c and an adder 84c2 that adds the output of the second flip-flop of the shifter 93c1 and the output of the subtractor 83c and outputs the result as output data F6. ing. The arithmetic unit 93d is provided with a shifter 9 composed of two flip-flops for shifting the output of the adder 83d.
3d1, the output of the second flip-flop of the shifter 93d1 and the output of the adder 83d are added to generate output data F
It is composed of an adder 84d2 which outputs as 2.

The arithmetic unit 93e is a shifter 84e4 comprising two flip-flops for shifting the output x0 of the serial circuit 100. Computing unit 93f
Is a shifter 84f4 composed of two flip-flops for shifting the output x1 of the serial circuit 100, and a subtractor 84
It comprises a subtractor 84f5 that subtracts the output of the shifter 84f4 from the output of f3 and outputs the result as output data F3. The arithmetic unit 93g includes a shifter 84g4 composed of two flip-flops for shifting the output x2 of the serial circuit 100, and an adder 84g based on the output of the shifter 84g4.
The arithmetic unit 93h comprises a shifter 84h4 composed of two flip-flops for shifting the output x3 of the serial circuit 100, and an output of the adder 84h3. And a subtractor 84h5 for subtracting the output of the shifter 84h4 from the output and outputting the result as output data F1.

As described above, the serial computing units 93a to 93d on the even side of the stage III correspond to the stages of FIG.
IV serial operation units 84a to 84d shifters 84a1 to 84a1 to 84d
84d1 has three stages of flip-flops (FF) removed, and the serial operation units 93e to 93h on the odd side of the stage III are the stages shown in FIG.
From the calculators 84e to 84h of the IV, the butterfly calculation part (for example, the shifter 84e1, the adder 84e2 and the subtractor 84e3 in the calculator 84e, the shifter 84f1, the adder 84f2 and the subtractor 84f in the calculator 84f)
3. In the operation unit 84g, the shifter 84g1, the adder 8
The 4g2, the adder 84g3, and the arithmetic unit 84h have a configuration in which the shifter 84h1, the adder 84h2, and the adder 84h3) are removed.

FIG. 8 is a circuit configuration diagram of the serial circuit 100 in which the DCT operation formula is directly converted into hardware. As described above, the serial circuit 100 is configured by applying the concept of the basic principle (II) to the portion indicated by the broken line in FIG.

For the operation within the broken line in FIG.
Ｂb3 and the output is x03x3, the serial circuit 100
Is a serial circuit 10 in the preceding stage for creating a part of a numerical value when a coefficient common to each of the inputs b0 to b3 obtained by expanding the DCT arithmetic expression is multiplied by a power of two.
1 and a serial circuit 102 at the subsequent stage which performs addition and subtraction including a sign in the output direction (horizontal direction of the DCT operation expression) with respect to the coefficient output calculated by the serial circuit 101 and outputs the result as outputs x0 to x3. Have been. In other words, the serial circuit 101 uses the coefficients common to the inputs b0 to b3 for the input b0 (in this embodiment, 17 and 8
5, 48, 72) multiplied by a power of 2 (in this embodiment, 2, 42, 6, 18), a serial calculator 101e for creating a portion of the numerical value, input b1 When a coefficient common to each of the inputs b0 to b3 is expressed by multiplying a numerical value by a power of 2, a serial operation unit 101f that creates a part of the numerical value, and a coefficient common to each of the inputs b0 to b3 for the input b2 Is expressed in the form of a power of 2 multiplied by a number, a serial arithmetic unit 101g that creates a portion of the numerical value, and for input b3, a coefficient common to each of inputs b0 to b3 is multiplied by a power of 2 It is composed of a serial calculator 101h that creates the numerical value part when expressed in the form. Specifically, the serial operation unit 101e
Is a shifter 101e1 composed of three flip-flops for shifting the input b0, an adder 101e2 for adding and outputting the input b0 and the output of the first flip-flop of the shifter 101e1, and adding the input b0 and the output of the shifter 101e1. Adder 101e3 for adding and outputting the output of the first flip-flop of shifter 101e1 and the output of shifter 101e1, and adder for adding and outputting input b0 and the output of adder 101e4. 101
e5. Similarly, the serial operator 10
1f is a shifter 101f1 composed of three flip-flops for shifting the input b1, an input b0 and a shifter 101f1.
Adder 101f2 that adds and outputs the output of the first flip-flop, adder 101f3 that adds and outputs the input b0 and the output of shifter 101f1, and shifter 101f1
Output of the first flip-flop and shifter 101f
Adder 101f4 for adding and outputting the output of 1 and input b0
Adder 1 that adds and outputs the output of adder 101f4
01f5. In addition, serial computing unit 1
01g is a shifter 101g1 composed of three flip-flops for shifting the input b2, an input b0 and a shifter 101g.
1, an adder 101g2 that adds and outputs the output of the first flip-flop, an adder 101g3 that adds and outputs the input b0 and the output of the shifter 101g1, and a shifter 101
The output of the first flip-flop of g1 and the shifter 10
It comprises an adder 101g4 for adding and outputting the output of 1g1, and an adder 101g5 for adding and outputting the input b3 and the output of the adder 101g4. The serial operation unit 101h includes a shifter 101e1 composed of three flip-flops for shifting the input b0, an input b0 and the shifter 101.
The adder 101h2 adds and outputs the output of the first flip-flop of h1, the adder 101h3 adds and outputs the input b0 and the output of the shifter 101h1, and the shifter 10
1h1 output of the first flip-flop and shifter 1
It comprises an adder 101h4 for adding and outputting the output of 01h1, and an adder 101h5 for adding and outputting the input b0 and the output of the adder 101h4.

The serial circuit 102 sequentially performs addition and subtraction including the sign in the output direction with respect to the coefficient output calculated by the serial calculators 101e to 101h, and outputs the result as outputs x3 to x0.
Ｈ102h. That is, the serial arithmetic unit 102e is an adder 102e1 that adds the output of the adder 101f2 of the serial arithmetic unit 101f and the output of the first flip-flop of the shifter 101e1 of the serial arithmetic unit 101e, and the output of the adder 102e1. An adder 102e2 for adding the output of the adder 101g3 of the serial calculator 101g, an adder 102e3 for adding the output of the adder 102e2 and the output of the adder 101h5 of the serial calculator 101h, and the output and input b3 of the adder 102e3. Adder 102e4 that adds
4 and the output of the first flip-flop of the shifter 101e1 of the serial operation unit 101e, and the output x3
And an adder 102e5 that outputs the same as
The serial operation unit 102f includes a subtracter 102f1 for subtracting the output of the first flip-flop of the shifter 101f1 of the serial operation unit 101f from the output of the adder 101h2 of the serial operation unit 101h.
02f1 output and the adder 10 of the serial operation unit 101e
Adder 102f2 for adding the output of 1e3;
02f2 output and the adder 10 of the serial operation unit 101g
Adder 102f3 for adding the output of 1g5,
An adder 102f4 for adding the output of 02f3 and the input b2;
From the output of the adder 102f4, the serial
subtracter 102f5 that subtracts the output of the first flip-flop of shifter 101f1 of f and outputs the result as output x2
It is composed of Further, the serial computing unit 102
g is the output of the adder 101e2 of the serial operation unit 101e and the first output of the shifter 101g1 of the serial operation unit 101g.
Adder 102 for adding the output of the flip-flop
g1, a subtractor 102g that subtracts the output of the adder 102g1 from the output of the adder 101h3 of the serial operation unit 101h.
2. From the output of the subtractor 102g2,
Subtractor 102 for subtracting the output of 1f adder 101f5
g3, a subtractor 102g4 for subtracting the input b1 from the output of the subtractor 102g3, and subtracting the output of the first flip-flop of the shifter 101g1 of the serial operation unit 101g from the output of the subtractor 102g4, and outputting the result as an output x1. It comprises a subtractor 102g5. Further, the serial operation unit 102h is a subtractor 102h1 for subtracting the output of the adder 101g2 of the serial operation unit 101g from the output of the first flip-flop of the shifter 101h1 of the serial operation unit 101h, and the output of the subtracter 102h1. An adder 102h2 for adding the output of the adder 101f3 of the serial calculator 101f, a subtractor 102h3 for subtracting the output of the adder 101e5 of the serial calculator 101e from the output of the adder 102h2, and an input b0 from the output of the subtractor 102h3. , And an adder 102h5 that adds the output of the subtractor 102h4 and the output of the first flip-flop of the shifter 101h1 of the serial calculator 101h and outputs the result as an output x0.

Next, the operation of this embodiment will be described.

In describing the operation of this embodiment, first, the overall operation of the data compression / decompression device will be described, and then the operation of the data conversion operation device 50 based on the basic principle (I) and the data based on the basic principle (II) will be described. Conversion arithmetic unit 9
The operation at 0 will be described.

Overall Operation In FIG. 2, parallel data stored in a data storage device 10 is input to a parallel-serial conversion device 11, which converts the parallel data read from the data storage device 10 into serial data. And outputs it to the data conversion operation device 50. The data conversion operation device 50 performs a one-dimensional DCT operation on the data output from the parallel-serial conversion device 11 in the form of a serial operation. The serial operation in this case is performed by a data conversion operation device 50 using a serial circuit in which the DCT operation coefficient is changed to a simple integer ratio. The data subjected to the serial DCT operation is output to the serial-to-parallel converter 13 and the serial-to-parallel converter 13
Converts the serial data output from the data conversion operation device 50 into parallel data and writes it to the data storage device 10. The above-described processing is performed in two dimensions vertically and horizontally (in no particular order).
The quantization device 51 is configured to absorb a change in gain caused by changing a DCT calculation coefficient into a simple integer ratio for the data after the data conversion calculation stored in the data storage device 10. A quantization operation is performed by multiplying the reciprocal by the value of the quantization table. That is, the DCT operation coefficient is changed to a simple integer ratio, and the change in the gain of each output caused by being expressed as the integer ratio is absorbed in the quantization device 51. In this embodiment, the quantization device 51 absorbs the change in gain by multiplying the quantization table by a predetermined number (described later). By the way, when using such a quantization table, it seems at first glance that the bit width of the quantization operation is required to be larger than that of the conventional one, but actually, Since the quantization operation is multiplication of the reciprocal, the reciprocal of the coefficient (for example, 7) is also 7 × 2
Since the reciprocal of / COS (N / 16) π is also an infinite decimal number,
Requires rounding approximation and contains about the same error. That is, since the rounding error is added when the conventional COS coefficient is expressed as a decimal number of two advances, it is not necessary to increase the bit width to suppress the error even if it is replaced by an integer ratio.

The serial DCT operation executed by the data conversion operation device 50 is performed by the serial operation described below.

Operation in Data Conversion Operation Device 50 (FIG. 4) The basic operation of the data conversion operation device 50 is the same as that of the conventional example shown in FIG. 22, but the serial operation in the data conversion operation device 50 will be described later. Since the gain per dimension has changed by a factor of 65/64, and the gain by a factor of 4225/4096 in the two dimensions, the quantization table is multiplied by 4225/4096 so that the correction is performed during quantization. Is corrected by dividing (multiplication of the reciprocal number) by.

Hereinafter, this calculation will be described.

The output of the operation circuit 61 of the stage I is the same as that of the conventional example shown in FIGS. 18 and 22, and will be described as follows.

F0 + f7 = a0, f0-f7 = b0, f1 + f6 = a
1, f1-f6 = b1, f2 + f5 = a2, f2-f5 = b2, f3 + f4 =
a3, f3-f4 = b3 First, in the conventional example shown in FIG.
And how they were represented by b0-b3.

F0 = (724a0 + 724a1 + 724a2 + 724a3) × 2048 F4 = (724a0−724a1−724a2 + 724a3) × 2048 F2 = (473a0 + 192a1−192a2−473 × 3 × 16963) × 4096F6 = (192 + 047 + 312) F7 = (-15104b0 + 25883b1-16833b2 + 2550b3) .times.16 F3 = (-18176b0-64255b1-12815b2 + 27264b3) .times.16 F5 = (27264b0 + 12815b1-64255b2 + 18176b3) .times.16 This equation is simplified as follows.

F0 = (92a0 + 92a1 + 92a2 + 92a3) .times.128 F4 = (92a0-92a1-92a2 + 92a3) .times.128 F2 = (60a0 + 25a1-25a2-60a3) .times.256 F6 = (25a0-60a1 + 60a2 + 1 @ 2 + 2 @ 56 + 7 @ 2) + 256 + 2 @ 72 + 2 @ 6 + 2 @ 2 + 2 @ 2 + 2 @ 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 2 + 2 @ 6 + 2b2 + 2b2 + 2b2 + 2b2 + 2b2 + 2b2 Ib5b2 Ib2b2b2b2b2b2b2b2b2b2 IbF2 = (92a0 + 92a1 + 92a2 + 92a3) .times.128 × 32 F7 = (− 85b0 + 72b1−48b2 + 17b3) × 6 × 32 F3 = (− 48b0−85b1−17b2 + 72b3) × 6 × 32 F5 = (72b0 + 17b1−85b2 + 48b3) × 6 × 32 Here, the ratio of each coefficient is a conventional one. Therefore, the ratios of the outputs F0 to F7 are considered to be substantially equal, but how the gain of the output changes will be considered.

Regarding the output F0, the original DCT calculation formula shows that the output F0 is 2√2 times the sum of the inputs f0 to f7, but this ratio is 23 times except for the exponent of 2. I have. The power of 2 can be ignored by shifting the timing of the capture, so multiplying 23 by 2 ^ 2 gives approximately 6
It becomes 5. Therefore, it can be seen that the gain is 65/64 times.

By performing the DCT transform using such an arithmetic expression, only 70 flip-flops (FFs) and 52 Add-units are required as the circuit configuration required for the arithmetic operation. Further, one-dimensional processing can be performed at the timing as shown in FIG. However, FIG. 5 shows the timings for F0 and F4, and the other outputs are the same for the final output but different for the output at each stage.

In practice, the above arithmetic expression is further modified as follows to form a circuit.

F0 = ((a0 + a3) × 16 + (a1 + a2) × 16) × 2 × 8 × 46 F4 = ((a0 + a3) × 16− (a1 + a2) × 16) × 2 × 8 × 46 F6 = ((a0− a3) × 40− (a1−a2) × 96) × 2 × 8 × 10 F2 = ((a0−a3) × 96 + (a1−a2) × 40) × 2 × 8 × 10 F7 = (((48 × (B1 + b2) + 68 × b3) × 2) × 2 − ((48 × (b2−b1) + 68 × b0) × 2) × 10) × 12 F3 = (((96 × b3−68 × (b1 + b2)) × 2) × 6 − ((96 × b0−68 × (b2−b1)) × 2) × 4) × 12 F5 = (((96 × b0−68 × (b2−b1)) × 2) × 6− ((96 × b3−68 × (b1 + b2)) × 2) × 4) × 12 F1 = (((48 × (b2−b1) + 68 × b0) × 2) × 2 − ((48 × (b1 + b2) +68 × b3) × 2) × 10) × 12 The operation of the configuration data conversion operation unit 50 will be described.

First, the case of DCT operation processing will be described.
Here, the adder 8 in the operation circuit 61 of the stage I is used.
1a, input data f0 and f7; adder 81b, input data f1 and f6; adder 81c, input data f2 and f5; adder 81d, input data f3 and f4; subtractor 81e, input data f3 and f4; Input data f2 and f5 are input to 81f, input data f1 and f6 are input to a subtractor 81g, and input data f0 and f7 are input to a subtractor 81h. As a result, the adder 81a outputs the addition result of the input data f0 and f7, and the adder 81b
Outputs the result of addition of the input data f1 and f6,
c outputs the addition result f2 + f5 of the input data f2 and f5,
The adder 81d outputs the result of adding the input data f3 and f4. The subtractor 81e outputs the result of subtraction of the input data f3 and f4, and the subtractor 81f outputs the subtraction result of the input data f2
And f5, the subtractor 81g outputs the subtraction result of the input data f1 and f6, and the subtractor 81h outputs the subtraction result of the input data f0 and f7. As shown in FIG. 4, the input data in this case is composed of 7-bit and 8-bit data of 1-bit sign bit. The output data is composed of 7 + 1 bits and 1 bit sign bit as shown in FIG. 5I.

Next, the operation proceeds to the operation circuit 62 of the stage II. Serial operation units 82a to 82h of the operation circuit 62
Are the addition / subtraction results a0, b0, a1, b1, a2, b2, a3, which are added or subtracted by the operation circuit 61 of the stage I.
b3 is given as input data. The computing unit 82a
Then, the DCT serial operation equation F0 = ((a0 + a3) × 16 + (a1 + a2)) when the coefficient is approximated to a simple integer ratio
× 16) × 2 × 8 × 46 and F4 = ((a0 + a3) ×
An operation of (a0 + a3) × 16 common to 16− (a1 + a2) × 16) × 2 × 8 × 46 is executed. In this case, the output (a0) of the adder 81a and the adder 8
The output (a3) of 1d is input, and these inputs are added by an adder 82a1, and the addition result is given to a shifter 82a2. From the shifter 82a2, as shown in FIG. 5I,
The output is delayed by the operation of the three flip-flops. Further, in the arithmetic unit 82b, the DCT serial arithmetic expression F0 = ((a0 + a) when the coefficient is approximated to a simple integer ratio.
3) × 16 + (a1 + a2) × 16) × 2 × 8 × 46 and F4 = ((a0 + a3) × 16− (a1 + a2) × 1
6) Execute (a1 + a2) × 16 operations common to × 2 × 8 × 46. In this case, the arithmetic unit 82b includes the adder 8
The output (a1) of 1b and the output (a2) of the adder 81c are input, and these inputs are added by the adder 82b1, and the addition result is given to the shifter 82b2. As shown in FIG. 5I, the data is output from the shifter 82b2 with a delay of three flip-flops.

In the arithmetic unit 82c, the DCT serial arithmetic expression F6 =
((A0-a3) x 40-(a1-a2) x 96) x 2 x 8
× 10 and F2 = ((a0−a3) × 96 + (a1−a
(2) × 40) × 2 × 8 × 10 (a1−a2) × 96 and (a1−a2) × 40 are executed. In this case, the output (a1) of the adder 81b and the adder 8
The output (a2) of 1c is input, and the subtracter 82c1 subtracts the output of the adder 81b from the output of the adder 81b to obtain (a1-a2). The output of the subtractor 82c1 is supplied to a shifter 82c2, the output of the first flip-flop of the shifter 82c2 and the output of the shifter 82c2 are added by an adder 82c3, and the output of the second flip-flop of the shifter 82c2 is By adding the output of the adder 82c3 by 82c4, (a1-a2) * 40
And (a1-a2) x 96 are obtained. In this case, a computing unit 82c is applied to the input data shown in FIG.
Then, the above-described operation result is generated as output data at the timing shown in FIG. Further, the computing unit 82
In the case of d, the DCT serial operation formula F6 = ((a0−a3) × 40− (a1−a) when the coefficient is approximated to a simple integer ratio.
2) × 96) × 2 × 8 × 10 and F2 = ((a0−a3)
× 96 + (a1−a2) × 40) × 2 × 8 × 10 (a0
-A3) × 40 and (a0−a3) × 96 are executed. In this case, the output (a0) of the adder 81a and the output (a3) of the adder 81d are input to the arithmetic unit 82d. a0-a3) are obtained. The output of the subtracter 82d1 is supplied to a shifter 82d2,
The output of the first flip-flop of d2 and the shifter 82
The output of d2 is added by an adder 82d3.
2d2 output of second flip-flop and adder 8
By adding the output of 2d3 by 82d4 (a0
−a3) × 40 and (a0−a3) × 96 are obtained. In this case, the arithmetic unit 82d generates the above-described calculation result as output data at the timing shown in FIG. II with respect to the input data shown as the input in FIG.

On the other hand, in the arithmetic unit 82e, the DCT serial arithmetic expression F7 =
(((48 × (b1 + b2) + 68 × b3) × 2) × 2-
((48 × (b2−b1) + 68 × b0) × 2) × 10)
× 12 and F1 = (((48 × (b2-b1) + 68 × b0)
× 2) × 2-((48 × (b1 + b2) + 68 × b3) ×
2) × 10) × 12 operation of 68 × b0 and F3 =
(((96 x b3-68 x (b1 + b2)) x 2) x 6
((96 × b0−68 × (b2−b1)) × 2) × 4) ×
12 and F5 = (((96 x b0-68 x (b2-b1)) x
2) × 6-((96 × b3−68 × (b1 + b2)) ×
2) × 4) × 12 of 96 × b0 is executed. In this case, the shifter 82e1 of the arithmetic unit 82e includes a subtractor 81
The output (b0) of e is input, the output of the third flip-flop of the shifter 82e1 is added by the adder 82e2, and the addition result is output one clock delayed by the shifter 82e3. The output of the first flip-flop and the output of the fifth flip-flop are added by an adder 82e4.
68 × b0 and 96 × b0 will be obtained. In this case, the operation unit 82
In e, the above-described operation result is generated as output data at the timing shown in FIG.

In the arithmetic unit 82f, when the coefficient is approximated to a simple integer ratio, the DCT serial arithmetic expression F7 =
(((48 × (b1 + b2) + 68 × b3) × 2) × 2-
((48 × (b2−b1) + 68 × b0) × 2) × 10)
× 12 and F1 = (((48 × (b2-b1) + 68 × b0)
× 2) × 2-((48 × (b1 + b2) + 68 × b3) ×
2) × 10) × 12 48 × (b2−b1) operation, and
F3 = (((96 × b3−68 × (b1 + b2)) × 2) ×
6-((96 × b0-68 × (b2-b1)) × 2) ×
4) × 12 and F5 = (((96 × b0−68 × (b2−b
1)) × 2) × 6-((96 × b3−68 × (b1 + b
2)) × 2) × 4) × 12 68 × (b2−b1) calculations are executed. In this case, the arithmetic unit 82f includes the subtractor 81
The output (b1) of f and the output (b2) of the subtractor 81g are input, and the output of the adder 81g is added to the adder 81 by the subtractor 82f1.
Subtraction with the output of f yields (b2-b1). The output of the subtractor 82f1 is supplied to the shifter 82f2, and the output of the second flip-flop of the shifter 82f2 and the third
The output of the flip-flop is added by the adder 82f3, and the output of the shifter 82f2 and the output of the subtractor 82f1 are added by 82f4 to obtain (b2−b1) ×
48 and (b2-b1) * 68 are obtained. In this case, the input data shown in FIG.
In 2f, the above-described operation result is generated as input data at the timing shown in FIG.

In the arithmetic unit 82g, the DCT serial arithmetic expression F7 =
(((48 × (b1 + b2) + 68 × b3) × 2) × 2-
((48 × (b2−b1) + 68 × b0) × 2) × 10)
× 12 and F1 = (((48 × (b2-b1) + 68 × b0)
× 2) × 2-((48 × (b1 + b2) + 68 × b3) ×
2) × 10) × 12 48 × (b1 + b2) operation, and
F3 = (((96 × b3−68 × (b1 + b2)) × 2) ×
6-((96 × b0-68 × (b2-b1)) × 2) ×
4) × 12 and F5 = (((96 × b0−68 × (b2−b
1)) × 2) × 6-((96 × b3−68 × (b1 + b
2)) × 2) × 4) × 12 68 × (b1 + b2) calculations are executed. In this case, the arithmetic unit 82g includes the subtractor 81
The output (b1) of f and the output (b2) of the subtractor 81g are input, and the output of the adder 81f and the adder 81 are added by the adder 82g1.
By adding the output of g, (b1 + b2) is obtained. The output of the adder 82g1 is supplied to a shifter 82g2, and the output of the second flip-flop of the shifter 82g2 and the third
The output of the flip-flop is added by the adder 82g3, and the output of the shifter 82g2 and the output of the adder 82g1 are added by 82g4 to obtain (b1 + b2) ×
48 and (b1 + b2) .times.68 are obtained. In this case, the input data shown in FIG.
In 2g, the above calculation result is generated as input data at the timing shown in FIG.

In the computing unit 82h, the DCT serial computing equation F7 =
(((48 × (b1 + b2) + 68 × b3) × 2) × 2-
((48 × (b2−b1) + 68 × b0) × 2) × 10)
× 12 and F1 = (((48 × (b2-b1) + 68 × b0)
× 2) × 2-((48 × (b1 + b2) + 68 × b3) ×
2) × 10) × 12 operation of 68 × b3 and F3 =
(((96 x b3-68 x (b1 + b2)) x 2) x 6
((96 × b0−68 × (b2−b1)) × 2) × 4) ×
12 and F5 = (((96 x b0-68 x (b2-b1)) x
2) × 6-((96 × b3−68 × (b1 + b2)) ×
2) × 4) × 12 96 × b3 calculations are executed. In this case, the shifter 82h1 of the arithmetic unit 82h has a subtractor 81
h (b3) is input, the output of the third flip-flop of the shifter 82h1 and the output of the fourth flip-flop are added by the adder 82h2,
The result of this addition is output with a delay of one clock by the shifter 82h3, and the output of the first flip-flop and the output of the fifth flip-flop of the shifter 82h1 are added by the adder 82h4. 96
× b3 is required. In this case, the arithmetic unit 82h generates the above-described calculation result as input data at the timing shown in FIG. II for the input data shown in the input of FIG.

Next, the operation proceeds to the operation circuit 63 of the stage III. The operation circuit 63 includes a stage II operation circuit 62
Are output to the adder 83a and the subtractor 83b, and similarly, the arithmetic units 82c and 82b
The output of d is given to the subtractor 83c and the adder 83d,
Further, the outputs of the calculators 82e and 82f are provided to the adder 83e and the subtractor 83f, and the outputs of the calculators 82g and 82h are provided to the subtractor 83 and the adder 83h. As a result, the adder 83a is connected to the arithmetic unit 82a of the arithmetic circuit 82 of stage II.
(A + a3) ×
16+ (a1 + a2) × 16) × 2, and the subtracter 83
b is the result of subtracting the output of the arithmetic unit 82b from the arithmetic unit 82a of the arithmetic circuit 62 of the stage II ((a0 + a3) × 16−
(A1 + a2) .times.16) .times.2, and the subtractor 83c is operated by the arithmetic unit 82c of the arithmetic circuit 62 of the stage II.
The result of subtracting the output of d ((a0−a3) × 40− (a1
−a2) × 96) × 2, and the adder 83d adds the output of the arithmetic unit 82c and the output of the arithmetic unit 82d of the arithmetic circuit 62 of the stage II ((a0−a3) × 96 + (a1−a).
2) × 40) × 2 is output. The adder 83e adds the output of the arithmetic unit 82e of the arithmetic circuit 82 of the stage II and the output of the arithmetic unit 82f (48 × (b2−b
1) + 68 × b0) × 2, and the subtracter 83f subtracts the output of the arithmetic unit 82f from the arithmetic unit 82e of the arithmetic circuit 62 of the stage II (96 × b0−68 × (b2−b)
1)) × 2, and the subtracter 83g outputs (96 × b3−68 × (b1 + b2)) × 2, which is the result of subtracting the output of the arithmetic unit 82h from the arithmetic unit 82g of the arithmetic circuit 62 of the stage II. The adder 83h adds the result (48
× (b1 + b2) + 68 × b3) × 2 is output. In this case, each of the adders 83 is applied to the input data of FIG.
a, 83d, 83e, 83h and subtractors 83b, 83
In c, 83f and 83g, the respective calculation results are output at the timing shown in FIG.

Next, the operation proceeds to the operation circuit 64 of the stage IV. In this arithmetic circuit 64, the arithmetic circuit 6 of stage III
3, the output of the adder 83a is given to the arithmetic unit 84a, the output of the subtractor 83b is given to the arithmetic unit 84b, the output of the subtracter 83c is given to the arithmetic unit 84c, and the output of the adder 83d is given to the arithmetic unit 84d. , The output of the adder 83e is the arithmetic unit 84e
The output of the subtractor 83f is supplied to the arithmetic unit 84f,
The output of g is supplied to the computing unit 84g, and the output of the adder 83h is supplied to the computing unit 84h. Thereby, the computing unit 8
4a is the output of the adder 83a of the operation circuit 63 of the stage III ((a0 + a3) × 16 + (a1 + a2) × 16) × 2
, And the result of the operation is output as output data F0. The arithmetic unit 84b is
An operation of × 8 × 46 is performed on the output ((a0 + a3) × 16− (a1 + a2) × 16) × 2 of the subtracter 83b of the operation circuit 63 of the stage III, and the operation result is output as output data F4. . Similarly, the arithmetic unit 84c outputs the output ((a0) of the subtractor 83c of the arithmetic circuit 63 of stage III.
−a3) × 40− (a1−a2) × 96) × 2 ×
An 8 × 10 operation is executed, and the operation result is output data F
Output as 6. The computing unit 84d is provided for the stage III.
Of the adder 83d of the arithmetic circuit 63 ((a0−a3) ×
An operation of × 8 × 10 is performed on 96+ (a1−a2) × 40) × 2, and the operation result is output as output data F2.

On the odd side, the operation unit 84e
The output of the adder 83e ((48 ×
(B2−b1) + 68 × b0) × 2) is input, and the output of the shifter 84e1 and the output of the adder 83e are added to the adder 84.
The output of the adder 84e2 is subtracted by the subtractor 84e3 from the output of the first flip-flop of the shifter 84h1 described later. The output of the subtractor 84e3 is provided to a shifter 84e4, the output of the subtractor 84e3 is subtracted from the output of the shifter 84e4 by a subtractor 84e5, and the operation result is output as output data F7. The output ((96 × b0−68 × (b2−b1)) × 2) of the subtractor 83f is input to the shifter 82f1 of the arithmetic unit 84f, and subtracted from the output of the first flip-flop of the shifter 84f1. The output of the adder 83f is added by an adder 84f2. The output of the shifter 84f1 is subtracted from the output of an adder 84g2 described later by the subtracter 84f3. The output of the subtractor 84f3 is provided to a shifter 84f4.
The output of the subtracter 84f3 is subtracted from the output of the shifter 84f4 by the subtractor 84f5, and the operation result is output as output data F3. The shifter 82 of the arithmetic unit 84g
The output of the subtracter 83g ((96 × b3−68 × (b
1 + b2)) × 2) is input, and the output of the first flip-flop of the shifter 84g1 and the output of the subtractor 83g are added by the adder 84g2. The output of the adder 84f2 and the output of the shifter 84g1 are combined with the output of the adder 84g3.
Add with The output of the adder 84g3 is provided to a shifter 84g4, the output of the adder 84g3 is subtracted from the output of the shifter 84g4 by a subtractor 84g5, and the operation result is output as output data F5. The output of the adder 83h ((48 × (b1 +
b2) + 68 × b3) × 2) are input and the shifter 84
The output of h1 and the output of adder 83h are added by adder 84h2, and the output of the first flip-flop of shifter 84e1 and the output of adder 84h2 are added to adder 84h3.
Subtract with. The output of the adder 84h3 is provided to a shifter 84h4, the output of the adder 84h3 is subtracted from the output of the shifter 84h4 by a subtractor 84h5, and the operation result is output as output data F1. In this case, the above stage I
The arithmetic units 84a to 84h of the V arithmetic circuit 64 execute a serial operation on the input data of FIG. 5 and generate the operation results as output data F0 to F7 at the timing shown in FIG. .

The above description is for the DCT operation, but the inverse DCT operation is the same as described above.

In this case, the input data is supplied in the order of the stage IV operation circuit 64 to the stage I operation circuit 61.

FIG. 5 is a timing chart from the input to the output of the data conversion operation device 50, and shows a timing chart when the operations of the operation circuits 61 of the stage I to the operation circuit 64 of the stage IV are integrated. In the present embodiment, the operation coefficient of the DCT is replaced with an integer value without being considered to be a power of 2, and the change in the gain is absorbed by the quantization device 51, thereby significantly increasing the circuit scale as shown in FIG. When 8-bit data is input, the processing cycle per line can be reduced to 21 clocks.

Note that the above example is a one-dimensional case, and a two-dimensional case of pixels or the like is realized by performing this processing twice vertically and horizontally.

Operation in Data Conversion Operation Device 90 (FIGS. 7 and 8) The basic operation of the data conversion operation device 90 is the same as that of the data conversion operation device 50 shown in FIG.
~ III, and the odd side of stage II is DC
Serial circuit 1 with T arithmetic expression as hardware
00, the operation of this part is different. First, the operation of the serial circuit 100 will be described, and then the overall operation of the data conversion operation device 90 will be described.

As for the operation within the broken line of the data conversion operation device 50 of FIG. 6, consider the input as b0 to b3 and the output as x0 to x3. The calculation within the broken line in FIG.

X0 = 32 × (−85b0 + 72b1−48b2 + 17b3) x1 = 32 × (−48b0−85b1−17b2 + 72b3) x2 = 32 × (72b0−17b1 + 85b2 + 48b3) x3 = 32 × (17b0 + 48b1 + 72b2 + 3x0, x3 = 32x3) For each input b0-b3,
It can be seen that it is obtained by addition and subtraction of values multiplied by certain numerical values of 17, 48, 72 and 85. In this case, as shown in the above equation, when the conventional serial operation is performed, the addition / subtraction and the butterfly operation are used. As a result, there is a redundancy of 5 stages of flip-flops (FF) with 32 = 25.

The serial circuit 100 shown in FIG. 8 is a circuit whose speed is increased while the ratios of the coefficients 17, 48, 72 and 85 in the above equation remain the same.

In the serial circuit 100 of the data conversion / calculation device 90 shown in FIG.
Think about it. With the circuit configuration shown in FIG. 8, each of the outputs x0 to x3 is represented by the following equation.

X0 = 4 × (−85b0 + 72b1−48b2 + 17b3) x1 = 4 × (−48b0−85b1−17b2 + 72b3) x2 = 4 × (72b0−17b1 + 85b2 + 48b3) x3 = 4 × (17b0 + 48b1 + 72b2 + 45) / 32 = 1/8 = 2-3 times different. That is, it can be seen that 2-3 to 3 clocks are output faster than the conventional one. Here, since only the inside of the broken line has been speeded up, the output timings and gains are different from those of the even-numbered components F0, F2, F4, F6. Therefore, unnecessary shift registers have been removed from the even-numbered components in order to make the timings and the gains uniform. FIG. 8 is a configuration diagram. The timing chart at that time is shown in FIG.

Hereinafter, the operation of the serial circuit 100 in which the above-described arithmetic expression is directly converted into hardware will be described.

Referring to FIG. 8, the serial operation unit 1 of the serial
The operation circuit 9 of the stage I of FIG.
The subtraction result b0, b1, b2, b3 obtained by subtracting 1 is given as input data, and a part of the numerical value when a coefficient common to the respective inputs b0 to b3 is expressed by multiplying the numerical value by a power of 2 Is calculated. That is, the serial computing unit 101
In e, when the input b0 is input, each of the inputs b0 to b0 is shifted or shifted and added.
When the coefficients 17, 85, 48, and 72 common to b3 are expressed by multiplying them by a power of 2 (2, 42, 6, and 18 in this embodiment), a portion of the numerical value is created. . In this case, assuming that the coefficients 17, 85, 48, and 72 common to the respective inputs are obtained by expanding the DCT operation equation as shown in the above equation, the coefficient 17 as described in the principle explanation (II) of FIG.
Is 16 + 1, coefficient 85 is 42 × 21 + 1, coefficient 48 is 6
× 23 and the coefficient 72 are expressed as 18 × 22.
The portions 2, 6, and 18 (see the numerical values in the broken lines in FIG. 1) are calculated by the serial calculator 101e. As a result, "2" output from the first flip-flop of the shifter 101e1 of the serial operation unit 101e with a delay of one flip-flop is output from the input b0 and the shifter 101e1.
The adder 101e5 to "42" adds the output of the first flip-flop of e1 and the adder 101e2 to "6" adds the input b0 and the output of the first flip-flop of the shifter 101e1.
However, by adding the input b0 and the output of the shifter 101e1, "18" is output from the adder 101e3. Similarly, the serial computing unit 101f
Then, the input b1 is shifted or shift-added, so that the shifter 101f1 of the serial operation unit 101f is shifted.
"2" from the first flip-flop of the input b0
And the output of the adder 101e4.
"42" is output from f5, "6" is output from adders 101f2, and "18" is output from adders 101f3. Further, in the serial arithmetic unit 101g, the input b2 is shifted or shift-added,
"2" is output from the first flip-flop of the shifter 101g1 of the serial arithmetic unit 101g, "42" is output from the adder 101g5, "6" is output from the adder 101g2, and "18" is output from the adder 101g3. That is, in the serial operation unit 101h, the input b3 is shifted or shift-added, so that "2" is output from the first flip-flop of the shifter 101h1 of the serial operation unit 101h, and "42" is output from the adder 101h5.
However, "6" is output from the adder 101h2, and "18" is output from the adder 101h3.

Numerical value “2” corresponding to the coefficient of the DCT calculation formula calculated by the serial calculators 101e to 101h,
“42”, “6”, and “18” are input to the serial operators 102 e to 102 h of the serial circuit 102 constituting the latter part of the serial circuit 100,
2e to 102h are serial operation units 101e to 101h
Are successively added and subtracted in the horizontal direction of the DCT operation expression including the sign to the coefficient outputs calculated by
Output as In this case, the coefficients 17, 85, 4
When 8 and 72 are expressed in a form obtained by multiplying a numerical value by a power of 2, the power of 2 is calculated by each of the serial arithmetic units 102e to 102e.
The coefficient is adjusted by the input position to the 2h adder / subtracter, and the coefficients 17, 8 for the reason explained in the principle explanation (II).
5, 48 and 72 are basically odd numbers (coefficient 1
7, 85) is performed first.

In the serial operation unit 102e, the DCT
Serial operation expression x3 = 4 × (17b0 + 48b1 + 72b2 + 85b) when the operation expression is directly converted into hardware
Perform 3). In this case, the output of the adder 101f2 of the serial calculator 101f and the output of the first flip-flop of the shifter 101e1 of the serial calculator 101e are input to the adder 102e1 of the serial calculator 102e. These inputs are added, the output of the adder 102e1 and the output of the adder 101g3 of the serial calculator 101g are added by the adder 102e2, and the output of the adder 102e2 and the output of the adder 101h5 of the serial calculator 101h are added. The output of the adder 102e3 and the input b3 are added by the adder 102e4. The output of the adder 102e4 and the output of the first flip-flop of the shifter 101e1 of the serial operation unit 101e are added to the adder 102e5. The output x3 is obtained by adding.

Further, in the serial computing unit 102f,
Serial operation expression x2 = 4 × (72b0-17b1 + 85b2 + 4) when DCT operation expression is directly converted to hardware
8b3) is executed. In this case, the serial operator 102
The output of the adder 101h2 of the serial calculator 101h and the output of the first flip-flop of the shifter 101f1 of the serial calculator 101f are input to the subtractor 102f1 of f. The output of the first flip-flop of the shifter 101f1 is subtracted, and the output of the subtractor 102f1 and the output of the adder 101e3 of the serial operation unit 101e are added to the adder 10
The output of the adder 102f2 and the output of the adder 101g5 of the serial operation unit 101g are added to the adder 10f2.
2f3, the output of the adder 102f3 and the input b2
Is added by the adder 102f4, and the output of the first flip-flop of the shifter 101f1 of the serial operation unit 101f is subtracted from the output of the adder 102f4 by the subtractor 102f5 to obtain the output x2.

In the above-mentioned serial operation unit 102g,
Serial operation expression x1 = 4 × (−48b0−85b1−17b2 +) when the DCT expression is directly converted to hardware
72b3) Execute. In this case, the serial operator 102
The output of the adder 101e2 of the serial arithmetic unit 101e and the output of the first flip-flop of the shifter 101g1 of the serial arithmetic unit 101g are input to the adder 102g1 of g, and the adder 102g1 adds these inputs.
Next, the output of the adder 102g1 is subtracted from the output of the adder 101h3 of the serial operator 101h by the subtracter 102g2, and the serial operator 1 is subtracted from the output of the subtractor 102g2.
The output of the adder 101f5 of 01f is subtracted by the subtractor 102g3, the input b1 is subtracted from the output of the subtractor 102g3 by the subtractor 102g4, and the output of the subtracter 102g4 is used as the first shifter 101g1 of the serial calculator 101g. Is subtracted by the subtractor 102g5 to obtain the output x1.

Further, in the serial computing unit 102h,
Serial operation expression x0 = 4 × (−85b0 + 72b1−48b2 +) when the DCT expression is directly converted to hardware
17b3) Execute. In this case, the serial operator 102
The output of the first flip-flop of the shifter 101h1 of the serial calculator 101h and the output of the adder 101g2 of the serial calculator 101g are input to the subtractor 102h1 of h.
The output of the adder 101g2 is subtracted from the output of the flip-flop, and the output of the subtracter 102h1 and the output of the adder 101f3 of the serial operation unit 101f are added to the adder 10
2h2, and the output of the adder 101e5 of the serial calculator 101e is subtracted from the output of the adder 102h2 by the subtractor 1
02h3, the input b0 is subtracted from the output of the subtractor 102h3 by a subtractor 102h4.
And the output of the first flip-flop of the shifter 101h1 of the serial operation unit 101h is added to the adder 102h5.
The output x0 is obtained by adding

In the case of the serial operation, the serial operation units 102e to 102h output respective operation results at the timing shown in FIG.

The operation of the data conversion operation device 90 including the serial circuit 100 will be described below.

First, the case of DCT calculation processing will be described.
Here, the adder 8 is used in the operation circuit 91 of the stage I.
1a, input data f0 and f7; adder 81b, input data f3 and f4; adder 81c, input data f1 and f6; adder 81d, input data f2 and f5; subtractor 81e, input data f0 and f7; Input data f3 and f4 are input to 81f, input data f1 and f6 are input to the subtractor 81g, and input data f2 and f5 are input to the subtractor 81h. As a result, the adder 81a outputs the addition result of the input data f0 and f7, and the adder 81b
Outputs an addition result of the input data f3 and f4,
c outputs the addition result f1 + f6 of the input data f1 and f6,
The adder 81d outputs the result of adding the input data f2 and f5. The subtractor 81e outputs the result of subtraction of the input data f0 and f7, and the subtractor 81f outputs the result of the input data f3
And f4, the subtractor 81g outputs the subtraction result of the input data f1 and f6, and the subtractor 81h outputs the subtraction result of the input data f2 and f5. As shown in FIG. 10, the input data in this case is composed of 7-bit and 8-bit data of 1-bit sign bit. The output data is composed of 7 + 1 bits and 1 bit sign bit as shown in FIG. 10I.

Next, the operation proceeds to the stage II arithmetic circuit 92. The even side serial operation unit 9 of the operation circuit 92
The addition results a0, a1, a2, and a3 added by the operation circuit 91 of the stage I are given as input data to 2a to 92d, and subtracted by the operation circuit 91 of the stage I to the odd-side serial circuit 100. Subtraction results b0, b1, b
2, b3 are given as input data. The computing unit 92
In a, the DCT serial operation formula F0 = (92a0 + 92a1 + 92a2 + 92) when the coefficient is approximated to a simple integer ratio.
a3) Perform the operation in parentheses of × 128. in this case,
Adder 82a forming the front stage of serial operation unit 92a
1 is supplied with the output of the adder 81a and the output of the adder 81d. The input data is added by the adder 82a1, and the addition result is given to the shifter 82a2. In the serial computing unit 92b, the DCT serial computing equation F4 = (92
a0−92a1−92a2 + 92a3) × 128. In this case, the output of the adder 81b and the output of the adder 81c are input to the arithmetic unit 92b, which constitutes the former stage of the serial arithmetic unit 92b, and the input data is added by the adder 82b1. Shifter 82
b2. As a result, the shifter 82a2 and the shifter 82b2 output the data with a delay of three flip-flops. In the serial computing unit 92c, the DCT serial computing equation F6 = (25a0 + 60a1-60) when the coefficient is approximated to a simple integer ratio.
a2-25a3) Perform the operation in parentheses of 128. In this case, the output of the adder 81b and the output of the adder 81c are input to the arithmetic unit 82c which constitutes the former stage of the serial arithmetic unit 92c, and the output of the adder 81b is output by the subtractor 82c1 to the output of the adder 81c. (A1-a2) is obtained by subtracting. The output of the subtractor 82c1 is supplied to a shifter 82c2, the output of the first flip-flop of the shifter 82c2 and the output of the shifter 82c2 are added by an adder 82c3, and the output of the second flip-flop of the shifter 82c2 By adding the output of the adder 82c3 and the output of the adder 82c3, "25" and "60" are obtained. In the serial computing unit 92d, the DCT serial computing equation F2 = (60a0 + 25a1-25a2-60a3) × 1 when the coefficient is approximated to a simple integer ratio.
Perform the operation in parentheses at 28. In this case, the output of the adder 81a and the output of the adder 81d are input to the arithmetic unit 82d, which constitutes the former stage of the serial arithmetic unit 92d, and the output of the adder 81a is output from the adder 81d by the subtractor 82d1. (A0-a3) is obtained by subtraction. The output of the subtracter 82d1 is supplied to a shifter 82d2,
The output of the first flip-flop of d2 and the shifter 82
Addition of the output of d2 by the adder 82d3, and addition of the output of the second flip-flop of the shifter 82d2 and the output of the adder 82d3 by the adder 82d4 yields "60" and "25". become.

Next, the arithmetic results obtained by the arithmetic units 82a to 82d are given to an adder / subtractor constituting the subsequent stage of the serial arithmetic units 92a to 92d. Specifically, the outputs of the arithmetic units 82a and 82b are added to the adder 83a and the subtractor 83
b and the outputs of the arithmetic units 82c and 82d
3c and an adder 83d.
e and 82f are output to an adder 83e and a subtractor 83f,
The outputs of the arithmetic units 82g and 82h are the subtractor 83 and the adder 8
3h. As a result, the adder 83a adds the output of the arithmetic unit 82a and the output of the arithmetic unit 82b (92a
0 + 92a1 + 92a2 + 92a3), and the subtracter 83
b outputs the result (92a0-92a1-92a2 + 92a3) obtained by subtracting the output of the arithmetic unit 82b from the arithmetic unit 82a, and the subtracter 83c subtracts the output of the arithmetic unit 82d from the arithmetic unit 82c (25a0 + 60a1-60a2-). 2
5a3), and the adder 83d adds the output of the arithmetic unit 82c and the output of the arithmetic unit 82d (60a0 + 25a1−).
25a2-60a3). in this case,
Arithmetic devices 83a to 83a to input data shown in the input of FIG.
At 83h, the above calculation result is generated as output data at the timing shown in FIG.

The odd of the operation circuit 92 of the stage II
The operation of the serial circuit 100 constituting the side has been described above.

Next, the operation proceeds to the operation circuit 93 of the stage III. The operation circuit 93 includes a stage II operation circuit 92
The output of the adder 83a is given to the computing unit 93a, and the output of the subtractor 83b is similarly supplied to the computing unit 93b,
The output of 3c is output to the operator 93c, the output of the adder 83d is output to the operator 93d, the output x0 of the serial circuit 100 is output to the operator 93e, and the output x1 of the serial circuit 100 is output to the operator 93d.
f, the output x2 of the serial circuit 100 is the arithmetic unit 93g
The output x3 of the serial circuit 100 is supplied to the arithmetic unit 93h. As a result, the arithmetic unit 93a outputs the output (92a0) of the adder 83a of the arithmetic circuit 92 of stage II.
+ 128a1 + 92a2 + 92a3) is executed, a gain 128 of the output F0 is given, and the operation result is output as output data F0. The arithmetic unit 9
3b is a value obtained by multiplying the output (92a0-92a1-92a2 + 92a3) of the subtractor 83b of the stage II arithmetic circuit 92 by x.
A calculation of 128 is executed, a gain 128 of the output F4 is given, and the calculation result is output as output data F4. Similarly, the operation unit 93c outputs the output (25a0 + 60a1-60a2-25) of the subtractor 83c of the operation circuit 92 of stage II.
A calculation of x128 is performed on a3), a gain 128 of the output F6 is given, and the calculation result is output as output data F6. The arithmetic unit 93d outputs the output (60a0 + 25a1-25) of the adder 83d of the stage II arithmetic circuit 92.
a2−60a3), a calculation of × 128 is performed, a gain 128 of the output F2 is given, and the calculation result is output as output data F2.

On the odd side, a computing unit 93e
The shifter 84e4 and the subtractor 84e5 perform a × 32 operation on the output x0 of the serial circuit 100 of the stage II to give a gain 32 of the output F7, and output the calculation result as output data F7. Further, the shifter 84f4 and the subtractor 84f5 of the arithmetic unit 93f execute a × 32 operation on the output x1 of the serial circuit 100 of the stage II to give a gain 32 of the output F3, and the calculation result is output data F3. Output. Similarly, the shifter 84g4 and the subtractor 84g5 of the operation unit 93g execute the operation of x32 on the output x2 of the serial circuit 100 of the stage II to give the gain 32 of the output F5, and output the operation result to the output data F5 Output as The shifter 8 of the arithmetic unit 93h
The 4h4 and the subtractor 84h5 execute a × 32 operation on the output x3 of the stage II serial circuit 100 to give a gain 32 of the output F1, and output the operation result to the output data F1
Output as In this case, each of the arithmetic units 93a to 93h of the arithmetic circuit 93 of the stage III executes a serial operation on the input data of FIG. 10 and outputs the arithmetic result as output data F0 to F7 at the timing shown in FIG. Will occur.

The above description is for the DCT operation, but the inverse DCT operation is the same as described above.

In this case, the input data is provided in the order of the stage III arithmetic circuit 93 to the stage I arithmetic circuit 91.

FIG. 10 is a timing chart from the input to the output of the data conversion operation device 90.
3 shows a timing chart when the operations of the arithmetic circuits 91 to 93 of the stage III are integrated. In the present embodiment, the coefficients are divided so that a common coefficient appears in each input by expanding the DCT arithmetic expression, and the expanded DCT arithmetic expression is directly implemented in hardware without being bound by the butterfly operation. When the shift register provided for adjusting the timing and the gain can be removed from the even-numbered component side, and 7-bit data is input as apparent from the timing chart of the data conversion operation device 50 shown in FIG. The processing cycle per line can be reduced from 26 clocks to 23 clocks.

As described above, the data compression / decompression device of this embodiment includes a data storage device 10 for storing image data in the form of parallel data, and a parallel data conversion device for converting parallel data read from the data storage device 10 into serial data. A serial conversion device 11 and a serial circuit in which a DCT operation coefficient is changed to a simple integer ratio, and the odd side is configured to include a serial circuit 100 in which the operation expression is directly converted into hardware; A data conversion operation device 90 that performs one-dimensional DCT operation on the data output from the parallel-serial conversion device 11 in the form of a serial operation, and converts serial DCT operation serial data into parallel data and stores the data Serial-to-parallel converter 13 for writing to device 10
Then, the data after the data conversion operation stored in the data storage device 10 is divided by the value of the quantization table configured to absorb the gain change caused by changing the DCT operation coefficient to an integer ratio. And a control device 52 for controlling the operation of each of the above components by controlling the entire data compression / decompression device.
The serial circuit 100 generates a part of a numerical value when a coefficient common to each input b0 to b3 obtained by expanding a DCT operation expression is multiplied by a power of two. And a serial circuit 102 that performs addition and subtraction including a code portion in the horizontal direction of the equation with respect to the coefficient output calculated by the serial circuit 101 and outputs the result as outputs x0 to x3. By using hardware, the butterfly operation unit can be eliminated, the number of stages such as FFs can be reduced, and the number of clocks (time) can be reduced. That is, FIG.
In the case of the circuit configuration of the conventional data conversion operation device 12 shown in FIG. 2, when 8-bit data is input, as shown in FIG.
Although it took 26 clocks from the SB input to the MSB output, the data conversion operation device 90 shown in FIG.
By using the serial circuit 100 on the odd side, it is possible to remove three stages of shift registers provided for equalizing the timing and the gain from the even-numbered component side, and compare with the timing chart of the data conversion operation device 50 shown in FIG. As is clear from the above, when 7-bit data is input, the processing cycle per line can be reduced from 26 clocks to 23 clocks. As a result, there is an advantage that the data conversion operation can be performed with a small number of clocks, and the data conversion operation can be used for data compression such as image compression.

The data compression / decompression device of this embodiment is
A data storage device 10 for storing image data in the form of parallel data, a parallel-serial conversion device 11 for converting parallel data read from the data storage device 10 into serial data, and a DCT operation coefficient changed to a simple integer ratio. And a data conversion operation device 50 configured to perform a one-dimensional DCT operation on the data output from the parallel-serial conversion device 11 in the form of a serial operation. This is caused by changing the DCT operation coefficient to an integer ratio between the serial-parallel conversion device 13 that converts the data into parallel data and writes the data into the data storage device 10 and the data after the data conversion operation stored in the data storage device 10. Divide by the value of the quantization table configured to absorb the gain change And a control unit 52 for controlling the operation of each unit described above by controlling the whole of the data compression / decompression device. A part that can be expressed by a power of 2 is expressed by a power and a serial circuit is formed. On the other hand, in the configuration, the portion where the number of bits is increased by exponentiation is dare not expressed by exponentiation, and the coefficient of the DCT arithmetic expression is replaced by an integer ratio without being restricted to exponentiation of 2. Since the variation is absorbed by the quantization unit, the circuit scale of the data conversion operation device 50 can be significantly reduced and the number of serial stages can be reduced as compared with the case where a serial circuit is simply realized. As a result, the processing speed can be improved. In other words, the conventional example shown in FIG. 22 requires 126 flip-flops (FF) and 62 1-bit Add (Sub) units, and the circuit scale is still large. (F
F) Only 70 units and 1 Add unit are required, so that the circuit scale can be significantly reduced. Further, since the number of stages of flip-flops (FFs) constituting the serial circuit is reduced, when 8-bit data is input as shown in FIG. 5, the processing cycle per line is set to 27 clocks of the conventional example (FIG. 26). ) To 21 clocks. Further, the operation using the coefficient including the error is performed only once in the quantization device 51, and most of the operation can be performed based on the ratio of integers including no error, and the data bit width in the operation before the quantization is performed. Can be made much smaller than conventional ones, and a high calculation accuracy can be obtained with a small bus width. Further, since the data conversion operation device 50 itself performs the DCT operation using a serial circuit composed of a combination of extremely small FFs and the like, the circuit scale can be significantly reduced and high-speed processing can be performed. Will be possible.

Since a data compression / decompression device having a high calculation accuracy and a small circuit scale can be realized,
It is suitable for application to a data compression / decompression device that performs image compression or audio compression using CT.

In this embodiment, an example is shown in which the serial circuit 100 is applied to the odd side of the stage II of the data conversion operation device 90. However, the present invention is not limited to this. It goes without saying that the present invention may be applied to any circuit portion as long as it is developed and forms a serial circuit according to the developed expression.

Further, in this embodiment, an example is shown in which the coefficient is, for example, a ratio of a predetermined integer. However, the present invention is not limited to this, and any integer ratio may be used as long as it is expressed by the ratio of integers. It goes without saying that even an integer value is used.

Further, the operation coefficient is expressed by the sum (difference) of a power of 2 (2 to the power of n) and the operation is performed by a serial circuit as shown in FIG. 3, but the serial data processing is performed. Of course, any combination of units may be used.

Further, it goes without saying that the number and types of circuits and members constituting the image compression apparatus and the like are not limited to those in the above-described embodiment, and software (for example, C language) may be used.
May be realized.

Further, in this embodiment, DCT is applied to the data conversion operation device. However, the present invention is not limited to these encoding methods, and any device or operation expression that performs the encoding operation can be used. Needless to say, this can also be applied. For example, Harr transformation, slope transformation (slant transformation),
The present invention can be applied to a data compression / decompression device using symmetric sine transform or the like.

The type of data conversion is not limited as long as data conversion is performed on input data.
In addition to the conversion of frequency components by CT, for example, FFT, L
OT (Lapped Orthogonal Transform)
And so on. Further, although the coefficients of the data conversion operation unit are absorbed by the quantization unit, it is needless to say that any quantization unit may be used as long as the coefficients can be adjusted.

[0145]

According to the first aspect of the present invention, a data storage means for storing predetermined data, and a data conversion operation based on a predetermined coefficient based on a predetermined coefficient for the data output from the data storage means. , A quantization unit that performs a quantization operation on the data after the data conversion by the data conversion operation unit, the data storage unit, the data conversion operation unit, and the quantization unit. A data compression / expansion device comprising control means for controlling, wherein the data conversion operation expression of the data conversion operation means is expanded, and the data conversion operation means is configured according to the expanded expression. The number of clocks can be reduced by reducing the number of stages of serial circuits such as registers, and the processing speed can be improved.

Further, claims 2, 3, 4, 5, 6, 7,
According to the inventions described in 8, 9, 10, 11, 12, 13, 14 and 15, the data storage means for storing the predetermined data, and the data output from the data storage means have a predetermined coefficient. A data conversion operation unit for performing a data conversion operation by serial operation based on the data conversion unit; a quantization unit for performing a quantization operation on the data after the data conversion by the data conversion operation unit; the data storage unit; What is claimed is: 1. A data compression / decompression device comprising an arithmetic unit and a control unit for controlling said quantization unit, wherein a gain generated by replacing a coefficient of said data conversion arithmetic unit with an integer ratio and replacing said coefficient with said integer ratio. Is adjusted by the quantization means, a data conversion operation expression is developed, and the data conversion operation means is constructed in accordance with the developed expression. So that the circuit scale can be significantly reduced as compared to the case where a serial circuit is simply realized, and the processing speed can be improved by reducing the number of serial stages, and the Can be used for data compression.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a data compression / decompression device.

FIG. 2 is a block diagram of a data compression / decompression device.

FIG. 3 is a block diagram of a data conversion operation device of the data compression / decompression device.

FIG. 4 is a circuit configuration diagram of a data conversion operation device of the data compression / decompression device.

FIG. 5 is a timing chart for explaining the operation of the data conversion operation device of the data compression / decompression device.

FIG. 6 is a circuit configuration diagram of a data conversion operation device of the data compression / decompression device.

FIG. 7 is a circuit configuration diagram of a data conversion operation device of the data compression / decompression device.

FIG. 8 is a circuit configuration diagram of a serial circuit of a data conversion operation device of the data compression / decompression device.

FIG. 9 is a timing chart for explaining the operation of the data conversion operation device of the data compression / decompression device.

FIG. 10 is a timing chart for explaining the operation of the data conversion operation device of the data compression / decompression device.

FIG. 11 is a block diagram of a conventional data compression / decompression device.

FIG. 12 is a diagram for explaining processing of image data by a conventional data compression / decompression device.

FIG. 13 is a diagram showing an example of a quantization table of a conventional data compression / decompression device.

FIG. 14 is a diagram for explaining a serial operation in a data conversion operation device of a conventional data compression / decompression device.

FIG. 15 is a diagram for explaining a serial operation in a data conversion operation device of a conventional data compression / expansion device.

FIG. 16 is a diagram for explaining a serial operation in a data conversion operation device of a conventional data compression / expansion device.

FIG. 17 is a block diagram of a data conversion operation device of a conventional data compression / decompression device.

FIG. 18 is a circuit configuration diagram of an I stage of a data conversion operation device of a conventional data compression / decompression device.

FIG. 19 is a circuit configuration diagram of an II stage of a data conversion operation device of a conventional data compression / decompression device.

FIG. 20 is a circuit configuration diagram of a stage III of a data conversion operation device of a conventional data compression / decompression device.

FIG. 21 is a circuit configuration diagram of an IV stage of a data conversion operation device of a conventional data compression / decompression device.

FIG. 22 is a circuit configuration diagram of a data conversion operation device of a conventional data compression / decompression device.

FIG. 23 is a diagram illustrating a serial operation element of a conventional data compression / decompression device.

FIG. 24 is a diagram illustrating a serial operation element of a conventional data compression / decompression device.

FIG. 25 is a diagram illustrating a serial operation element of a conventional data compression / decompression device.

FIG. 26 is a timing chart for explaining an operation of a data conversion operation device of a conventional data compression / decompression device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 data storage device 11 parallel-serial conversion device 13 serial-parallel conversion device 51 quantizer 50, 90 data conversion operation device 52 control device 91 operation circuit of stage I 92 operation circuit of stage II 93 operation circuit of stage III 100 Serial circuit 101 Serial circuit (first serial operation unit) 102 Serial circuit (second serial operation unit)

(Equation 3)

(Equation 4)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-222121 (JP, A) JP-A-4-222122 (JP, A) JP-A-1-276980 (JP, A) JP-A-2-222 105792 (JP, A) "Application of Digital Signal Processing", May 1981, published by The Institute of Electronics and Communication Engineers, edited by Inoue et al., Pp. 61-64 (58) Fields studied (Int. Cl. ⁷ , DB Name) H03M 7/30 H03M 9/00

Claims (15)

(57) [Claims] A data storage unit for storing predetermined data; a data conversion operation unit for performing a data conversion operation on the data output from the data storage unit by a serial operation based on a predetermined coefficient; Data comprising: a quantizing means for performing a quantization operation on data after data conversion by the data conversion operation means; and a control means for controlling the data storage means, the data conversion operation means, and the quantization means. A compression / decompression device, which expands a data conversion operation expression of the data conversion operation means,
A data compression / decompression device wherein the data conversion operation means is configured in accordance with an expanded expression. 2. A data storage means for storing predetermined data, a data conversion operation means for performing a data conversion operation by serial operation based on a predetermined coefficient on data output from the data storage means, Data comprising: a quantizing means for performing a quantization operation on data after data conversion by the data conversion operation means; and a control means for controlling the data storage means, the data conversion operation means, and the quantization means. A compression / decompression device, wherein a coefficient of the data conversion operation means is replaced with an integer ratio,
The change in gain caused by replacing the ratio of the integers is adjusted by the quantization means, a data conversion operation expression is developed, and the data conversion operation means is configured according to the expanded expression. A data compression / decompression device characterized by the above-mentioned. 3. A data storage means for storing predetermined data; a parallel-serial conversion means for converting data in the data storage means from parallel data to serial data; and a data output from the parallel-serial conversion means. A data conversion operation unit for performing a data conversion operation by a serial operation based on a predetermined coefficient, and a serial-parallel conversion for converting serial data output from the data conversion unit into parallel data and writing the data into the data storage unit Means, a quantization means for performing a quantization operation on the data after the data conversion by the data conversion operation means, the data storage means, the parallel-serial conversion means, the data conversion operation means, the serial-parallel. Conversion means and control means for controlling the quantization means. Example was a data compressing and expanding apparatus, replacing the coefficient of the data conversion operation means the ratio of integers,
The change in gain caused by replacing the ratio of the integers is adjusted by the quantization means, a data conversion operation expression is developed, and the data conversion operation means is configured according to the expanded expression. A data compression / decompression device characterized by the above-mentioned. 4. A data storage means for storing predetermined data, a data conversion operation means for performing a data conversion operation by serial operation on data outputted from the data storage means based on a predetermined coefficient, Data comprising: a quantizing means for performing a quantization operation on data after data conversion by the data conversion operation means; and a control means for controlling the data storage means, the data conversion operation means, and the quantization means. A compression / expansion device, wherein a value of a coefficient of a data conversion operation expression of the data conversion operation means is expressed by a power of 2, and a bit number greater than a predetermined value when the value of the coefficient is expressed by a power of 2 The coefficient is replaced by an integer ratio, and a change in gain caused by replacing the integer ratio is adjusted by the quantization means. Rutotomoni, expand the data conversion arithmetic expression, the data compressing and expanding apparatus being characterized in that so as to constitute the data converting operation means according to the expanded expressions. 5. A first serial operation section for expanding a data conversion operation expression so that a predetermined coefficient appears at each input and serially operating a coefficient portion of the expanded data conversion operation expression. And a second serial operation unit for adding and subtracting the output of the first serial operation unit and executing the operation of the expanded data conversion operation expression. Claim 3 or Claim 4
The data compression / decompression device according to any one of the above. 6. The first serial operation unit expresses a coefficient of the expanded data conversion operation expression by a power of 2 and multiplies the coefficient by a power of 2. 6. The data compression / decompression apparatus according to claim 5, wherein a numerical part represented by the following equation is constituted by a serial circuit that performs a serial operation. 7. The first serial operation unit includes:
And a plurality of adder / subtracters for adding and subtracting the numerical value output from the serial operation unit and outputting the result, wherein the coefficient of the expanded data conversion operation expression is expressed by a power of 2 multiplied by 2 6. The data compression / decompression device according to claim 5, wherein the portion is adjusted by an input position to each of the adders / subtracters. 8. The data processing apparatus according to claim 1, wherein said data conversion operation means is an orthogonal transformation means for executing orthogonal transformation by serial operation on data. The data compression / decompression device according to any one of the above. 9. The data conversion operation unit according to claim 1, wherein the data conversion operation unit is a discrete cosine transform unit that performs a discrete cosine transform (DCT) on the data by a serial operation. A data compression / decompression device according to claim 4. 10. The data conversion operation means according to claim 1, further comprising a serial operation device for sequentially moving input data in response to a predetermined clock. The data compression / decompression device according to claim 3 or 4. 11. The data conversion operation means is constituted by a serial circuit in which the value of a coefficient of the data conversion operation expression is expressed by a power of 2, and the data conversion operation is executed by serial operation by the serial circuit. The data compression / decompression device according to any one of claims 1, 2, 3, and 4, wherein 12. The data conversion operation means expresses a value of a coefficient of the data conversion operation expression by a power of 2 and a part in which the number of bits is larger than a predetermined value when the value of the coefficient is expressed by a power of 2. 5. The data processing method according to claim 2, wherein the serial circuit comprises a serial circuit in which the coefficient is replaced by an integer ratio, and performs a data conversion operation by a serial operation performed by the serial circuit. A data compression / decompression device according to any of the claims. 13. A data conversion operation expression used by said data conversion operation means is prepared so that coefficients of said data conversion operation expression are included in quantization coefficients used for quantization operation of said quantization means. Claims 2 and 3
A data compression / decompression device according to claim 4. 14. The gain adjustment by the quantization means is performed by a quantization table configured to absorb a gain change caused by changing a coefficient of the data conversion operation means to an integer ratio. The data compression / decompression device according to claim 2, wherein 15. The data conversion operation means according to claim 2, wherein said coefficient is replaced with an integer ratio by replacing said coefficient with an integer value. 15. The data compression / decompression device according to claim 12 or claim 14.