JP3089377B2 - Normalized floating point multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a normalized floating-point multiplication circuit for multiplying digitally normalized floating-point signals of two's complement format.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional normalized floating point multiplication circuit.

The conventional normalized floating point multiplication circuit shown in FIG. 1 comprises a normalized two's complement floating point signal comprising a mantissa part (including a sign) 101 and an exponent part 103, and a mantissa part. (Including a sign) 102 and an exponent 104 are multiplied with a normalized two's complement floating point signal.

As shown in FIG. 1, a conventional normalized floating-point multiplication circuit includes a multiplication circuit 1 for multiplying a mantissa part 101 input as a multiplier and a mantissa part 102 input as a multiplicand, and an exponent part 103. , 104 and a shift signal generating circuit 3 for generating a shift signal 108 for normalizing the multiplication result 107 of the multiplication circuit 1
And a normalization processing circuit 4 that normalizes the multiplication result 107 of the multiplication circuit 1 by shifting it according to the shift signal 108 and outputs a mantissa operation result 109, and a shift indicated by the shift signal 108 based on the addition result 110 of the addition circuit 2. A subtraction circuit 5 that subtracts the number and outputs an exponent part operation result 111 indicating the value of the exponent part after the normalization processing.

The multiplication circuit 1 includes an encoder 11, a partial product generation and addition circuit 12, and an addition circuit 13.

The encoder 11 has a mantissa 101 as a multiplier.
Is input, a process according to Booth's algorithm is performed, and an operation method for generating one partial product for a multiplier of 2 bits is performed by the partial product generation and addition circuit 1.
Notify 2.

The processing of the encoder 11 will be described in detail. When a multiplier Y (supposed to be composed of 6 bits Y _{1 to} Y ₆ ) is input, as shown in FIG. Are separated by 2 bits from
The bits Y _{i + 2 and} Y _{i + 1} are paired with the preceding one bit Y _i . Then, the Booth algorithm shown in FIG. 5 is applied to each pair, and the partial product generation and addition circuit 12 is notified of an operation method for generating one partial product for a multiplier of 2 bits.

For example, Y ₁ = 1 _, Y ₂ = 0 _, Y ₃ = 0 _,
Assuming that Y ₄ = 1 _, Y ₅ = 1 _{, and} Y ₆ = 0, Y _{i + 2} = 0 _, Y _{i + 1} = 1 _{, and} Y _i = 0 for bits Y _{1 and} Y ₂ .
Therefore, the operation method for generating the first partial product for the bits Y _{1 and} Y _{2 is} to notify the partial product generation and addition circuit 12 that “the value of the multiplicand X will be a partial product Z _i ”, and the bit Y
_3, since for the Y ₄ are _{Y i + 2 = 1, Y} i + 1 = 0, Y i = 0, "multiplicand as an operation method for generating a second partial product for bit Y _3, Y ₄ X Shift one bit to the left,
To the partial product generation and addition circuit 12 to make the two's complement of that value into a partial product Z _i , and to the bits Y _{5 and} Y ₆ ,
_{Since i + 2} = 0 _, Y _{i + 1} = 1 _{, and} Y _i = 1, the bit Y
_5, as an operation method for generating a third partial product for Y ₆ "by one bit shifting the multiplicand X to the left, to partial product Z _i" notifies the partial product generating circuit 12 that.

The partial product generation and addition circuit 12 includes an encoder 11
Generates a partial product in accordance with the instruction from, and adds the generated partial products to form a sum vector 105 and a carry vector 1.
06 is output.

The adder circuit 13 includes a sum vector 105 and a carry vector 106 output from the partial product generator / adder circuit 12.
And outputs the addition result as the multiplication result 107 of the multiplication circuit 1.

If the sign bit of the multiplication result 107 is "0", that is, if the multiplication result is positive, the shift signal generation circuit 3 outputs 1 if the first decimal place of the multiplication result 107 is "0".
Outputting a shift signal 108 indicating a bit shift;
If "1", a shift signal 108 indicating that no shift is performed is output. If the sign bit of the multiplication result 107 is “1”, that is, if the multiplication result is negative, a shift signal 108 indicating a one-bit shift is output if the first decimal place of the multiplication result 107 is “1”. If "0", a shift signal 108 indicating that no shift is performed is output.

In the normalization process 4, the multiplication result 107 added from the multiplication circuit 1 is normalized by shifting it according to the shift signal 108, and the result is converted to the mantissa operation result 10
9 is output.

The addition circuit 2 to which the exponents 103 and 104 are added adds the two, and outputs an addition result 110.

The subtraction circuit 5 calculates the addition result 110 of the addition circuit 2.
Is subtracted from the shift number indicated by the shift signal 108, and the result of the subtraction is output as the exponent part operation result 111.

[0015]

The conventional normalized floating-point multiplication circuit shown in FIG.
7, the shift signal 108 for normalization is generated, and the shift signal 108 cannot be generated unless the operation in the multiplication circuit 1 is completed.
There is a problem that it is difficult to increase the calculation speed.

An object of the present invention is to improve the operation speed of a normalized floating point multiplication circuit.

[0017]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a normalized floating-point multiplication circuit for multiplying a floating-point signal in 2's complement format, in which a mantissa as a multiplicand and a multiplier are provided. Generate a partial product by inputting the mantissa and
A multiplication circuit that adds the generated partial products to generate a sum vector and a carry vector, adds the generated sum vector and the carry vector, and outputs an addition result as a multiplication result, and a sum generated by the multiplication circuit. A shift signal look-ahead circuit for inputting a vector, a carry vector, a sign bit of a mantissa part to be the multiplicand and a multiplier, and foreseeing a sign of a multiplication result of the multiplication circuit and a value of a first decimal place; A shift signal generating circuit for generating a shift signal for normalization based on a sign and a value of the first decimal place which the circuit has seen, and an operation result of the operation circuit based on the shift signal generated by the shift signal generating circuit A normalization processing circuit for normalizing, an addition circuit for adding an exponent part corresponding to the mantissa part serving as the multiplicand and an exponent part corresponding to the mantissa part serving as the multiplier, and an addition circuit. It is provided with a result of the addition and the subtraction circuit performing subtraction between the shift number indicating a shift signal.

[0018]

The multiplication circuit inputs a mantissa part to be a multiplicand and a mantissa part to be a multiplier, generates a partial product, and adds the generated partial products to generate a sum vector and a carry vector. Further, the multiplication circuit adds the sum vector and the carry vector, and outputs the addition result as a multiplication result of the multiplication circuit.

The shift signal look-ahead circuit inputs a sign bit of a mantissa part as a multiplicand and a multiplier, a sum vector and a carry vector which are values in the middle of a multiplication process, and outputs a sign and a decimal point of a multiplication result of the multiplication circuit. Foresee the value of the first place.

The shift signal generation circuit generates a shift signal for normalization based on the sign and the value of the first decimal place which the shift signal look-ahead circuit looks ahead.

The normalization processing circuit normalizes the multiplication result of the multiplication circuit based on the shift signal generated by the shift signal generation circuit.

The exponent corresponding to the mantissa as the multiplicand and the multiplier is added by the adder and then added to the subtractor, where the shift number indicated by the shift signal is subtracted.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The same reference numerals as in FIG. 3 denote the same parts.

The normalized floating-point multiplication circuit of this embodiment has a configuration in which a shift signal look-ahead circuit 6 is added to the conventional normalized floating-point multiplication circuit shown in FIG.

As shown in FIG. 2, the shift signal look-ahead circuit 6 includes a carry look-ahead circuit 61, an adder circuit 62, and an exclusive OR circuit 63.

The carry look-ahead circuit 61 has bits 105 corresponding to the second and lower decimal places of the sum vector 105 and the carry vector 106 output from the partial product generation and addition circuit 12.
-(N-2) -105-1,106- (n-2) -10
6-1 is added, and when a carry is necessary for the first decimal place, a carry output signal 61 which is an output signal thereof.
−1 is set to “1”, and if not necessary, set to “0”.

The addition circuit 62 has a bit 1 corresponding to the first decimal place of the sum vector 105 and the carry vector 106.
05- (n-1), 106- (n-1) and the carry output signal 61-1 output from the carry look-ahead circuit 61, and by adding them, the multiplication circuit 1
Bit 6 indicating the value of the first decimal place of the multiplication result 107 of
2 is output. Note that the most significant bit (sign bit) of the sum vector 105 and the carry vector 106 is not used in the shift signal look-ahead circuit 6.

The exclusive OR circuit 63 has a mantissa 101,
The code bits 101-1 and 102-1 of 102 are added, and the exclusive OR of the two is obtained to output a code bit 6-1 indicating the sign of the multiplication result 107.

Next, the operation of this embodiment will be described.

When the mantissa parts 101 and 102 are added, the multiplication circuit 1 performs the same operation as described above, and the multiplication result 1
07 is output.

Before the multiplication circuit 107 outputs the multiplication result 107 to the shift signal look-ahead circuit 6, the sum vector 105, the carry vector 106 and the mantissa part 10 which are values during the multiplication are output.
1, 102 sign bits 101-1 and 102-1 are added.

When the sign bits 101-1 and 102-1 are added, the exclusive OR circuit 63 in the shift signal look-ahead circuit 6 takes the exclusive OR of the two and outputs the sign bit 6 indicating the sign of the multiplication result 107. Outputs -1.

The carry look-ahead circuit 61 in the shift signal look-ahead circuit 6 includes a sum vector 105 and a carry vector 106.
Bit 105- (n-
2) When 105-1 and 106- (n-2) to 106-1 are added, a carry signal 61-1 indicating the presence or absence of a carry to the first decimal place is output.

The adder circuit 62 outputs a bit 105 corresponding to the first decimal place of the sum vector 105 and the carry vector 106.
When-(n-1), 106- (n-1) and the carry output signal 61-1 are added, they are added and the multiplication circuit 1 is added.
Output the bit 6-2 indicating the multiplication result 107 of the first decimal place of.

When the shift signal look-up circuit 6 outputs the sign of the multiplication result 107 and the bits 6-1 and 6-2 indicating the value of the first decimal place from the shift signal look-ahead circuit 6, the shift signal generation circuit 3 performs normalization based on these. A shift signal 108 indicating the number of shifts is generated and output. That is, when the bit 6-1 indicating the sign of the multiplication result 107 is “0”, the shift signal generation circuit 3
That is, when the multiplication result 107 is positive, if the bit 6-2 is “0”, the shift signal 10 indicating a one-bit shift
8 is output, and if "1", a shift signal 108 indicating that no shift is performed is output. Also, the multiplication result 10
7 is “1”, that is, the multiplication result 1
When 07 is negative, a shift signal 108 indicating a one-bit shift is output if bit 6-2 is "1", and a shift signal 108 indicating no shift is performed if bit 6-2 is "0".
Is output.

In accordance with the shift signal 108, the normalization processing circuit 4 and the subtraction circuit 5 perform the same operations as described above.

As described above, this embodiment uses the sum vector 105 and the carry vector 106 which are values in the middle of multiplication by the multiplication circuit 1 in the shift signal look-ahead circuit 6 to sign and multiply the decimal point of the multiplication result 107. Bit 6-1 indicating the value of the first place
Since 6-2 is generated and output, the shift signal 108 can be generated earlier than in a conventional circuit that generates the shift signal 108 based on the multiplication result 107 of the multiplication circuit 1. As a result, the normalization processing in the normalization processing circuit 4 can be performed earlier than in the conventional circuit, and the processing speed of the normalized floating-point multiplication circuit can be improved.

[0039]

As described above, according to the present invention, the sign and the decimal point of the multiplication result of the multiplication circuit are calculated based on the sign bit of the mantissa and the sum vector and the carry vector which are values in the middle of the operation of the multiplication circuit. A shift signal look-ahead circuit for looking ahead to the first place value is provided, and the shift signal look-ahead circuit generates a shift signal based on the look-ahead sign and the value of the first decimal place. The time required for the normalization processing can be reduced as compared with a conventional normalized floating-point multiplication circuit that has generated a shift signal based on the above, and the processing speed of the normalized floating-point multiplication circuit as a whole can be increased. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a shift signal look-ahead circuit 6.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a diagram for explaining the operation of the encoder 11.

FIG. 5 is a diagram showing a Booth algorithm.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Multiplication circuit 11 ... Encoder 12 ... Partial product generation addition circuit 13 ... Addition circuit 2 ... Addition circuit 3 ... Shift signal generation circuit 4 ... Normalization processing circuit 5 ... Subtraction circuit 6 ... Shift signal look-ahead circuit 61 ... Carry look-ahead circuit 62 ... Addition circuit 63 ... Exclusive OR circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 310 G06F 7/00

Claims (2)

(57) [Claims] 1. A normalized floating-point multiplication circuit for multiplying a two's complement floating-point signal by inputting a mantissa part as a multiplicand and a mantissa part as a multiplier to generate a partial product, A multiplication circuit that generates a sum vector and a carry vector by adding the calculated partial products, adds the generated sum vector and the carry vector, and outputs an addition result as a multiplication result, and a sum vector generated by the multiplication circuit. , The carry vector and the sign bit of the mantissa part to be the multiplicand and the multiplier,
A shift signal look-ahead circuit for foreseeing the sign and the value of the first decimal place of the multiplication result of the multiplication circuit; and a shift signal for normalization based on the sign and the value of the first decimal place for which the shift signal look-ahead circuit looks ahead A shift signal generation circuit that generates the following: a normalization processing circuit that normalizes the operation result of the operation circuit based on the shift signal generated by the shift signal generation circuit; and an exponent part corresponding to the mantissa part serving as the multiplicand. An adder circuit for adding an exponent part corresponding to the mantissa part serving as the multiplier, and a subtractor circuit for subtracting the addition result of the adder circuit from the shift number indicated by the shift signal. Normalized floating point multiplier. 2. The shift signal look-ahead circuit, wherein an exclusive-OR circuit for foreseeing the sign of the multiplication result of the multiplication circuit by taking the exclusive-OR of the sign bit of the mantissa part to be the multiplicand and the multiplier; A carry look-ahead circuit for inputting a bit corresponding to the second decimal place or less of the sum vector and the carry vector and outputting a signal indicating whether or not the carry to the first decimal place is present; An adder circuit for adding the bit corresponding to the first decimal place and the output signal of the carry look-ahead circuit to look ahead to the value of the first decimal place of the multiplication result of the multiplication circuit. 2. The normalized floating point multiplication circuit according to claim 1, wherein