JP3077601B2 - Semiconductor integrated circuit layout and wiring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the and element blocks in a semiconductor integrated circuit, relates placement and routing method such as wiring for connecting the blocks, regarding placement and routing method for a semiconductor integrated circuit having particular hierarchical layout structure.

[0002]

2. Description of the Related Art Generally, in designing a large-scale semiconductor integrated circuit, it is necessary to simultaneously design each part of the integrated circuit in order to shorten the design period. Therefore, in such a large-scale integrated circuit, a building block type design method is adopted in which a circuit is divided into a plurality of blocks, each block is designed at the same time, and finally each block is wired and assembled. Then, in this design method, in order to reduce the chip area and achieve high-speed operation, each block is brought as close as possible and the wiring between blocks is shortened as much as possible. ) Process is adopted. As this method, for example, Japanese Patent Laid-Open No. 7-2
There is a technique described in Japanese Patent No. 73204.

FIG. 8 is a flowchart of a conventional building block design method. Here, from the viewpoints of chip area reduction and high-speed operation, each layout block is arranged at an optimum relative position (step S11), and the layout positions and terminals of layout blocks (hereinafter referred to as hard blocks) to be laid out manually are set. From the position, CAD
The external shape and terminal positions of layout blocks (hereinafter, referred to as soft blocks) to be automatically laid out by the apparatus are determined (step S12), wiring is performed between layout blocks (step S13), and the chip layout after wiring is determined according to the design rules. The procedure is to reduce as much as possible (hereinafter referred to as compaction) within the allowable range (step S14). FIG. 9A shows a layout before compaction by the conventional method, and FIG. 9B shows a completed chip layout after compaction by the conventional method.

[0004]

However, the conventional compaction technology based on the building block method has a problem that the effect of area reduction by compaction is small. The reason is that the external shape and terminal position of the soft block are determined before compaction, so if the relative position of each layout block is slightly shifted after compaction, the external shape and terminal position of the soft block will not be optimal, This is to prevent effective compaction.

An object of the present invention is to provide a method of arranging and wiring a semiconductor integrated circuit , which enhances the effect of compaction in a building block system and enables a further reduction in the area of a chip.

[0006]

According to the present invention, there is provided a method of arranging and wiring a semiconductor integrated circuit including a first block having a fixed shape and terminal position and a second block having a changeable shape and terminal position. a step of wiring between blocks based on the arrangement and the terminal position of the block, blanking of the interconnection
Determining the number of wires extending in parallel with the lock side; and determining the shape and terminal position of the first block and the number of wires.
The method includes a step of determining a position, a shape, and a terminal position of the second block based on the number , a step of rewiring between blocks thereafter, and a compaction step performed thereafter. Here, the interval between the layout blocks is set to the minimum interval that can secure the number of channels that can be arranged in each channel region.

[0007]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart showing an embodiment of the present invention in the order of steps, and the overall procedure will be described. First, the step of arranging the hierarchical layout blocks at the optimum relative positions (step S1), and the external shape of the soft blocks to be automatically laid out by the CAD device from the arrangement positions and the terminal positions of the hard blocks laid out manually. A step of optimizing terminal positions (step S2), a step of wiring between layout blocks (step S3), and a compaction step of reducing the chip layout after wiring as much as possible within the setting rules ( Step S4), a step of determining the number of channels necessary for the channel region between the layout blocks (Step S5), a step of deleting the wiring between the layout blocks (Step S6), and the channel determined in this step. Relocate each layout block as close as possible while keeping the number Step (Step S7)
A step of optimizing the outer shape and terminal positions of the soft blocks based on the arrangement (step S8), a step of rewiring between layout blocks (step S9), and a rule for setting a chip layout after wiring And a compaction step (step S10) for reducing the size as much as possible.

The above method will be described in detail with reference to layout examples shown in FIGS. First, FIG.
As shown in (a), each layout block is arranged at an optimum relative position from the viewpoint of chip area reduction and high-speed operation. Next, as shown in FIG. 2B, the hard block HB1
Block S from the arrangement position and terminal position of
The external shape and terminal position of B1 are determined. Here, the arrangement position and the outer shape of the soft block SB1 are determined so that the hard block HB1 and the soft block SB1 are aligned in the height direction.

Next, as shown in FIG. 3A, wiring is performed between layout blocks to obtain a layout having a wiring L1 as shown in FIG. Next, compaction is performed to bring each layout block close to each other, and the wiring L
1 is obtained, and a layout as shown in FIG. 3B is obtained. Up to this point, it is the same as the conventional method. In this layout, the area between the hard block HB1 and the soft block SB1 and the area between the hard block HB2 and the soft block SB1 are useless. However, this area cannot be reduced unless the terminal position of the soft block SB1 is changed. For example, if the interval between the hard block HB1 and the soft block SB1 is to be reduced, the wiring connecting the terminal on the upper side of the hard block HB2 and the terminal on the lower side of the soft block SB1 is bent, and the wiring shown in FIG. ), And it becomes impossible to observe the design rule between wirings in this portion. Therefore, the soft block SB1 and the hard block HB2
Cannot be made smaller than the current state, and the chip area increases.

Therefore, in the present invention, as described above, the number of channels required for each channel region, that is, the number of wirings extending in parallel with the block sides in the region between blocks is first determined from the result of the compaction. FIG.
In (a), the soft block SB1 and the hard block H
The required number of channels is 0 in the area S1 between B1, the required number of channels is 3 in the area S2 between the soft block SB1 and the hard block HB2, and the required number of channels is 3 in the area S3 between the hard block HB1 and the hard block HB2.

Next, the wiring between the layout blocks is deleted, and the layout blocks are rearranged as close to each other as possible while securing the number of channels determined in the above step. obtain. This close distance is the minimum dimension in which a channel required for each region can be arranged.
Then, based on this layout, the terminal positions of the soft blocks are optimized again to obtain FIG. 5A. If the wiring L3 between the layout blocks is executed again for this layout and compaction is performed, a layout in which a useless area between the layout blocks is maximally deleted as shown in FIG. 5B can be obtained. Become.

Here, considering the case where the result of the first compaction (step S4, FIG. 4 (a)) is as shown in FIG. 6 (a), the design is advanced in accordance with the above-mentioned flowchart, After the second compaction (step S7), it is assumed that the result of optimizing the terminal positions of the soft block SB1 is as shown in FIG. As described above, even if wiring between the layout blocks is performed and final compaction is applied, useless areas Z1 and Z2 remain above the soft block SB1 and on the left side of the hard block HB2. Then, soft block S
While keeping the area of B1 constant, its external shape is shown in FIG.
By changing as in (a), the useless area described above does not occur, and the chip surface can be minimized. After that, wiring between the layout blocks is performed and final compaction is performed to obtain a layout as shown in FIG. 7B, in which useless areas between the layout blocks are maximally deleted.

[0013]

As described above, the present invention relates to a method of arranging and wiring a semiconductor integrated circuit including a first block having a fixed shape and terminal position and a second block having a changeable shape and terminal position. Wiring between blocks based on the arrangement and terminal positions of the blocks , determining the number of wirings extending in parallel with the block side of the wirings, and determining the shape and the shape of the first block. the distribution terminal position
Since the method includes a step of determining the position, shape and terminal position of the second block based on the number of lines, a step of rewiring between blocks thereafter, and a compaction step performed thereafter, chip layout by compaction is performed. The reduction effect is enhanced, thereby minimizing a useless area between layout blocks and realizing a reduction in the size of the semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the method of the present invention in the order of steps.

FIG. 2 is a first layout diagram according to an embodiment of the method of the present invention.

FIG. 3 is a second layout diagram according to the embodiment of the method of the present invention.

FIG. 4 is a third layout diagram in the embodiment of the method of the present invention;

FIG. 5 is a layout diagram No. 4 in the embodiment of the method of the present invention;

FIG. 6 is a first layout diagram according to another embodiment of the method of the present invention.

FIG. 7 is a second layout diagram in another embodiment of the method of the present invention.

FIG. 8 is a flowchart of an example of a conventional method.

FIG. 9 is a layout diagram for explaining a problem in a conventional method.

[Explanation of symbols]

 HB1, HB2 Hard block SB1 Soft block L1 to L3 Wiring S1 to S3 Channel area Z1, Z2 Useless area

Claims (2)

(57) [Claims] 1. A method for arranging and wiring a semiconductor integrated circuit including a first block having a fixed shape and terminal position and a second block having a changeable shape and terminal position, based on the block arrangement and terminal position. Wiring between blocks by extending the wiring in parallel with the block side.
Determining the number of wirings to be connected; determining the position, shape and terminal position of the second block based on the shape and terminal position of the first block and the number of wirings; And a compaction step performed thereafter. 2. The method according to claim 1, wherein an interval between the layout blocks is
Placement and routing method for a semiconductor integrated circuit according to claim 1 to set the minimum interval to each of the channel region may ensure disposed possible number of channels.