JP3077502B2 - Pulse modulation method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation apparatus for transmitting a digital signal and a recording apparatus for recording the digital signal. The present invention relates to a pulse modulation device for realizing this.

[0002]

2. Description of the Related Art A band-limited pulse signal can be represented by an impulse response waveform weighted by a pulse amplitude. Since pulses are generated at fixed time intervals, the pulse signal train after band limitation is represented by convolution addition of the above-mentioned response waveform to the generated pulse at each time. The amplitude of the impulse response decreases as the distance from the pulse generation time increases, and after a certain period of time, even if the impulse response is terminated and the amplitude is set to 0, the transmission frequency bandwidth of the signal is hardly affected. At this time, time nT
The generated signal i (nTs) in s can be represented by (Equation 1).

[0003]

(Equation 1)

In equation (1), T is a pulse time interval,
Ts is a discrete time interval for outputting a modulation signal, and I (k)
Is the amplitude of the k-th pulse, h (t) is the amplitude of the impulse response at time t when the necessary frequency band limitation is performed on the unit pulse of amplitude 1, and x is the pulse time at which the impulse response is stopped. This is a coefficient when expressed as a multiplier with the interval. Note that h (t) represents a waveform when a pulse is input at t = 0, and h (xT) =
Set to 0. Further, it is assumed that n is in a range represented by 0 ≦ nTs <T.

Now, if I (k) has s values and n is a constant value, i (nTs) becomes 2 × I
It can have the same kind of value as the combination of (k). That is, i (nTs) takes one of s ^2x kinds of values.
If there is a relationship of T = mTs, n is 0, 1,
... In order to take m types of values of m-1, in equation (1), the possible value of i (nTs) for all n is s ^2x
× m.

Next, the operation of the pulse modulation device for realizing the conventional pulse modulation method will be described. FIG. 8 shows a configuration of a conventional pulse modulation device. In FIG. 8, digital data to be modulated is input from an input terminal 21 and input to an address generator 22. The address generator 22 generates an address according to the input data,
Output to the memory 23. The memory 23 outputs the modulated signal stored at the designated address from the output terminal 24. In FIG.
The address corresponding to (k) is generated by the address generator 22, and the addresses corresponding to the discrete times obtained by dividing the pulse interval into m are sequentially output to the memory 23, whereby the modulation stored in the memory 23 in advance is performed. The signal can be extracted.

As described above, in the above-described conventional pulse modulation method and the pulse modulation apparatus for realizing the same, all necessary signals are prepared in advance in the memory, so that the pulse generation and frequency Bandwidth can be limited.

[0008]

However, in the pulse modulation device according to the above conventional pulse modulation method, s ^2x ×
All of the m kinds of modulated signals must be prepared in the memory, and a large memory capacity is required, so that the circuit scale is increased. As a result, a large power consumption is required and the price is increased. There was a problem.

The present invention solves such a conventional problem, and provides a pulse modulation method capable of greatly reducing the required memory capacity. The pulse modulation method significantly reduces the circuit scale. It is an object of the present invention to provide an excellent pulse modulation device which can reduce power consumption and can be realized at low cost.

[0010]

Means for Solving the Problems The present invention to achieve the above object, a component and Do Ri time of the output waveform memory symmetry
By storing one waveform of the following combination and providing an adder at the subsequent stage of the memory, the symmetry output from the memory is improved.
The required processing is performed on the signal of a certain combination to output the signal.

[0011]

Therefore, according to the present invention, the types of signals to be stored in the memory in advance can be reduced by processing the output from the memory using an externally provided adder. This has the effect that the required memory capacity can be significantly reduced.

[0012]

1 to 7 show an embodiment of the present invention.
This will be described with reference to FIG.

FIG. 1 shows the configuration of a first embodiment of the present invention. In FIG. 1, 1 is an input terminal for inputting data to be modulated, 2 is an address generator for generating an address for a memory, 3 is a memory for storing a signal for generating a modulation signal, and 4 is an output of the memory. , A selector for holding an input signal, 6 an adder for adding two input signals to each other and outputting the same, and 7 an output terminal.

Next, signals to be stored in the memory in the first embodiment will be described. As described in the description of the related art, the modulation signal i at time nTs
(NTs) can be represented by (Equation 1). At this time,
Since the impulse response to the pulse signal has a waveform that is symmetrical back and forth as viewed from the time when the pulse signal is added, (Equation 1) can be expressed as (Equation 2) shown below.

[0015]

(Equation 2)

However, in (Equation 2), the contents and conditions of the symbols are the same as in (Equation 1). Now, assuming that I (k) has s values, the first term of (Equation 2) can take s ^x values, and the same applies to the second term. At this time, T
= MTs, the time t of the impulse response h (t) used is from 0 to (x-1) T + (m-1) Ts for each Ts in the first term. In the second term, a value from Ts to xT is taken for each Ts. h (xT) =
Since 0, except for this from the second term, the range of the second term of t can be from Ts to (x-1) T + ( m-1) Ts, the second term s ^x -1 The type value can be included in the s ^x type value of the first term. Therefore, the types of values to be prepared in the memory are s ^x types. Also, n
Takes m types of values 0, 1,..., M−1, and the value to be prepared in the memory for all n is s ^x × m
Kind.

Next, the operation of the first embodiment will be described. In FIG. 1, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 generates addresses representing the storage addresses of the signals represented by the first and second terms of the above (Equation 2), and inputs the generated addresses to the memory 3. At this time,
Since the possible value of the second term is included in the possible value of the first term, by reading out the signal in the memory in a time-divided manner, one value is obtained for the first and second terms. All you have to do is prepare the memory. The signal output from the memory 3 is sorted by the selector 4 according to each term, and is held by the holding circuits 5a and 5b.
Is input to The adder 6 adds the values of the first and second terms held in the holding circuit to each other and outputs the result from the output terminal 7.

As described above, according to the first embodiment,
Compared with the conventional pulse modulation device, the required memory capacity can be reduced to 1 / ^x .

Next, a second embodiment of the present invention will be described. FIG. 2 shows the configuration of the second embodiment. In FIG. 2, 1 is an input terminal for inputting data to be modulated, 2 is an address generator for generating an address for the memory, 3 is a memory for storing a signal for generating a modulated signal,
Reference numeral 8 denotes a sign inverter that inverts the sign of the input signal or outputs the signal without inversion, and 7 denotes an output terminal.

Next, the signals to be stored in the memory in the second embodiment will be described. As described in the description of the related art, the modulation signal i at time nTs
(NTs) can be represented by (Equation 1). At this time,
Assuming that the possible values of the amplitude of the pulse signal are arranged symmetrically when viewed from 0, I (k) can be expressed as shown in (Equation 3) below.

[0021]

(Equation 3)

In (Equation 3), S (k) is I + (k)
And has a value of either +1 or -1.
When I (k) has s values, if s is even, I + (k) is s / 2 types, and if s is odd, I + (k) is (s + 1) / 2 values. have.

Using I + (k), (Equation 1) can be rewritten as (Equation 4) below.

[0024]

(Equation 4)

However, in (Equation 4), the contents of the symbols and
And conditions are the same as in (Equation 1). As shown in (Equation 4)
And all combinations of S (k) have opposite signs
For items, only the entire sign of the term is reversed,
There is a relationship that the pair values are equal to each other. Therefore, the output
By having the function of inverting the sign of the signal,
It is possible to reduce the number of signals that need to be prepared. sand
That is, in the second embodiment, when s is an even number, s^2x
× m / 2 types, when s is an odd number, (s^2x+ S ^2x-1) × m
/ 2 types are the types of values that should be prepared in the memory.
You.

Next, the operation of the second embodiment will be described. In FIG. 2, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 generates an address representing the storage address of the signal represented by (Equation 4). At this time, if the modulation signal corresponding to the input data is stored in the memory as it is, the address is generated as it is, and if the modulation signal corresponding to the input data is stored in the memory in a reversed form. Generates the address of the inverted signal and controls the sign inverter 8 to invert the sign. The address output from the address generator 2 is input to the memory 3, and the signal output from the memory 3 is input to the sign inverter 8. The sign inverter 8 inverts the sign of the input signal according to the control from the address generator, or outputs the signal without inversion. The output of the sign inverter 8 is output from the output terminal 7.

As described above, according to the second embodiment,
The required memory capacity can be reduced to 1 / 2s / (s + 1) or less as compared with the conventional pulse modulation device.

Next, a third embodiment of the present invention will be described.
FIG. 3 shows the configuration of the third embodiment. FIG.
Wherein 1 is an input terminal for inputting data to be modulated,
2 is an address generator for generating an address for the memory, 3a to 3d are memories for storing modulation signals, 6 is an adder for adding and outputting output signals from the memories to each other,
7 is an output terminal.

Next, signals to be stored in the memory in the third embodiment will be described. As described in the description of the related art, the modulation signal i at time nTs
(NTs) can be represented by (Equation 1). Here, the coefficient x when the time to stop the impulse response is represented by the product of the pulse time interval is represented by the following (Equation 5).

[0030]

(Equation 5)

Here, it is assumed that a and xd are both positive integers. Expressing (Equation 1) using the relation of (Equation 5) can be expressed as (Equation 6) shown below.

[0032]

(Equation 6)

However, in (Equation 6), the contents and conditions of the symbols are the same as in (Equation 1). Here, the value in the curly braces (（) can take s × ^d kinds of values. From this, when n is considered to be a constant, the possible values of the terms in the curly braces are s × ^d , and the value to be stored in the memory is 2
a × s ^xd types. Also, n is 0, 1, ... m-1
, The values to be stored in the memory for all n are 2a × s ^xd × m types, that is, 2a × s
^{x / a} × m types.

Next, the operation of the third embodiment will be described. FIG. 3 shows that as a value of a in (Equation 5), a =
2 shows a configuration in the case of 2. At this time, a signal to be prepared in the memory can be expressed as shown in (Equation 7) below by applying a = 2 to (Equation 6).

[0035]

(Equation 7)

The memories 3a to 3d store the contents of the first to fourth terms of (Equation 7), respectively.

In FIG. 3, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 generates an address representing the storage address of the signal represented by each term of the equation (7).
The addresses output from the address generator 2 are input to the memories 3a to 3d, respectively. The signals output from the memories 3a to 3d are input to the adder 6, added to each other, and output from the output terminal 7.

As described above, according to the third embodiment,
By appropriately selecting the value of a, the required memory capacity can be reduced as compared with the conventional pulse modulation device.

In the above third embodiment, a =
In the case where a positive integer of 2 or more is selected as the value of a, 2 × a memories 3 are prepared in FIG.
A value corresponding to each value of j in (Equation 6) is stored. In addition, since it is necessary to add all the outputs of the memories, the adder 6 has a 2-input adder of 2 × a−1.
It is necessary to prepare an adder which adds two or more inputs and outputs one signal. With this configuration, even when the value of a is selected as an arbitrary positive integer, the same effect as in the third embodiment can be obtained.

Next, a fourth embodiment of the present invention will be described. FIG. 4 shows the configuration of the fourth embodiment. In FIG. 4, 1 to 7 are the same as the components used in the first embodiment. Numeral 8 denotes the same sign inverter as used in the second embodiment.

A signal to be stored in the memory in the fourth embodiment will be described. As described in the description of the first embodiment, the modulation signal i at time nTs
(NTs) can be represented by (Equation 2). Also, the second
As described in the embodiment, when I (k) can be expressed by (Equation 3), (Equation 2) is expressed by S (k) and I +
Using (k), it can be rewritten as shown in the following (Equation 8).

[0042]

(Equation 8)

However, in (Equation 8), the contents and conditions of the symbols are the same as in (Equation 2) and (Equation 4). As described in the first embodiment, the possible values of the first and second terms of (Equation 8) for all n are s ^x × m. Further, as described in the second embodiment, the first
In the term and the second term, when all the combinations of S (k) are inverted, the types of signals to be prepared in the memory can be reduced by providing a sign inverter, and when s is even, s ^x × m / 2 types, and when s is an odd number, (s ^x + s ^x-1 ) × m / 2 types may be prepared. .

Next, the operation of the fourth embodiment will be described. In FIG. 4, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 generates an address representing the storage address of the signal represented by the first and second terms of (Equation 8). At this time, if the modulation signal corresponding to the input data is stored in the memory as it is, the address is generated as it is, and if the corresponding signal is stored in the memory with the sign of the signal inverted, An address of the inverted signal is generated, and the sign inverter 8 is controlled to invert the sign. The address output from the address generator 2 is input to the memory 3. The signal output from the memory 3 is input to the sign inverter 8. The sign inverter 8 inverts the sign of the input signal or outputs the signal without being inverted according to the control from the address generator. The output of the sign inverter 8 is sorted by the selector 4 according to each term, and is input to the holding circuits 5a and 5b. Subsequent operations are the same as in the first embodiment.

As described above, according to the fourth embodiment,
There is an advantage that the required memory capacity can be reduced as compared with the conventional pulse modulation device.

Further, according to the fourth embodiment, the first
There is an advantage that the required memory capacity can be reduced as compared with the embodiments and the second embodiment. Next, a fifth embodiment of the present invention will be described. FIG. 5 shows the configuration of the fifth embodiment. FIG.
Wherein 1 is an input terminal for inputting data to be modulated,
2 is an address generator for generating an address to the memory, 3a and 3b are memories for storing a signal for generating a modulation signal, 4a and 4b are selectors for branching and outputting an output signal from the memory, and 5a to 5d are A holding circuit for holding the input signals, 6 is an adder for mutually adding and outputting the output signals from the four holding circuits, and 7 is an output terminal.

Next, signals to be stored in the memory in the fifth embodiment will be described. As described in the description of the first embodiment, the modulation signal i (nTs) at the time nTs can be represented by (Equation 2). Here, if x is expressed by (Equation 5), (Equation 2) can be expressed as (Equation 9) shown below using a and xd.

[0048]

(Equation 9)

In (Equation 9), for each value of j, t (t) of h (t) in the first term in braces
The range t of the second term is shifted in the positive direction by Ts with respect to the range. For example, when j = 0, the first term t
The range to from 0 (xd-1) T + (m-1) in the range of Ts, the second term takes a value in the range of Ts of x ^d T. At this time, t in the second term is out of the range of t in the first term only when n = 0. (Equation 9) at this time can be expressed as (Equation 10) shown below.

[0050]

(Equation 10)

In (Equation 10), since both the first and second terms in the curly braces 項 include the term of I (0) · h (0), it is necessary to exclude one of them. But here h
The value of t in (t) becomes 0 because n = 0, that is, Equation 9b
Therefore, when calculating the data to be stored in the memory, h (0) / h is used instead of h (0) in advance.
By calculating using the value of 2, (Equation 10)
The third term becomes unnecessary. Although the second term of (Equation 10) does not include the term of I (x) · h (x), since the value of h (x) is 0, this term can be ignored. .

H '(0) = h (0) / 2, and for other than 0, h' (t) = h (t).
By rewriting (Equation 10) using
It can be expressed as 1).

[0053]

[Equation 11]

In the second term in the curly braces (Equation 11)
Therefore, the possible range of t of h '(t) is
H when n = 0 in the first term in
Since (t) is within the range of t, (Equation 9),
In (Equation 11), the first and second terms in curly braces ｛｝
Can be s^xdPerfectly matches in kind. Also this
Since the value is independent for each value of j, the possible range of each term
The box is a × s^xdKind. Therefore, for all n
The type of signal to be prepared in the memory is a × s ^xd
× m types, ie, a × s^{x / a}× m types.

Next, the operation of the fifth embodiment will be described. FIG. 5 shows a configuration when a = 2 in (Equation 9). At this time, the signal to be prepared in the memory can be expressed as (Equation 12) and (Equation 13) shown below by applying a = 2 to (Equation 9) and (Equation 11).

[0056]

(Equation 12)

[0057]

(Equation 13)

In the memory 3a, (Equation 12) and (Equation 13)
The contents of the first and second terms are stored in the memory 3b, and the contents of the third and fourth terms of (Equation 12) and (Equation 13) are stored in the memory 3b. .

In FIG. 5, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 generates an address representing the storage address of the signal represented by (Equation 12) and (Equation 13). The addresses output from the address generator 2 are input to the memories 3a and 3b, respectively. Memory 3a,
The signals output from 3b are selectors 4a and 4b, respectively.
Are input to the corresponding ones of the holding circuits 5a to 5d and held according to the first and second terms of (Equation 12) and (Equation 13). The outputs of the four holding circuits are input to an adder 6, added, and output from an output terminal 7.

As described above, according to the fifth embodiment,
There is an advantage that the required memory capacity can be reduced as compared with the conventional pulse modulation device. Furthermore, according to the fifth embodiment, by selecting the value of a as a positive integer as appropriate, the required memory capacity can be reduced as compared with any of the first embodiment and the third embodiment. It has the advantage that it can be made smaller.

In the fifth embodiment, a =
Although the configuration is assumed to be 2, when a is selected to be a positive integer of 2 or more, a memory 3 is prepared in FIG. 5 and each j in (Equation 9) and (Equation 11) is used.
The value corresponding to the value of must be stored. Also,
It is necessary to prepare a selectors and 2 × a holding circuits, and as for the adder, it is necessary to add all outputs of the holding circuits.
It is necessary to prepare a-1 or an adder for adding 2 × a inputs to each other and outputting one signal. With such a configuration, the same effect as that of the fifth embodiment can be realized for the positive integer a appropriately selected.

Next, a sixth embodiment of the present invention will be described. FIG. 6 shows the configuration of the sixth embodiment. In FIG. 6, 1 is an input terminal for inputting data to be modulated, 2 is an address generator for generating an address for the memory, 3a to 3d are memories for storing a signal for generating a modulation signal, and 8a to 8d. Is a sign inverter which inverts the sign of the input signal or outputs the signal without inverting the sign;
Is an adder for mutually adding and outputting input signals, and 7 is an output terminal.

Next, signals to be stored in the memory in the sixth embodiment will be described. As described in the second embodiment, when I (k) is represented by (Equation 3), i (nTs) can be represented by (Equation 4). Here, assuming that x is represented by (Equation 5), if (Equation 4) is represented using a and xd, it can be represented as (Equation 14) shown below.

[0064]

[Equation 14]

However, in (Equation 14), the contents and conditions of the symbols are the same as (Equation 4) and (Equation 6).

As shown in (Equation 14), when all combinations of S (k) have opposite signs, there is a relationship that only the sign of the entire term is inverted and the absolute values are equal to each other. Therefore, by providing the function of inverting the sign of the output signal, the number of signals to be prepared in the memory can be reduced. That is, (Equation 14)
The value in curly braces is s ^xd / 2 when s is even.
When the type and s are odd, (s ^xd + s ^xd-1 ) / 2 types of values can be taken.

From this, the types of signals to be prepared in the memory for all n are a × s × ^d × m when s is an even number, ie, a × s ^{x / a} × m, When s is an odd number, there are a × (s ^xd + s ^xd-1 ) × m types, that is, a × (s ^{x / a} + s ^{x / a-1} ) × m types.

Next, the operation of the sixth embodiment will be described. FIG. 6 shows a configuration when a = 2 in (Equation 14). At this time, a signal to be prepared in the memory can be expressed as shown in (Equation 15) below by applying a = 2 to (Equation 14).

[0069]

(Equation 15)

In FIG. 6, memories 3a to 3d store
Of the contents of items 1 to 4 of (Equation 15),
It is assumed that signals other than combinations whose signs are all inverted are stored. In FIG. 6, digital data to be modulated is input from an input terminal 1 and an address generator 2
Is input to The address generator 2 generates a storage address of the signal shown in each item of (Equation 15). At this time, if the modulation signal corresponding to the input data is stored in the memory as it is, the address is generated as it is, and if the modulation signal corresponding to the input data is stored in the memory in a reversed form. Generates an address of an inverted signal and performs control to invert the sign of the corresponding one of the sign inverters 8a to 8d. The addresses output from the address generator 2 are stored in the memories 3a to 3d.
Is input to the corresponding one. Memory 3a to 3d
The output signals are sign inverters 8a to 8d, respectively.
To the adder 6 with the sign of the input signal inverted or without being inverted. In the adder 6, the output signals of the four sign inverters are added to each other and output to the output terminal 7.

As described above, according to the sixth embodiment,
There is an advantage that the required memory capacity can be reduced as compared with the conventional pulse modulation device. Further, according to the sixth embodiment, the value of a is appropriately selected as a positive integer, so that the required memory capacity can be reduced as compared with any of the second and third embodiments. It has the advantage that it can be made smaller.

In the sixth embodiment, a =
In the case where a is selected to be a positive integer of 2 or more, the memory 3 in FIG.
It is necessary that a values are prepared and values corresponding to the respective values of j in (Equation 14) are stored. Also, 2 × a sign inverters need to be prepared and connected to the output of each memory. As for the adder, since it is necessary to add all the outputs of the respective sign inverters, a two-input adder is used.
It is necessary to prepare × a−1 or an adder that adds 2 × a inputs and outputs one signal. With such a configuration, the same effect as that of the sixth embodiment can be realized for the positive integer a appropriately selected.

Next, a seventh embodiment of the present invention will be described. FIG. 7 shows the configuration of the seventh embodiment. In FIG. 7, 1 is an input terminal for inputting data to be modulated, 2 is an address generator for generating an address for the memory, 3a and 3b are memories for storing a signal for generating a modulation signal, 8a and 8b Are sign inverters that invert the sign of the input signal or output the signal without inversion,
a, 4b are selectors for branching and outputting the output from the sign inverter, 5a to 5d are holding circuits for holding input signals, 6 is an adder for adding and outputting input signals to each other, 7
Is an output terminal.

Next, signals to be stored in the memory in the seventh embodiment will be described. As described in the fifth embodiment, if x is expressed by (Equation 5), the modulation signal i (nTs) at the time nTs can be expressed by (Equation 9) and (Equation 11). Here, when I (k) is represented by (Equation 3), (Equation 9) and (Equation 11) are represented by the following (Equation 16) using S (k) and I + (k).
And (Equation 17).

[0075]

(Equation 16)

[0076]

[Equation 17]

Where h ′ (t) is h ′ (0) = h (0)
/ 2, and for t other than 0, h ′ (t) = h
(T).

In (Equation 16) and (Equation 17), the possible values of the first term are s ^xd / 2 types when s is even and (s ^xd + s ^xd-1 ) / 2 when s is odd. is there. The possible values of the second term are included in the possible values of the first term. From this, the type of signal to be prepared in the memory for all n is a × when s is an even number.
s ^xd × m / 2 types, that is, a × s ^{x / a} × m / 2 types, and when s is an odd number, a × (s ^xd + s ^xd-1 ) × m /
There are two types, that is, a × (s ^{x / a} + s ^{x / a-1} ) × m / 2.

Next, the operation of the seventh embodiment will be described. FIG. 7 shows a configuration when a = 2 in (Equation 16). In FIG. 7, digital data to be modulated is input from an input terminal 1 and input to an address generator 2. The address generator 2 is given by
6), an address representing the storage address of the signal shown in (Equation 17) is generated, and the memory 3a is generated in accordance with the value of j.
Or input to 3b. At this time, if the modulation signal corresponding to the input data is stored in the memory as it is, the address is generated as it is, and if the corresponding signal is stored in the memory with the sign of the signal inverted, In addition to generating the address of the inverted signal, control is performed to invert the sign of the corresponding one of the sign inverters 8a and 8b. The address generated from the address generator 2 is input to the memory 3a or 3b, and is stored in the memory 3a or 3b.
The output signal from b is input to sign inverters 8a and 8b. The sign inverters 8a and 8b invert the sign of the input signal according to the control from the memory generator 2 or output the signal to the selectors 4a and 4b without inversion. Selector 4
In a and 4b, the first term of (Equation 16) and (Equation 17), the second term
The term data is branched and output to another holding circuit 5a to 5d for each term. The adder 6 adds the signals output from the holding circuits 5a to 5d and outputs the added signal to the output terminal 7.

As described above, according to the seventh embodiment,
There is an advantage that the required memory capacity can be reduced as compared with the conventional pulse modulation device. In addition, according to the seventh embodiment, by appropriately selecting the value of a, the required memory capacity can be reduced as compared with any of the first to third embodiments.

In the seventh embodiment, a =
Although the configuration is assumed to be 2, when a is selected as a positive integer of 2 or more, a memory a is prepared in FIG. 7 and each j in (Equation 16) and (Equation 17) is prepared. The signal corresponding to the value of must be stored. Further, the same number of sign inverters 8 and selectors 4 need to be connected as the number of memories 3. Selector 4
Of the holding circuit 5 connected to the subsequent stage,
, That is, 2 × a. As for the adder 6, it is necessary to add all the outputs of the respective holding circuits.
It is necessary to prepare one or an adder for adding 2 × a inputs and outputting one signal. With such a configuration, for the appropriately selected positive integer a, the seventh
The same effect as that of the embodiment can be realized.

[0082]

As is apparent from the above embodiment, the present invention provides a memory for storing a waveform and a post-adder or sign reversal in the memory for storing the waveform in the modulation for limiting the band of the pulse signal by convolution addition of the impulse response waveform. By providing a signal processor and performing signal processing, it is possible to reduce the types of signals to be stored in the memory in advance, so that the required memory capacity can be significantly reduced, thereby reducing the circuit scale. Power consumption and can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a pulse modulation device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a pulse modulation device according to a second embodiment of the present invention.

FIG. 3 is a schematic block diagram of a pulse modulation device according to a third embodiment of the present invention.

FIG. 4 is a schematic block diagram of a pulse modulation device according to a fourth embodiment of the present invention.

FIG. 5 is a schematic block diagram of a pulse modulation device according to a fifth embodiment of the present invention.

FIG. 6 is a schematic block diagram of a pulse modulation device according to a sixth embodiment of the present invention.

FIG. 7 is a schematic block diagram of a pulse modulation device according to a seventh embodiment of the present invention.

FIG. 8 is a schematic block diagram of a conventional pulse modulation device.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 address generator 3a-3d memory 4a-4b selector 5a-5d holding circuit 6 adder 7 output terminal 8a-8d sign inverter 21 input terminal 22 address generator 23 memory 24 output terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 25/00

Claims (8)

(57) [Claims] In a modulation method for limiting the band of a pulse signal by convolution addition of an impulse response waveform, only one of time-symmetric combinations of waveform components to be convolution-added is calculated in advance and stored in a memory.
The signals in the memory are read from the memory in a time-divided manner.
Pulse modulation method to generate a band-limited pulse signal by the waveform components of the combinations which are symmetrical output another by adding the outputs by issuing. 2. A and generates an address in accordance with the input data address generator for outputting to the memory, a memory for storing one of the waveform components of the combination which is the time symmetry for producing a modulated output signal, memory from the memory The signal
The symmetry output by reading out by dividing in time
A selector circuit for switching each combination of signals output destination comprising a plurality of holding circuits for holding respective signals output from the selector circuit, a signal combination which are symmetrical output from said plurality of retaining circuits A pulse modulation device comprising: an adder for mutually adding and outputting. 3. A modulation method for limiting a band of a pulse signal by convolution addition of an impulse response waveform, wherein only one of time-symmetric combinations among waveform components to be convolution-added is calculated in advance, and the calculated waveform component is calculated. Of the combinations, only one of the sign-symmetric combinations is selected and stored in the memory, and the sign of the waveform output from the memory is inverted as necessary, to obtain a further symmetric combination.
2. The pulse modulation method according to claim 1, wherein the band-limited pulse signal is generated by adding and outputting the different waveforms . 4. An address generator for generating an address in accordance with input data and outputting the generated address to a memory, a memory for storing one waveform component of a time-symmetric combination for generating a modulation output signal, and an output from the memory. A signal inversion circuit for inverting the sign of the signal or outputting the signal without inversion, a selector circuit for switching an output destination of the signal output from the sign inversion circuit, and a signal output from the selector circuit. And a symmetrical output from the plurality of holding circuits.
A pulse modulator comprising: an adder for mutually adding and outputting signals of different combinations . 5. In a modulation method for limiting the band of a pulse signal by convolution addition of an impulse response waveform, k pulses (k is an integer of 2 or more) to be convolution-added are a pulses (a is an integer of 2 or more). Divides into equal blocks, calculates a response waveform due to band limitation in advance for each of the blocks, and selects only one of the calculated waveform components that is time-symmetrical in the memory for each block. stored, symmetrical output from the memory
2. The pulse modulation method according to claim 1, wherein a band-limited pulse signal is generated by mutually adding and outputting a combination of waveform components. 6. An address generator for generating an address in accordance with input data and outputting the generated address to a memory, a memory for storing one waveform component of a time-symmetric combination for generating a modulation output signal, and an output from the memory. A selector circuit for switching an output destination of a signal to be output, a plurality of holding circuits for respectively holding signals output from the selector circuit, and an addition for mutually adding and outputting signals output from the plurality of holding circuits. And a pulse modulator. 7. In a modulation method for performing band limitation of a pulse signal by convolutional addition of an impulse response waveform, k (k is an integer of 2 or more) pulses to be convolutionally added are a (a is an integer of 2 or more). Is divided into equal blocks, the response waveform due to band limitation is calculated in advance for each of the blocks, and among the calculated waveform components, only one of the sign-symmetric combinations is selected, and the selected Of the waveform components, only one of the time-symmetrical combinations is stored in the memory, the sign of the waveform output from the memory is inverted as necessary, and further added to each other to output the band-limited pulse signal. 2. The pulse modulation method according to claim 1, wherein 8. An address generator for generating an address in accordance with input data and outputting the address to a memory, a memory for storing one waveform component of a time-symmetric combination for generating a modulation output signal, and an output from the memory. A signal inversion circuit for inverting the sign of the signal or outputting the signal without inversion, a selector circuit for switching an output destination of the signal output from the sign inversion circuit, and a signal output from the selector circuit. And a symmetrical output from the plurality of holding circuits.
A pulse modulator comprising: an adder for mutually adding and outputting signals of different combinations .