KR940009963B1 - Musical scale frequence generator of electronic musical instrument - Google Patents

Abstract

The apparatus provides average pitch frequency without cento error by a simple digital circuit. The apparatus comprises: an input data buffer (1) applied with ND, DEV signal of micom, an address decoder (2) decoding the input signal, scale frequency data ROM's I (13) and II (14) finding scale frequency data correspondent to decoded signal, a presettable 2 modulus counter (15) dividing the output of the scale frequency data ROM I, a sample data counter (16) counting the signal of the scale frequency data ROM II, a relative address generator (5) generating the relative address according to RP signal.

Description

Scale generator of electronic musical instruments

1 is a block diagram of a device for generating a frequency generator of a conventional electronic musical instrument.

2 is a block diagram of a scale frequency generator of an electronic musical instrument according to the present invention.

3 is a block diagram of a sample data counter of a scale generator for electronic musical instruments according to the present invention.

4 is an error comparison diagram with an average rate frequency.

* Explanation of symbols for main parts of the drawings

1: Input data buffer 2: Address decoder

3: scale divider ratio data ROM 4: divider

5: relative address generator 6: adder

7: Absolute address generation circuit 8: Waveform data ROM

9: D / A Converter 10: Multiplier

11: Envelope Generator 12: Sound System

13, 14 scale division ratio data ROM I, II

15: Presettable 2 Modulus Counter 16: Sample Data Counter

The present invention relates to a scale generator for electronic musical instruments. Each scale frequency is minimized by a cento error with an average rate frequency, and a scale scale frequency for frequency deviation can be generated. The present invention relates to a scale frequency generator of an electronic musical instrument sound generator of a waveform data reading method which is adapted.

In the conventional scale frequency generator, the master clock fclk is divided into preset data by inputting the divider ratio data for the desired scale frequency output from the scale division ratio data ROM (3) as the preset data. After that, a reading pulse RP is output to the relative address generator 5 to obtain a scale frequency. The division ratio data ROM (3) stores division ratio data for 12 octave scales, and the division ratio data is stored for each of them by appropriately dividing each of the smaller scales into 16 pieces. X 16 = 192 bytes.

In FIG. 1, ND is note clock data, and data representing a 12th scale (C-B). DEV is a data that gives a slight frequency variation with respect to the reference frequency of each scale in order to enrich the tone of the musical instrument that is generated and to be closer to the natural musical instrument. The degree of frequency shift is determined by this data. The ND and DEV data input from the microcomputer (not shown) are once stored in the input data buffer and connected to the input terminal of the address decoder 2 for outputting the address signal of the scale factor data ROM. The address of the relative address generator is increased by one by the RP pulse, and its output is added through the absolute address generator circuit output and the adder (6) to address the waveform data ROM (8) for the desired instrument sound for one cycle. It is configured to generate waveforms at the desired scale and frequency. Referring to the operation of the prior art device as follows. When ND and DEV data are input to the input data buffer 3, they are output to the address decoder 2, and when the address signal for addressing the division ratio data table of the division ratio ratio data ROM 3 is output, the division ratio data is output. The ROM 3 outputs the selected data to the divider 4 to preset the divider 4 to the desired divide ratio.

When the master clock fclk is counted in the frequency divider 4, the RP pulse is output and input to the relative address generator 5 whenever the preset value is reached. When the RP pulse is input, the relative address generator 5 adds one by one. When the number of sample data for one cycle of the desired instrument sound waveform in the waveform data ROM 8 reaches 32, 64, 128, 256, 512, etc. By performing the repetition coefficient in the form of counting, the instrument sound waveform of the waveform data ROM 8 is sequentially read in synchronization with the RP pulse. Therefore, the desired instrument sound waveform is generated at the desired scale frequency.

F is the desired scale frequency, N is the division ratio at this time, N is the number of sample data for one period of the desired instrument sound waveform in the waveform data ROM 8 at this time, Ns is the master clock frequency input to the divider 4, and fclk. If the following equation is established.

Therefore, in order to reduce the error from the desired scale frequency fo, the Nt should be made as large as possible, so that fclk should be high.

If fclk and Ns are constant, if fo is low, it may not be a big problem, but if fo is high, the N value should be small. Therefore, the resolution of the frequency is reduced so that the error with the original average rate scale is large. There is this. The solution to this problem is to (1) increase the frequency of the master clock fclk or (2) reduce the number of samples of each sound waveform data. However, in the case of (1), it is difficult to raise the fclk enough to obtain the desired frequency resolution due to the limitation of the operating frequency and the increase of power consumption when the circuit is LSI, and in the case of (2), the shape of the instrument sound waveform is simplified. Therefore, it is difficult to implement a rich tone close to the natural instrument by reducing the sound quality of the instrument sound.

The present invention improves these problems, and does not reduce the number of instrument sound waveform samples, and does not increase the frequency of master clock fclk, and it is possible to generate a desired scale frequency with a very small mentor error, and minute frequency change in each scale. It was designed to have enough frequency resolution.

2 is a block diagram of an electronic musical instrument frequency generator according to the present invention. The input data buffer 1 receives the ND and DEV signals of the microcomputer and the address of the input signal from the output of the input data buffer 1. Divides the output of the address division ratio ROM 2 to be converted, the scale division ratio data ROMI (13) and II (14) for finding the address-converted signal as the corresponding division ratio ratio data, and the scale division ratio data ROMI (13). The presettable two modulus counter 15 which divides into N and N + 1, and the signal of the scale-division ratio data ROM II 14 are counted and applied to the presettable two modulus counter 15 as a module control signal. A sample data counter 16 and a relative address generator 5 for receiving the RP signal of the preconfigurable two modulus counter 15 to generate a relative address.

FIG. 3 is a block diagram of the sample data counter 16 of FIG. 2. The sample data counter 16 controls two A and P counters 61 and 62 which are presettable down counters and controls them. It is composed of a modulus control circuit 63. A division 61 inputs scale division ratio data A and a P counter 62 enters division division ratio data P, which is a sum of data A and data P. Is equal to the number Ns of samples for one cycle of waveform data. That is, Ns = P + A. The RP pulse is connected to the clock pulse inputs of the A counter 61 and the P counter 62, and the output terminal Co of each counter is connected to the modulus control circuit 63, and the clock pulse input of each counter is the RP pulse. Are connected, and control signals APS (A Preset) and PPS (P Preset) of the modulus control circuit 63 are connected to the A counter 61 and the P counter 62, respectively. It is a structure connected to the settable 2 modulus counter 15.

Referring to the operation of the musical instrument frequency generator of the electronic musical instrument according to the present invention, the basic configuration of the present invention by adopting the division ratio in the above formula (1) not "integer" (that is, the number with a decimal point) For example, when "fclk = 8 MHz, Ms = 32, fo = 1046.5 (Hz), the dividing ratio N is N = 238.8915432 obtained by Equation (1). Is equal to N = 239, but in the present invention, the result is equivalently divided by N = 238.906 so that the desired average is finally obtained as fo = 1046.436 (Hz) very close to the frequency fo = 1046.5 (Hz). Can be.

인데, Ns=P+A로 하고, 디바이드(Divide)N을 P-A번 수행하고 디바이드 N+1을 A번 수행한다고 하면 식(1)은The reason for this can be achieved by configuring the frequency divider with a pre-settable 2 modulus counter. In equation (1)

If Ns = P + A, Divide N is performed PA times and Divide N + 1 is performed A times, Equation (1)

As a result, in the conventional apparatus, it is impossible to dispense other than the integer ratio which is a multiple of Ns.

In the present invention, since the frequency division can be performed by any integer Nt (Nt = Np + A), the frequency resolution is naturally improved.

=238.8915…=239로 나눌 수밖에 없으나, 본 장치에서는 238로 3번 나눈뒤, 239로 29번을 나눈다면 P-A=3, A=29가 되고, P=32이므로 식(2)에서 NP+A=238×32＋29=7645=Nt가 되고 이것은 Ns=32의 공배수는 아니다. 따라서 Nt=7645가 되므로 Nt=Neq,Ns에서 등가적인 분주비 Neq는 Neq=

=238.90625가 된다. 따라서 훨씬 평균을 주파수 fo에 가까운 주파수를 얻어낼 수 있다. 이때 오차를 센토로 나타내고자For example, for fclk = 8 (MHz), Ns = 32, fo = 1046.5 (Mz), N = for conventional devices

= 238.8915... = 239, but in this device, if you divide 3 times by 238, then divide by 29 into 239, PA = 3, A = 29, P = 32, so NP + A = 238 × 32 + 29 = 7645 = Nt, which is not a common multiple of Ns = 32. Therefore, Nt = 7645, so the equivalent division ratio Neq at Nt = Neq, Ns is Neq =

= 238.90625. Therefore, we can obtain a frequency much closer to the frequency fo. To express the error in cento

(F1: average frequency, f2: frequency obtained by dividing)

As shown in FIG. 4, in the case of the C6 scale, the error of the conventional device is about 0.83C or -0.17C by the present invention, and in the case of C6 ^*, the error is considerably smaller, such as + 3.74 ￠ or -0.16 ￠. .

Accordingly, the operation of the scale frequency generator of FIG. 2 will be described.

Once the scale frequency information ND and the frequency shift information DEV are input from the microcomputer, they are stored in the input data butter (1), and the address decoder (2) uses the scale division ratio data ROM I (13) and ROM II (14) by ND and DEV. ) The division data P and A are input to the preconfigurable 2 modulus counter 15 and the sample data counter 16 by converting the data into address data for reading out and outputting them. When this preset data is input to the preset terminal of the counter 15, the master clock fclk is immediately counted, first divided by N + 1 by the modulus control signal MC from the sample data counter 16. When the master clock fclk counts N + 1, the RP pulse is output once. When A divided by N + 1, the modulus control signal MC from the sample data counter 16 is converted so that the counter 15 starts dividing by N, starts dividing by N, and then divides by N, PA again. Counters 61 and 62 in (16) are loaded with control signals APS and PPS by A and P values by modulus control circuit 63, and MC signals are pre-settable 2 modulus counters 15 again. ) Is converted to perform divide (N + 1) so that the preconfigurable 2 modulus counter 15 repeatedly performs the operations of divide (N + 1) and divide (N) so that the RP signal is continuously output and the relative address generator As input to (5), the selected instrument sound waveform stored in a predetermined area in the waveform data memory is sequentially read to generate an instrument sound of a desired scale frequency.

Therefore, the device according to the present invention can be used without increasing the basic clock frequency or reducing the number of samples for one cycle of the sound wave data, that is, without increasing the operation speed and power consumption or degrading the quality of the sound when LSI is used. With simple digital circuit configuration, the desired average rate frequency can be achieved with little sento error, and the frequency resolution is improved, allowing 16 steps between each scale (response) to give a frequency shift to obtain rich and natural musical instrument sound. The frequency divided by the degree can be easily obtained.

Claims (2)

The input data buffer 1 to which the microcomputer ND and DEV signals are applied, the address decoder 2 for converting the address of the input signal from the output of the input data buffer 1, and the address-converted signal Presettable two modulus counters for dividing the division of the division ratio data ROM I (13) and II (14) found by non-data and the division of the division ratio data ROM I (13) with divide N and divide N + 1. (15), a sample data counter 16 for counting the signal of the scale division data ROM II (14) and applying it as a modulus control signal to the preconfigurable two modulus counter 15; It consists of a relative address generator (5) which receives the RP signal of the counter (15) and generates a relative address. The first division data (N) is input to the presettable modulus counter (15) as preset data, and the second division data. P and A are samples Preset data is input to the other counter 16 to change the division ratio of the preconfigurable two modulus counter 15 according to the modulus control signal MC of the sample data counter 16 so that it can be divided at any integer ratio. Scale frequency generator of the electronic musical instrument, characterized in that the configuration. The apparatus of claim 1, wherein the sample data counter (16) comprises an A counter (61), a P counter (62), and a modulus control circuit (63).

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