JP3073048B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for driving an analog device, and more particularly to a high power digital output circuit for generating a high power digital signal for driving an analog device such as an audio speaker through a suitable filter circuit.

[0002]

2. Description of the Related Art Digital power amplifiers, which can provide high-quality reproduced audio signals from digital systems, have been increasingly used in, for example, audio amplifiers. The use of a digital power amplifier eliminates analog signal processing from all audio systems except for the last stage that drives audio speakers. This allows
Ideally reproduces and processes audio signals without the distortion and noise inherent in analog audio systems. Such a digital power amplifier is particularly suitable for reproducing an audio signal from a digital signal source such as a digital audio disc player or a digital tape recorder which generates an output audio signal in the form of digital information.

FIG. 9 shows an example of a digital audio system.

Referring to FIG. 9 , a digital signal source 1 supplies a digital output signal to a demodulator 3 via an optical fiber cable 2. In response, the demodulator 3 reproduces a pulse code modulation (PCM) signal. Converter 4
When a PCM signal is supplied, a PWM signal and its logically inverted value are simultaneously generated and supplied to the digital drive circuit 5. The digital drive circuit 5 drives the drive output circuits 6a and 6b each comprising a pair of high power MOS transistors connected in series between the voltage source V _CC and the ground plane V _EE . The output circuits 6a and 6b are driven complementarily,
a output circuit 6b to generate the output current voltage V _CC output circuit 6a to generate the output current ground level V _EE, and the circuit 6b voltage V _CC becomes the ground level. The output circuits 6a and 6b drive the speaker 8 via low-pass filters 7a and 7b for smoothing the pulse width modulation signals supplied from the output circuits 6a and 6b, respectively.
As a result, a high power amplitude modulated signal whose amplitude changes above and below the level V _CC / 2 is obtained from the speaker 8. Figure
10 shows a configuration of a conventional drive circuit 5 including MOS output circuits 6a and 6b.

Referring to FIG. 10 , drive circuits 11a and 11b respectively include a PWM signal D and a logically inverted value thereof.

[0006]

(Equation 1)

Are supplied to input terminals T _i1 and T _i2 . The driving circuit 11a is a bipolar transistor _Tr3.
Output terminal connected to the base of the drive circuit 11b
_Has a connection to an output terminal connected to the base of another bipolar transistor _Tr4 . Transistors _Tr3 and _Tr4
Is connected in series between the voltage source V _CC and the ground level V _EE ,
Transistor T _r3 is an emitter connected to the collectors of the transistors T _r4 connected to a voltage source V _CC. The transistor T _r4 has been connected to the ground plane V _EE emitter. Similarly, input terminals T _i3 and T
_The drive circuits 11c and 11d connected to the _i4
M signal

[0008]

(Equation 2)

And a non-inverted PWM signal D. The drive circuit 11c has an output terminal connected to the base of a bipolar transistor _Tr5 , and the drive circuit 11d has an output terminal connected to the base of another bipolar transistor _Tr6 . The transistors _Tr5 and _Tr6 are connected to the voltage source V
_CC and is connected in series between the ground plane V _EE, the transistor T _r5
The collector is connected to a voltage source V _CC and the transistor T _r6
Having an emitter connected to the collector of Transistor T _r6 has been connected to the ground plane V _EE emitter.

[0010] The output circuit 6a and 6b, the power MOS transistor T _r1 connected in series between a voltage source V _CC and V _EE
And has a T _r2, MOS transistor T _r1 is a voltage source V _CC
A drain connected, and a source connected to the drain of the MOS transistor T _r2 on, the MOS transistor T _r2 has a source connected to the ground plane V _EE. In addition, the transistor T _r1 is, bipolar transistor T _r3
And the emitter of which is connected to the node n ₁ whose collector is connected to the bipolar transistor T _r4, transistor T _r2
It is connected to the node n ₂ to the collector of the emitter and the transistor T _r6 of the transistor T _r5 is connected. Node n ₃ which is connected to the drain of the source and the transistor T _r2 of the output of the output circuit 6a and 6b transistor T _r1
From the output terminal T ₀ connected to

In the conventional driving circuit, the transistors _Tr3 and _Tr4 are provided with complementary input signals D and

[0012]

(Equation 3)

[0013] In response to the signal, the transistor turns on and off complementarily. That is,
When the transistor _Tr3 is on, the transistor _Tr4 is off and vice versa. Similarly, transistors _Tr5 and _Tr6 provide complementary input signals D and

[0014]

(Equation 4)

[0015] In response to the above, it turns on and off complementarily. That is,
When the transistor _Tr5 is on, the transistor _Tr6 is off, and vice versa. As described above, when the transistor _Tr3 is turned on in response to the high-level signal at the input terminal _Ti1 , the transistor _Tr4 is turned off in response to the low-level signal at the input terminal _Ti2 . Thus, appeared high level signal to the node n _1, MOS transistor T _r1 is turned on in response thereto. In response to the high level signal at input terminal T _i1, the low level signal input terminal T _i3, appear on the high level signal input terminal T _i4, transistor T _r6 is between transistors T _r5 ON is turned off. Thus, it appeared low level signal at node n _2, turned off the transistor T _r2 is in response thereto. In this way, a large output current obtained at the output terminal T _0. On the other hand, the input terminals T _{i1 to} T _i1
When the logic state of the signal at _i4 is inverted, the transistor _Tr3
Is turned off, the transistor _Tr4 is turned on, the transistor _Tr5 is turned on, and the transistor _Tr6 is turned off. As a result, the transistor T _r1 is the transistor T _r2 turned off is turned on. Thereby, the output terminal T ₀ is grounded and no output current is available therefrom. Desired output current is obtained by smoothing the PWM output current at the output terminal T ₀ in the filter circuit.

[0016]

However, the conventional driving circuit 5 has the following problems. That is, the gate voltage of the transistor T _r1 and T _r2 are inverted, both transistors T _r1
And _Tr2 may be turned on depending on their characteristics. Then, a through current flows from the voltage source V _CC to the ground plane, causing distortion in the reproduced audio signal, and increasing the power consumption of the amplifier. Of course, the distortion of the reproduced audio signal causes a deterioration in the quality of the reproduced sound, and the increased power consumption is a serious problem in a battery driven system such as a portable audio system.

Accordingly, it is a general object of the present invention to provide a new and useful digital drive circuit that solves the above-mentioned problems.

Further, the present invention provides a digital drive capable of outputting a high power digital drive signal in response to a digital input signal, driving an analog device with a large output, reducing power consumption, and obtaining an analog signal without distortion. It is another object to provide a circuit.

[0019]

The present invention solves the above problems,
Intersects a first logic level with a lower second logic level
A first input terminal for receiving one another take the input logic signal, before
A second input terminal for receiving a logically inverted value of the input logical signal
A first voltage source for supplying a first drive voltage;
A second voltage for supplying a second drive voltage different from the drive voltage;
The input logic signal is connected in series between the
A logically inverted value is supplied from the first and second input terminals, respectively.
And the first and second trucks that are turned on and off in response thereto.
Transistor and a third voltage source for supplying a third drive voltage
And supplying a fourth drive voltage different from the third drive voltage.
Connected in series with a fourth voltage source,
The signal and its logical inversion are sent to the first and second input terminals.
And a third and a third respectively supplied and turned on and off in response thereto.
A fourth transistor, wherein the first transistor
Is on, the second transistor is off, and
The first transistor is turned on when the second transistor is on.
The first and second transistors so that the star is turned off.
The star responds to the input logic signal and its logically inverted value.
On and off, and when the third transistor is on,
The fourth transistor is turned off and the fourth transistor is turned off.
The third transistor is turned off when the star is turned on
As described above, the third and fourth transistors are connected to the input terminal.
Turned on and off in response to a logic signal and its logical inverse, yet a
A fifth voltage source for supplying a fifth driving voltage and a sixth driving voltage
With a sixth voltage source different from the fifth drive voltage that supplies
Connected in series, and the first transistor is turned on.
A first power transistor that is turned on when the
The second power that turns on when the third transistor turns on
Transistor and the second power transistor.
And the second power transistor detects an on-off state.
After detecting that it has been turned off, the first transistor is turned off.
A first drive control circuit for shifting to the ON state, the first
Detecting the on / off state of the power transistor of
Detected that 1 power transistor was turned off
After that, the second transistor that causes the third transistor to transition to the ON state
It consists of a drive control circuit and supplies input digital signals.
Output digital signal with increased output power.
An output circuit for generating, wherein the first transistor is
A collector connected to the first voltage source, and an emitter
Based on an input digital signal from the first input terminal.
A first bipolar comprising a signal supplied base
A second transistor, wherein the second transistor is
Collector connected to the emitter of one bipolar transistor
An emitter connected to the second voltage source;
The logical inversion value of the input digital signal from the second input terminal
A second base comprising a base supplied with a signal based on
A polar transistor, wherein the third transistor is
A collector connected to the third voltage source, and an emitter
Based on an input digital signal from the second input terminal.
A third bipolar comprising a base to which a signal is supplied
A fourth transistor, wherein the fourth transistor is
3 connected to the emitter of the bipolar transistor
An emitter connected to the fourth voltage source;
A signal based on the input digital signal from the first input terminal;
Bipolar transistor consisting of a base supplied with
And the first power transistor comprises:
A drain connected to a fifth voltage source;
A gate connected to the emitter of the polar transistor,
A first MOS transistor serving as a source,
The second power transistor is connected to the first MOS transistor.
A drain connected to the source of the transistor;
Gate connected to emitter of bipolar transistor
And a source connected to the sixth voltage source.
The first drive control.
The circuit is connected to the base of the first bipolar transistor.
Connected collector and the emitter connected to the second voltage source
A fifth bipolar transistor having
The second drive control circuit is the third bipolar transistor
And a collector connected to the base of
Sixth bipolar transistor with connected emitter
The problem is solved by an output circuit comprising a resistor .

[0020]

According to the present invention, first and second power MOSs are provided.
The transistors are prevented from being turned on at the same time, and the problems of distortion of the reproduction signal and excessive power consumption are eliminated.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described with reference to FIGS. FIG. 1 shows a main part of the first embodiment, and FIG. 2 shows a main part of the second embodiment.

In this embodiment, the transistors _Tr4 and _Tr6
Of the control transistors TC ₂ and TC
Released by _one .

FIG. 1 is a diagram corresponding to FIG. 10 showing a conventional configuration.
But the transistor T_r6Supply the base potential of
1 control transistor TC₁Having. This first control
Transistor TC₁Is the transistor T_r3Connect to the base of
Collector and ground plane V _EEWith the emitter connected to
Having. Transistor TC₁Is the first inversion
Bipolar transistor T via circuit 12a_r6Bee
Connected to the transistor TC₁Is a tran
Jista T_r6In response to the base voltage of the inverter circuit 12a.
It is driven with a delay. Transistor TC₁Turned on
Then, the driving circuit 11a_r3Turn on
Transistor T_r3Is a tran
Gista TC₁Is turned off by Similarly, Transis
T_r5Collector and ground plane V connected to the base of_EETo
Connected inverting circuit 12b
Through the transistor T_r4Base connected to the base of
Transistor TC having_TwoIs provided. This
Transistor TC_TwoIs the transistor T_r4Base phone
Driven by the inverting circuit 12b in response to the voltage
You. At that time, the transistor TC_TwoTurns on when
The circuit 11c is a transistor T_r5Turn on the output current
Transistor TC even when generated_TwoIs the transistor T_r5
Turn off.

For example, when the logic level of the input information D changes from high level to low level, the input signals supplied to the input terminals T _i1 and T _i4 change from high level to low level, and the input terminals T _i2 and T _i3. Changes from the low level to the high level. In response, the driving circuits 11a and 11d generate high-level signals, and the driving circuits 11b and 11c generate low-level signals. Further, the transistor _Tr4 is immediately turned off in response to the low level output of the drive circuit 11b. Then, since the transistor _Tr6 is immediately turned on, the power MOS transistor _Tr2 is turned off.

On the other hand, when the logic level of the input signal to the input terminals T _{i1 to} T _i4 changes, the base voltage of the transistor TC ₁ is high due to the delay caused by the inversion circuit 12a. Thus, the transistor TC ₁ will then turn off keeping while on state. During transistor TC ₁ is on, the base current through the transistor TC ₁ escapes into the ground, the transistor T _r3 is turned off. Thus, the voltage at the node n ₁ becomes low during this time, and the power MOS transistor TC ₁ remains off. After transistor TC ₁ is the period, i.e. viewed transistor T _r3 when turned off after detecting that the transistor T _r6 is turned is turned on, MOS transistor T _r1 is turned on.

Similarly, if the input signal is input terminals T _{i1 to} T _i4
Base voltage between the transistor TC ₂ sent to remains low. Thus transistor TC ₂ is turned on at the time interval corresponding to the delay through the subsequent inverting circuit 12b turns off has elapsed. However, the transistor T _r5 in response to the high level at the input terminal T _i3 since off, the operation of the transistor TC ₂ does not substantially alter the circuit 10. The voltage level of the thus node n ₂ is between the input terminal T _i3 high is low, the power MOS transistor T _r2 is turned off. During the operation, the power MO
S transistor T _r1 is the output current turns on the output terminal T
Before obtained from ₀ both transistors T _r1 and T _r2 there is a moment when turned off. Therefore, it is possible to prevent a through current from flowing from the voltage source V _CC to the ground plane V _EE .

The above operation is performed when the level at the input terminals T _i1 and T _i4 changes from a low level to a high level, and when the level at the input terminals T _i2 and T _i3 changes from a high level to a low level. Since this also applies, repeated description will be omitted.

FIG. 2 shows a main part of the second embodiment. This embodiment
Then, contact n₁And n_TwoThe voltage at each
Gista TC_Four, TC_ThreeIs detected by Transistor
TC_FourIs the transistor T_r5Collection connected to the base of the
And a grounded emitter. Specifically, the contact
n₁And a voltage divider DIV1 connected across the ground.
The transistor TC_FourIs the contact of the voltage divider DIV1
Having a connected base. Note that the resistors Rx and Ry
Are connected to each other in series. Similarly, the transistor T
_r3Collector and emitter connected to the base of the
Control transistor TC having_ThreeIs provided
You. Further, the transistor TC_ThreeIs the node n_TwoAnd the ground plane
With base connected across to voltage divider DIV2
You. Specifically, the voltage divider DIV2 is connected to the node n _TwoAnd ground
It has resistors Rx 'and Ry' connected in series between
Transistor TC _ThreeThe resistance of Rx 'and Ry'
Connected to the contacts of the connected voltage divider DIV2
You.

Transistor TC_ThreeIs a power MOS transformer
Jista T_r2Threshold level substantially smaller than the threshold level of
Transistor TC_FourIs a power MOS transistor
Star T_r1Threshold level substantially smaller than the threshold level of
Having. Therefore, the power MOS transistor T_r2But
When the transistor TC_ThreeIs the transistor T _r2
It turns on at the timing of turning on before turning on.
Similarly, the power transistor T_r1Is turned on, the tiger
Transistor TC_FourIs the transistor T_r1Actually turns on
Turn on before. Transistor TC_ThreeResponds to the on
And the transistor T_r3Is turned off and the power MOS transistor
Transistor T_r2Before the power is turned on
T_r1Turns off. Also, the transistor TC_FourIs on
, The transistor T_r5Turns off,
Power MOS transistor T_r1Before the power is turned on
MOS transistor T_r2Turns off. As a result,
Power MOS transistor T_r1And T_r2Are turned on at the same time
Can be prevented, and the shoot-through current is_CCFlows from to the ground
Can be effectively prevented.

Next, a first embodiment of the present invention will be described with reference to FIG.
Will be explained. Referring to FIG. 3, the drive circuit includes a circuit 10.
Represents the power MOS transistor T _r1Driving the first
Drive unit 2a and power MOS transistor T_r2Drive
A second driving unit 2b. In the first drive unit 2a
Input terminal T_i1The input signal D at_CCConstant power
Collector and ground plane V connected via flow source 3a_EEContact
NPN transistor T with a continuous emitter_r11of
Supplied to the base. Transistor T_r11Is Darling
Ton pair with transistor T_r3NPN transistors formed with
T_r12Through the transistor T_r3Drive. here
And the transistor T_r12Is the transistor T_r11Collection of
And the voltage source V_CCCollection connected to
And the transistor T_r3Emitter connected to the base of
Having. Further, the diode D is connected to the transistor T_r12of
Emitter and base are connected by transistor T_r12To the emitter
Connected anode terminal and transistor T_r12Base of
Are connected by the cathode terminal connected to. Similarly,
Force signal

[0031]

(Equation 5)

To obtain an input terminal T _i2 via a resistor R _2.
And a voltage source V via a constant current source 3b.
An NPN transistor _Tr13 having a collector connected to _CC and a grounded emitter is provided. Transistor T _r13 drives the transistor T _r4 through the NPN transistor T _r15 which form the transistor T _r4 Darling ton pair. Thus, the transistor T
_r15 has a collector connected to the collector of the transistor T _r4, an emitter connected to the base of the transistor T _r4, and a base connected to the collector of the transistor T _r13. Furthermore, the transistor T _r15 is connected to the emitter of the transistor T _r12 through the resistor R _1. In addition to the driving transistor T _r13, a base connected to an input terminal T _i2 through the resistor R _3, the transistor T
Another driving transistor T _r14 having a base connected to a collector of _r4 and the connected to the ground plane V _EE emitter is also provided.

The same configuration is provided for the drive section 2b. The transistors _{Tr21 to Tr25} are the transistors _Tr21.
r11 or respectively corresponding to T _r15.

As described above, the second driving section 2b outputs the input signal

[0035]

(Equation 6)

An NPN transistor having a base connected to the input terminal T _i3 for receiving the signal, a collector connected to the voltage source V _CC via the constant current source 3b, and an emitter connected to the ground plane V _EE. It has _Tr21 . Transistor T _r21 transistor via the NPN transistor T _r22 which form the transistor T _r5 Darling ton pair T _r5
Drive. Here, the transistor _Tr22 has a base connected to the collector of the transistor _Tr21 and a voltage source V _CC.
And an emitter connected to the base of transistor _Tr5 . Further, the transistor T
The connected cathode terminal to the anode terminal and the base of the transistor T _r22 connected to the emitter of the _r22 diode D for connecting the emitter and base of the transistor T _r22 is provided.

Similarly, a base connected to input terminal T _i4 via resistor R ₇ to receive input signal D, a collector connected to voltage source V _CC via constant current source 3b,
NPN transistor T having a grounded emitter
_r23 is provided. Transistor T _r23 drives the transistor T _r6 through the NPN transistor T _r25 which form the transistor T _r6 Darling ton pair. Thus, having a collector transistor T _r25 is connected to the collector of the transistor T _r6, an emitter connected to the base of the transistor T _r6, and a base connected to the collector of the transistor T _r23. Further, the transistor T
The collector of the _r25 is the resistance through the R ₆ transistor T _r22
Is connected to the emitter, the emitter of the transistor T _r25 is grounded via a resistor R _9. In addition to the driving transistor T _r23, another having a base connected to an input terminal T _i2 via a resistor R _8, a collector connected to the base of the transistor T _r6, and is connected to the ground plane V _EE Emitter Transistor _Tr24 is provided.

The object to achieve the present invention, the power MOS transistor T _r1 and for T _r2 is prevented from simultaneously turned on, the bipolar transistor T _r18 via the resistor R ₄ is connected to the base of transistor T _r15 Is provided. Transistor T _r18 further has a collector connected to a voltage source V _CC via the constant current source 3c, a grounded emitter. Thus, the transistor T _r18 is turned on in response to the base voltage of the transistor T _r15, the level of the collector of the transistor T _r18 transistor T _r18
Changes to low after a delay corresponding to the above operation. Transistor T _r18 is another having a base connected to the collector of the transistor T _r18, a collector connected to the base of the transistor T _r22, and a grounded emitter NPN
The transistor _Tr17 is driven. Thus, the transistor T _r17 is turned off when the transistor T _r16 is turned on,
_Turns on when the transistor _Tr16 is off. Transistor T _r17 is when on also the base current of the transistor T _r22 and T _r5 directly, even through the diode D absorbs, transistor T _r22 and T _r5 regardless of the voltage level of the collector of the transistor T _r21 both Turn off.

Similarly, the driving section 2b includes a transistor T
_r25Resistance R at the base of_TenHas a base connected through
Bipolar transistor T_r28Having. Transi
Star T _r28Is further connected to a voltage source V via a constant current source 3c '.
_CCWith a collector connected to the ground and an emitter grounded
You. Therefore, the transistor T_r28Is the transistor T_r25
Is turned on in response to the base current of
_r28The collector level of the transistor T_r28Suitable for
Lower by delay. Transistor T_r28The Transis
T_r28Base connected to the collector of the transistor
T_r12Collector connected to the base of the
Another NPN transistor T having an emitter _r27Drive
Move. Therefore, the transistor T_r27Is the transistor T
_r26Is turned off when is turned on, and the transistor T_r26
Is turned on when is turned off. When on, Transis
T_r27Is the transistor T_r12And T_r3Base current
Absorbed directly or through diode D, the transistor T
_r12And T_r3Are both transistors T_r11Collector's power
Turns off regardless of pressure level.

FIGS. 4A to 4J are time charts showing the operation of each part of the circuit 10. FIG. Here, FIG.
Indicates input information D supplied to the input terminals T _i1 and T _i4 . FIG. 4B shows input information supplied to input terminals T _i2 and T _i3.

[0041]

(Equation 7)

Is shown. FIG. 4C shows the input terminal T _i4
Transistors T _r25 and T _r25 generated in response to signal D at
_This shows the timing of _{turning on} and off _r6 . As shown in FIG. 4 (C), on-off of the transistor T _r25 and T _r6 is consistent with the rise and fall substantially input information D.

On the other hand, FIG. 4 (D) shows the on-off timing of transistor T _r27 responsive to the base voltage of the transistor T _r25. As shown in FIG. _4D , there is a delay in _turning on and off the transistor _Tr27 , and such a delay is caused by the operation of the transistor _Tr28 . The transistor T _r28 drives the transistor T _r27 and detects the base voltage of the transistor T _r25. When the input information D returns to a low level corresponding to the fall of the waveform of FIG. 4A, the transistor _Tr23 turns off and the voltage level of the collector of the transistor _Tr23 goes high.
In response, transistor _Tr28 turns on and transistor _Tr27 turns off after the delay shown in FIG.

The transistor T _r27 is transistor T _r12
And base transistors _Tr3 and _Tr3 are turned off in response to the high level of the input signal D,
Even if the input signal D returns to the low level in the falling state of FIG. 4A, _r12 and _Tr3 remain off during the period shown in FIG. Transistor T as a result the power MOS transistor T _r1 is shown in FIG. 4 (F)
_r12 and T _r3 does not turn on until it is turned on in response to the off of the transistor T _r27. At that time, the transistor T
_r1 responds to the rise of the input signal D in FIG. 6A corresponding to the fall of the input signal D shown in FIG.
The input signal D is a transistor _Tr4 and a transistor _Tr13.
The control is immediately turned off by the control by _Tr15 .

FIG. 4G shows transistors _Tr4 and _Tr15.
The state of is shown. As shown in the figure, the turning on and off of these transistors occur substantially in synchronization with the input signals D and D shown in FIGS. 4A and 4B. Further, FIG. 4 (H) shows the operation of the transistor T _r17 in response to the base voltage of the transistor T _r15. As shown in FIG.
The transistor _Tr15 operates with a delay with respect to the input signals D and D in (A) and (B). This is because the transistor _Tr16 that actually drives the transistor _Tr17 operates with a delay.

FIG. 4I shows the input signal at the input terminal T _i3.

[0047]

(Equation 8)

[0048] showing the operation of the transistor T _r22 and T _r5 in response to. As shown in FIG.
_r22 and T _r5 transistors T _r17 is off during the on. When the transistor T _r17 is turned off, the transistor T _r22 and T _r5 is turned on, the input signal shown in FIG. 4 (B)

[0049]

(Equation 9)

Turns off substantially in response to the rise of
You. Transistor T_r22And T_r5Power in response to
-MOS transistor T_r2Is shown in FIG. 4 (J).
Turn off. Power MOS transistor T_r1Shows the operation of
FIG. 4F shows the power MOS transistor T_r2Of it
Compared to FIG. 4J, the transistor T_r1And T
_r2Are both transistors T_r18And transistor T_r28
Notice that there is an interval to turn off in response to the delay caused by
Good. Therefore, as described with reference to FIG.
Transistor T_r1And T_r2Are not turned on at the same time.

FIG. 6 is a detailed circuit diagram of the second embodiment corresponding to FIG.

In this circuit, the MOS transistor T_r1No
The gate voltage is the resistance R₃₁And R₃₂Voltage divider including series connection of
Through the NPN transistor T_r31Detected by
You. Transistor T_r31Is the transistor T_r22Base of
With a collector connected to the ground and an emitter grounded
You. Therefore, the MOS transistor T_r1Is turned on
MOS transistor T_r1Gate voltage rises
Star T_r31Turns on and the transistor T_r22as well as
T_r5Turns off. Similarly, a resistor R connected in series ₃₃Passing
And R₃₄MOS transistor T via a voltage divider including_r2of
NPN transistor T for detecting gate voltage_r32Provided
Can be Transistor T_r32Is the transistor T_r12No
The collector connected to the ground and the grounded emitter
Have. Transistor T_r32Is the transistor T_r2Game
Transistor T in response to an increase in_r12And Tran
Jista T_r3Turn off.

FIGS. 7A to 7D show time charts of the circuit operation of FIG. Figure 7 (A) shows the transition of the gate voltage of the power MOS transistor T _r1 at node TOa. Figure 7 (C) shows the transition of the gate voltage of the power MOS transistor T _r2 of the node TOB. In FIG. 7A,
The threshold level for OFF of the power MOS transistor T _r1 is expressed by V _THa. Similarly, power MOS
The threshold level of the transistor T _r2 is expressed by V _THb.

Here, the transistor T_r31Action
The threshold level is_raThe MOS transistor shown in FIG.
Transistor T_r1It is set lower than that of. As well
And the transistor T_r32The threshold level for the operation of
Line V_rbThe MOS transistor T shown in FIG._r2Noso
It is set lower than this. This allows the transition
Star T_r317 (B) showing the operation of FIG.
As shown, the power MOS transistor T_r1Is on
When low level (V_EE) To high level (V _CCContact
When the voltage level of the point TOa changes, the transistor T_r31
Is the transistor T_r1Is turned on before it is turned on.
You. Similarly, the voltage level of the contact point TOb is low (V
_EE) To high level (V_CC) Increases to Transis
T_r32Is turned on as shown by the rising edge in FIG.
And the power MOS transistor T _r2Is the transistor T
_r32Turns on after is turned on.

While the transistor _Tr32 is on, the power M
OS transistor T _r1 is not accustomed to on. Therefore, the power MOS transistor T _r1 is turned off by the transistor T _r32 before transistor T _r2 is turned on. Similarly, while the transistor T _r31 is on the power MOS transistor T _r2 can not become ON. Thus, transistor T _r2 is turned off by the transistor T _r31 before transistor T _r1 is turned on. Therefore, even if there are variations in the threshold of the circuit constant or a transistor, a power MOS transistor T _r1 and T _r2 are never turned on simultaneously.
Further, a through current never flows through the transistor T _r1 and T _r2.

FIG. 7 shows a modification of the circuit of FIG. In the figure
As shown, the transistor responds to the voltage at the contact TOa.
T_r12And T_r3NPN Transistors to turn off
T _r33And T_r34Is provided. Transistor T
_r33Is the resistance R₃₁And R₃₂Is the voltage level at the contact point TOa
Connect to the contacts of the voltage divider connected together to detect
And the voltage source V via the constant current source 3d._CCTo
Having a connected collector and a grounded emitter
You. On the other hand, transistor T_r34Is the transistor T _r33of
A base connected to the collector and a transistor T_r12of
A collector connected to the base and a grounded emitter
Having.

Transistor T_r34Is low at contact point TOa
It turns on in response to the voltage level, and the input terminal T_i1Input
Is high level and the supplementary input terminal T_i2Input is low level
Transistor T between_r12And T_r3Turn off. Input end
Child T_i1And T_i2When the signal level at
Star T_r34Is the transistor T_r33Respond to delays caused by
While on, the transistor T_r12And T_r3Turns on immediately
Prohibit becoming. Transistor T_r15And T_r4Is off
Transistor T only when_r12And T_r3Is on
I can be. Thereby, the transistor T_r3And T_r4Waste electricity
The characteristic of the circuit shown in FIG.
It is intended to improve power consumption. Input terminal T_i1as well as
T_i2When the input signal level at
T _r12And T_r3Is immediately turned off and the transistor T
_r15And T_r4Turns on. Here, the transistor T
_r34Is turned on with a delay. In this case, the transistor T
_{r3 Four}Transistor T_r12And T_r3Ha
It remains.

[0058] transistor T _r35 and the transistor T _r36 to transistor T _r5 and T _r6 is prevented from simultaneously turned on is provided in the driver unit 2b. The operation of this circuit is the same as that described above, and a duplicate description will be omitted. FIG.
According to the circuit of saving the power consumption of the output circuit, the power MOS transistor T _r1 and T _r2 are never turned on simultaneously.

If the output circuits of FIGS. 5 to 7 are used, FIG.
Power consumption of the digital audio system of the present invention can be saved and higher sound quality can be obtained than the system. Further, the output circuit is not limited to a digital audio system. For example, it can be used to drive an electric motor or an electromagnetic actuator with low power consumption.

[0060]

According to the present invention, it is possible to reliably prevent the power MOS transistors from being turned on at the same time, to reduce the power consumption, and to reduce the distortion in the output signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a main part of a second embodiment according to the present invention.

FIG. 3 is a detailed circuit diagram showing a driving circuit of a first embodiment according to the present invention.

FIG. 4 is a time chart illustrating the operation of the transistor in the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a modification of the circuit of FIG. 3;

FIG. 6 is a detailed circuit diagram showing a driving circuit according to a second embodiment of the present invention.

FIG. 7 is a time chart illustrating the operation of the transistor in the circuit of FIG. 5;

FIG. 8 is a diagram showing a modification of the circuit of FIG. 6;

FIG. 9 is a block diagram showing a configuration of a digital audio system according to the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional digital drive circuit used in the audio system of FIG.

[Explanation of symbols]

Reference Signs List 1 digital signal source 2 optical fiber cable 3 modulator 4 converter 5 digital drive circuit 6a, 6b output circuit 7a, 7b low-pass filter 8 speaker 10 circuit 11a, 11b, 11c, 11d drive circuit _Ti1 , _Ti2 , _Ti3 , T _i4 input terminal V _CC voltage source V _EE ground plane _{T r1, T r2, T r3} , T r4, T r5, T r6 transistor _{T r11, T r12, T r13} , T r14, T r15 transistor T _r16, T _r17, T _r18, T _r19, T _r20 transistor _{T r21, T r22, T r23} , T r24, T r25 transistor _{T r26, T r27, T r28} , T r29, T r30 transistor _{T r31, T r32, T r33} , T r34 , T _r35 transistor T ₀ the output terminal n _1, n _2, n ₃ contacts TC _1, TC ₂ control transistors D, D input information DIV1, DIV2 voltage divider Rx, Ry, Rx ', Ry ' resistance _{1, R 2, R 3,} R 4, R 5 resistors _{R 6, R 7, R 8} , R 9, R 10 resistors

──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Toshio Hanazawa 2-844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd. (56) References JP-A-1-309414 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 17/567 H03K 17/16 H03F 3/217

Claims (8)

(57) [Claims] A first logic level and a lower second logic level;
First receiving an input logic signal that alternates logic levels
An input terminal and a second input terminal for receiving a logically inverted value of the input logic signal
And a first voltage source for supplying a first drive voltage; and a first drive
A second voltage source for providing a second drive voltage different from the voltage
And the input logic signal and its logic
Inverted values are supplied from the first and second input terminals, respectively.
And the first and second transformers that turn on and off in response thereto.
A third drive, a third voltage source for supplying a third drive voltage, and a third drive
A fourth voltage source for supplying a fourth drive voltage different from the voltage
Between the input logic signal and the logic
Logical inversion is supplied from the first and second input terminals, respectively.
And the third and fourth transformers which are turned on / off in response thereto.
A second transistor when the first transistor is on.
The transistor is turned off and the second transistor is turned on.
Sometimes, the first transistor is turned off.
First and second transistors are connected to the input logic signal and the input logic signal.
On and off in response to the logical inversion value of the fourth transistor when the third transistor is on.
The transistor is turned off and the fourth transistor is turned on.
Sometimes, the third transistor is turned off.
Third and fourth transistors are connected to the input logic signal and the input logic signal.
On and off in response to the logic inversion of
And a fifth voltage source for supplying the sixth drive voltage.
5 connected in series with a sixth voltage source different from the drive voltage.
To be turned on when the first transistor is turned on.
A first power transistor and the third transistor
Second power transistor that turns on when the star turns on
And the on / off state of the second power transistor is detected.
And that the second power transistor has been turned off.
Is detected, the first transistor is turned on.
A first drive control circuit to be turned on and an on / off state of the first power transistor detected
And that the first power transistor is turned off
Is detected, the third transistor is turned on.
And a second drive control circuit for
Output digitized with increased output power
An output circuit for generating a ground signal, wherein the first transistor is connected to the first voltage source.
Input from the first input terminal.
A base to which a signal based on a force digital signal is supplied.
The first bipolar transistor, and the second bipolar transistor
Of the first bipolar transistor
A collector connected to the emitter and a second voltage source;
Connected to the input terminal from the second input terminal.
Base supplied with a signal based on the logically inverted value of the digital signal.
In front of the second bipolar transistor
The third transistor is connected to the third voltage source.
A collector, an emitter, and an input from the second input terminal
Digital signal based signal supplied base and more
A third bipolar transistor, and the fourth bipolar transistor
The transistor is an emitter of the third bipolar transistor.
And a collector connected to the fourth voltage source
And the input digital signal from the first input terminal.
The signal is based on the ground signal
4 bipolar transistors, wherein the first power
A transistor connected to the drain connected to the fifth voltage source;
And the emitter of the first bipolar transistor
A first MOS transistor comprising a connected gate and a source
The second power transistor comprising a transistor.
Is connected to the source of the first MOS transistor.
Drain and the emitter of the three bipolar transistors.
And a gate connected to the sixth voltage source.
Of the second MOS transistor comprising the source
And the first drive control circuit includes a first bipolar transistor.
A collector connected to the base of the transistor and a second voltage source
Bipolar transistor having an emitter connected to
And the second drive control circuit is connected to the third drive control circuit.
Collector connected to base of bipolar transistor
And an emitter connected to the fourth voltage source.
An output circuit including a sixth bipolar transistor. 2. The first drive control circuit according to claim 1, wherein the first drive control circuit
Supplied from the base of the fourth bipolar transistor.
And the first bipolar transistor is connected to the fourth bipolar transistor.
Turns on after bipolar transistor turns on
The base of the fifth bipolar transistor
A, with a predetermined delay, the first slow to Kyusuru subjected driving current
And the second drive control circuit includes an input signal
Supplied from the base of the second bipolar transistor
And the third bipolar transistor is connected to the second bipolar transistor.
After the bipolar transistor is turned on, the sixth
To be turned on by the bipolar transistor of
The base of the sixth bipolar transistor is provided with a predetermined
From the second delay circuit that supplies the drive current with a delay
The output circuit according to claim 1. 3. The method according to claim 1, wherein said first and second delay circuits are provided with an input signal.
From the inverter that generates the drive current as the logical inversion of
3. The output circuit according to claim 2, wherein 4. The fourth delay circuit according to claim 1 , wherein
The base connected to the base of the polar transistor and the front
Connected to the base of the fifth bipolar transistor
A collector, an emitter connected to the fourth voltage source,
A seventh bipolar transistor comprising:
The second delay circuit includes the second bipolar transistor
And the sixth bipolar transistor connected to the base
A collector connected to the base of the transistor;
An eighth bypass comprising an emitter connected to the second voltage source.
4. The output circuit according to claim 3, wherein the output circuit comprises a polar transistor. 5. The first drive control circuit according to claim 1 , wherein:
Connected to the gate of the MOS transistor
And detecting the voltage of the fifth bipolar transistor.
Voltage detecting means for supplying the detected gate voltage to the
And the second drive control circuit comprises:
Connected to the gate of the MOS transistor
And the base voltage of the sixth bipolar transistor is detected.
Voltage detecting means for supplying the detected gate voltage to the
And the fifth bipolar transistor comprises a plurality of stages.
A fifth bipolar transistor is connected to the second MOS transistor.
Set to turn on before the transistor turns on.
The sixth bipolar transistor having a threshold level
The sixth bipolar transistor is connected to the first MO.
Set to turn on before the S transistor turns on.
2. The output circuit according to claim 1, wherein the output circuit has a threshold level that has been set. 6. The first voltage detecting means according to claim 1 , wherein:
Between the gate of the MOS transistor and the second voltage source
The second voltage detecting means, comprising a voltage divider connected to
Is connected to the gate of the second MOS transistor and the fourth MOS transistor.
6. A voltage divider connected between the first and second voltage sources.
Output circuit as described. 7. The first, third, and fifth voltage sources include a first voltage source,
Are provided as the first, third, and fifth voltages.
A common voltage source to supply the second, fourth and sixth
A voltage source supplies a second predetermined voltage to the second, fourth and sixth power supplies.
7. A source according to claim 6, which is a common voltage source supplied as pressure.
Power circuit. 8. The first, second, third, and fourth bipolar transistors.
La transistors each form a Darlington pair
2. The output of claim 1, wherein the output is a pair of bipolar transistors.
circuit.