JPH04347926A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain a high power analog signal, which drives an analog device, from a high power digital driving signal responding to a digital input signal with a low power consumption and no distortion. CONSTITUTION:A control transistor TR TC1 is driven after a delay by an inverting circuit 12a in response to the base voltage of a TR Tr6. When the TR TC1 is turned on, a TR Tr3 is turned off by the TR TC1 even if a driving circuit 11a generates an output current to turn on the TR Tr3. In the same manner, a control TR TC2 turns off a TR Tr5 even if a driving circuit 11c generates a current to turn on the TR Tr5. A power MOS TR Tr1 is turned on, and both TRs Tr1 and Tr2 are turned off in a moment before the output current is obtained from an output terminal To, and a through current is prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving an analog device, and more particularly to a high power digital output circuit for generating a high power digital signal for driving an analog device such as an audio speaker via a suitable filter circuit.

0002

2. Description of the Related Art Digital power amplifiers are increasingly being used in, for example, audio amplifiers because they provide high quality reproduced audio signals from digital systems. By using a digital power amplifier, analog signal processing can be omitted from the entire audio system except for the final stage that drives the audio speakers. This results in
It can ideally reproduce and process audio signals without the distortion and noise typical of analog audio systems. Such a digital power amplifier is particularly suitable for reproducing audio signals from digital signal sources such as digital audio disc players or digital tape recorders, which produce output audio signals in the form of digital information.

FIG. 8 shows an example of a digital audio system.

Referring to FIG. 8, a digital signal source 1 provides a digital output signal to a demodulator 3 via a fiber optic cable 2. In response, demodulator 3 regenerates a pulse code modulated (PCM) signal. converter 4
When supplied with the PCM signal, it simultaneously generates a PWM signal and its logical inversion value and supplies them to the digital drive circuit 5. Digital drive circuit 5 drives drive output circuits 6a and 6b each consisting of a pair of high power MOS transistors connected in series between voltage source VCC and ground plane VEE. Output circuits 6a and 6b are driven complementary, and circuit 6
When a generates an output current from voltage VCC, output circuit 6b
becomes the ground level VEE, and when the circuit 6b generates an output current from the voltage VCC, the output circuit 6a becomes the ground level. Output circuits 6a and 6b drive speakers 8 through low-pass filters 7a and 7b that smooth pulse width modulated signals supplied from output circuits 6a and 6b, respectively. As a result, the amplitude from speaker 8 is level VCC/2
A high power amplitude modulated signal that varies above and below is obtained. FIG. 9 shows the configuration of a conventional drive circuit 5 including MOS output circuits 6a and 6b.

Referring to FIG. 9, drive circuits 11a and 1
1b is the PWM signal D and its logical inversion value, respectively.

0006
]

[Math 1]

The input terminals Ti1 and Ti2 are connected to input terminals Ti1 and Ti2, respectively. The drive circuit 11a has an output terminal connected to the base of a bipolar transistor Tr3, and the drive circuit 11b has a connection to an output terminal connected to the base of another bipolar transistor Tr4. Transistor Tr
3 and Tr4 are connected in series between voltage source VCC and ground level VEE, and transistor Tr3 has a collector connected to voltage source VCC and an emitter connected to the collector of transistor Tr4. In addition, the transistor Tr
4 has an emitter connected to the ground plane VEE. Similarly, drive circuits 11c and 11d connected to input terminals Ti3 and Ti4, respectively, receive an inverted PWM signal.

[0008]

[Math 2]

and a non-inverted PWM signal D are respectively supplied. The drive circuit 11c has an output terminal connected to the base of a bipolar transistor Tr5, and the drive circuit 11d has an output terminal connected to the base of another bipolar transistor Tr6. Transistors Tr5 and Tr6 are connected in series between voltage source VCC and ground plane VEE, and transistor Tr5 has a collector connected to voltage source VCC and an emitter connected to the collector of transistor Tr6. Transistor Tr6 has an emitter connected to ground plane VEE.

The output circuits 6a and 6b have power MOS transistors Tr1 and Tr2 connected in series between voltage sources VCC and VEE, and the MOS transistor Tr1 has a drain connected to the voltage source VCC and a drain of the MOS transistor Tr2. and a source connected to M
OS transistor Tr2 has a source connected to ground plane VEE. Further, the transistor Tr1 is connected to a node n1 where the emitter of the bipolar transistor Tr3 and the collector of the bipolar transistor Tr4 are connected, and the transistor Tr2 is connected to a node n2 where the emitter of the transistor Tr5 and the collector of the transistor Tr6 are connected. Ru. The outputs of the output circuits 6a and 6b are connected to the source of the transistor Tr1 and the transistor Tr2.
It is obtained from the output terminal T0 connected to the node n3 connected to the drain of.

In the conventional drive circuit, the transistor Tr3
and Tr4 receive complementary input signals D and

0012

[Math 3]

It turns on and off in a complementary manner in response to . That is,
When transistor Tr3 is on, transistor Tr4 is off, and vice versa. Similarly, transistor Tr
5 and Tr6 are complementary input signals D and

[0014]

[Math 4]

It turns on and off in a complementary manner in response to . That is,
When the transistor Tr5 is on, the transistor Tr6 is off, and vice versa. In this way, the transistor T
When r3 is turned on in response to a high level signal at input terminal Ti1, transistor Tr4 is turned off in response to a low level signal at input terminal Ti2. As a result, a high level signal appears at the node n1, and the MOS transistor Tr1 is turned on in response. In response to the high level signal at the input terminal Ti1, a low level signal appears at the input terminal Ti3, a high level signal appears at the input terminal Ti4,
While the transistor Tr6 is on, the transistor Tr5 is off. As a result, the low level signal is transferred to node n2.
appears, and the transistor Tr2 is turned off in response. In this way, a large output current is obtained at the output terminal T0. On the other hand, when the logic states of the signals at the input terminals Ti1 to Ti4 are reversed, the transistor Tr3 is turned off, the transistor Tr4 is turned on, and the transistor Tr3 is turned off, and the transistor Tr4 is turned on.
5 is turned on, and transistor Tr6 is turned off. As a result, the transistor Tr1 is turned off and the transistor Tr2 is turned on. Thereby, the output terminal T0 is grounded and no output current is obtained from it. Output terminal T0
A desired output current can be obtained by smoothing the PWM output current with a filter circuit.

[0016]

However, the conventional drive circuit 5 has the following problems. That is, the transistor Tr1
When the gate voltages of transistors Tr1 and Tr2 are inverted, both transistors Tr1 and Tr2 may be turned on depending on their characteristics. A shoot-through current then flows from the voltage source VCC to the ground plane, distorting the reproduced audio signal and increasing the power consumption of the amplifier. Distortion of the reproduced audio signal naturally leads to a decrease in the quality of the reproduced sound, and increased power consumption becomes a serious problem in battery-powered systems such as portable audio systems.

Accordingly, the general object of the present invention is to provide a new and useful digital drive circuit that solves the above problems.

The present invention also provides a digital drive that outputs a high-power digital drive signal in response to a digital input signal, drives an analog device with high output, reduces power consumption, and provides an analog signal without distortion. The other purpose is to provide a circuit.

[0019]

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an output circuit that is supplied with an input digital signal and generates an output digital signal having increased output power. a first input terminal for receiving an input logic signal that alternates between second logic levels; a second input terminal for receiving a logic inverse value of the input logic signal; and a first input terminal for providing a first drive voltage. and a second voltage source that supplies a second drive voltage and is different from the first drive voltage. a third voltage source that supplies a third drive voltage; first and second transistors that are supplied from the second input terminal and turned on and off in response;
A fourth voltage source different from a third drive voltage that supplies a fourth drive voltage is connected in series between the input logic signal and its logic inverted value to the first and second input terminals the second transistor is turned off when the first transistor is on, and the second transistor is turned off when the first transistor is on; The first and second transistors are turned on and off in response to the input logic signal and its logic inversion such that when the first transistor is turned off, the fourth transistor is turned on and off when the third transistor is turned on. the third and fourth transistors are turned on and off in response to the input logic signal and its logic inversion such that the transistor is turned off and the third transistor is turned off when the fourth transistor is on; Both are connected in series between a fifth voltage source that supplies a fifth drive voltage and a sixth voltage source that is different from the fifth drive voltage that supplies a sixth drive voltage, and a first power transistor that is turned on when the transistor is turned on; a second power transistor that is turned on when the third transistor is turned on; and a second power transistor that is turned on when the third transistor is turned on; a first drive that delays and prohibits transition of the first transistor to the on state for a predetermined interval even after the second power transistor is turned on from off so that the first transistor does not turn on immediately; a control circuit, and a control circuit that immediately detects the on state of the first power transistor and, in response, prevents the third transistor from turning on, even after the first power transistor is turned on from off. and a second drive control circuit that delays and inhibits the transition of the transistor to the on state for a predetermined interval.

[0020]

[Operation] According to the present invention, the first and second power MOS
This prevents the transistors from turning on at the same time, eliminating the problems of reproduced signal distortion and excessive power consumption.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 shows the main part of the first embodiment, and FIG. 2 shows the main part of the second embodiment.

In this embodiment, transistors Tr4 and T
The base potential of r6 is the control transistor TC2.
, TC1.

FIG. 1 is a diagram corresponding to FIG. 10 showing a conventional configuration, which includes a first control transistor TC1 that supplies the base potential of the transistor Tr6. This first control transistor TC1 has a collector connected to the base of the transistor Tr3 and an emitter connected to the ground plane VEE. The base of the transistor TC1 is connected to the base of the bipolar transistor Tr6 via the first inverting circuit 12a, so that the transistor TC1 is delayed and driven by the inverting circuit 12a in response to the base voltage of the transistor Tr6. When the transistor TC1 is turned on, the transistor Tr3 is turned off by the transistor TC1 even when the drive circuit 11a generates an output current that turns on the transistor Tr3. Similarly, a transistor TC2 is provided which has a collector connected to the base of the transistor Tr5 and an emitter connected to the ground plane VEE, and further has a base connected to the base of the transistor Tr4 via the second inverting circuit 12b. It will be done. As a result, the transistor T
C2 is delayed and driven by the inverting circuit 12b in response to the base voltage of the transistor Tr4. At this time, when the transistor TC2 is turned on, the transistor TC2 turns off the transistor Tr5 even when the drive circuit 11c generates an output current that turns on the transistor Tr5.

For example, when the logic level of input information D changes from high level to low level, input terminals Ti1 and Ti
The input signal supplied to input terminal 4 changes from high level to low level, and the level of the input signal supplied to input terminals Ti2 and Ti3 changes from low level to high level. In response, drive circuits 11a and 11d generate high level signals, and drive circuits 11b and 11c generate low level signals. Furthermore, in response to the low level output of the drive circuit 11b, the transistor Tr4 is immediately turned off. Since the transistor Tr6 is immediately turned on, the power MOS transistor Tr2 is turned off.

On the other hand, the base voltage of the transistor TC1 is in a high state due to the delay caused by the inverting circuit 12a when the logic level of the input signals to the input terminals Ti1 to Ti4 changes. As a result, the transistor TC1 remains on for a while and then turns off. transistor T
While C1 is on, the base current escapes to ground through transistor TC1, so transistor Tr3 is turned off. In this way, the voltage at node n1 is low during this time and power MOS transistor TC1 remains off. Only when the transistor TC1 is turned off after the aforementioned period has elapsed, that is, after detecting that the transistor Tr6 has been turned on, the transistor Tr3 is turned on and the MOS transistor Tr1 is turned on.

Similarly, input signals are input to input terminals Ti1 to T
The base voltage of transistor TC2 remains low while being fed to i4. As a result, the transistor TC2 is turned off and then turned on after an interval corresponding to the delay by the inverting circuit 12b has elapsed. However, input terminal T
Since transistor Tr5 is turned off in response to the high level at i3, the operation of transistor TC2 is as in circuit 10.
does not substantially change. In this way, the voltage level of the node n2 is low while the input terminal Ti3 is high, and the power MOS transistor Tr2 is turned off. During the operation, there is a moment when the power MOS transistor Tr1 is turned on and both transistors Tr1 and Tr2 are turned off before the output current is obtained from the output terminal T0. Therefore, it is possible to prevent the through current from flowing from the voltage source VCC to the ground plane VEE.

The above operation applies also when the level at input terminals Ti1 and Ti4 changes from low level to high level, and when the level at input terminals Ti2 and Ti3 changes from high level to low level, so it is redundant. Explanation will be omitted.

FIG. 2 shows the main part of the second embodiment. In this example, the voltages at contacts n1 and n2 are detected by control transistors TC4 and TC3, respectively. Transistor TC4 has a collector connected to the base of transistor Tr5 and a grounded emitter. Specifically, there is provided a voltage divider DIV1 connected across contact n1 and ground, and transistor TC4 has its base connected to the contact of voltage divider DIV1. Note that the resistor Rx and the resistor Ry are connected in series with each other. Similarly, another control transistor TC has a collector connected to the base of transistor Tr3 and an emitter grounded.
3 are provided. Additionally, transistor TC3 has a base connected across node n2 and the ground plane to voltage divider DIV2. Specifically, the voltage divider DIV
2 is a resistor R connected in series between the node n2 and the ground plane.
x' and Ry', and the base of the transistor TC3 is connected to a voltage divider DI in which the resistors Rx' and Ry' are connected to each other.
Connected to the V2 contact.

Transistor TC3 has a threshold level that is substantially smaller than the threshold level of power MOS transistor Tr2, and transistor TC4 has a threshold level that is substantially smaller than the threshold level of power MOS transistor Tr1. Therefore, when the power MOS transistor Tr2 is turned on, the transistor TC3 is turned on at the timing when the transistor TC3 is turned on before the transistor Tr2 is turned on. Similarly, when power transistor Tr1 is turned on, transistor TC4 is turned on before transistor Tr1 is actually turned on. In response to turning on the transistor TC3, the transistor Tr3 turns off and the power M
Before the OS transistor Tr2 turns on, the power MOS
Transistor Tr1 is turned off. Also, in response to the transistor TC4 being turned on, the transistor Tr
5 is turned off, and the power MOS transistor Tr2 is turned off before the power MOS transistor Tr1 is turned on. This prevents the power MOS transistors Tr1 and Tr2 from being turned on simultaneously, and effectively prevents the through current from flowing from the voltage source VCC to the ground.

Next, a first embodiment of the present invention will be described with reference to FIG. Referring to FIG. 3, the drive circuit represents the circuit 10, and the first drive circuit drives the power MOS transistor Tr1.
2a and a second drive unit 2b that drives the power MOS transistor Tr2. In the first driving section 2a, the input signal D at the input terminal Ti1 is the voltage source VC
The voltage is supplied to the base of an NPN transistor Tr11, which has a collector connected to C via a constant current source 3a and an emitter connected to the ground plane VEE. Transistor Tr
11 drives the transistor Tr3 via the NPN transistor Tr12 forming a Darlington pair with the transistor Tr3. Here, the transistor Tr12
has a base connected to the collector of the transistor Tr11, a collector connected to the voltage source VCC, and an emitter connected to the base of the transistor Tr3. Further, a diode D connects the emitter and base of the transistor Tr12 with an anode terminal connected to the emitter of the transistor Tr12 and a cathode terminal connected to the base of the transistor Tr12. Similarly, the input signal

[0031]

[Math 5]

The input terminal T is connected via the resistor R2 to obtain
An NPN transistor Tr13 is provided which has a base connected to i2, a collector connected to voltage source VCC via constant current source 3b, and a grounded emitter. Transistor Tr13 is transistor Tr4
and an NPN transistor Tr forming a Darlington pair.
15 to drive the transistor Tr4. In this way, the transistor Tr15 has a collector connected to the collector of the transistor Tr4, and a collector connected to the collector of the transistor Tr4.
and the emitter connected to the base of transistor Tr1.
3 and a base connected to a collector. Furthermore,
Transistor Tr15 is connected to the emitter of transistor Tr12 via resistor R1. In addition to the drive transistor Tr13, the base connected to the input terminal Ti2 via the resistor R3, and the transistor Tr4
Another drive transistor Tr14 having a collector connected to the base of and an emitter connected to the ground plane VEE.
Also provided.

A similar configuration is also provided in the drive section 2b. Transistors Tr21 to Tr25 correspond to transistors Tr11 to Tr15, respectively.

[0034] In this way, the second driving section 2b receives the input signal

[0035]

[Math 6]

It has an NPN transistor Tr21 having a base connected to the input terminal Ti3 for receiving , a collector connected to the voltage source VCC via a constant current source 3b, and an emitter connected to the ground plane VEE. . The transistor Tr21 drives the transistor Tr5 via the NPN transistor Tr22 forming a Darlington pair with the transistor Tr5. Here, the transistor Tr22 has a base connected to the collector of the transistor Tr21, a collector connected to the voltage source VCC, and an emitter connected to the base of the transistor Tr5. Furthermore, the anode terminal connected to the emitter of the transistor Tr22 and the transistor Tr22
A diode D connects the emitter and base of the transistor Tr22 by its cathode terminal connected to the base of the diode D.
is provided.

Similarly, a base connected to the input terminal Ti4 via a resistor R7 for receiving the input signal D;
An NPN transistor Tr23 is provided having a collector connected to the voltage source VCC via a constant current source 3b and a grounded emitter. Transistor Tr23 is an NP that forms a Darlington pair with transistor Tr6.
Transistor Tr6 via N transistor Tr25
to drive. In this way, the transistor Tr25 has a collector connected to the collector of the transistor Tr6,
an emitter connected to the base of the transistor Tr6;
The base of the transistor Tr23 is connected to the collector of the transistor Tr23. Further, the collector of the transistor Tr25 is connected to the emitter of the transistor Tr22 via a resistor R6, and the emitter of the transistor Tr25 is grounded via a resistor R9. Drive transistor T
In addition to r23, input terminal Ti2 is connected via resistor R8.
Another transistor Tr24 is provided having a base connected to the base of the transistor Tr6, a collector connected to the base of the transistor Tr6, and an emitter connected to the ground plane VEE.

In order to achieve the object of the present invention and to prevent power MOS transistors Tr1 and Tr2 from being turned on at the same time, transistor Tr15 is connected via resistor R4.
Bipolar transistor Tr1 connected to the base of
8 are provided. The transistor Tr18 further has a collector connected to the voltage source VCC via a constant current source 3c, and a grounded emitter. Therefore, the transistor Tr18 is turned on in response to the base voltage of the transistor Tr15, and the level at the collector of the transistor Tr18 changes to low after a delay corresponding to the operation of the transistor Tr18. Transistor Tr18 drives another NPN transistor Tr17, which has a base connected to the collector of transistor Tr18, a collector connected to the base of transistor Tr22, and a grounded emitter. Therefore, the transistor Tr17 is turned off when the transistor Tr16 is on, and turned on when the transistor Tr16 is off. When on, transistor Tr17 absorbs the base currents of transistors Tr22 and Tr5 directly and also through diode D, and regardless of the voltage level at the collector of transistor Tr21, transistor Tr2 absorbs the base current of transistors Tr22 and Tr5.
2 and Tr5 are both turned off.

Similarly, the driving section 2b includes a transistor Tr.
The bipolar transistor Tr28 has a base connected to the base of the transistor Tr25 through a resistor R10. Transistor Tr28 further has a collector connected to voltage source VCC via constant current source 3c' and a grounded emitter. Therefore, the transistor Tr28 is turned on in response to the base current of the transistor Tr25, and the level at the collector of the transistor Tr28 is lowered by a delay corresponding to the transistor Tr28. Transistor Tr28 drives another NPN transistor Tr27, which has a base connected to the collector of transistor Tr28, a collector connected to the base of transistor Tr12, and a grounded emitter. Therefore, transistor Tr27 is transistor Tr2
6 turns off when it turns on, and the transistor Tr2 turns off.
Turns on when 6 turns off. When on, transistor Tr27 connects transistors Tr12 and Tr3.
absorbs the base current of directly or through diode D,
Both transistors Tr12 and Tr3 are turned off regardless of the voltage level at the collector of transistor Tr11.

FIGS. 4A to 4J are time charts showing the operation of each part of the circuit 10. Here, Fig. 4(A)
indicates input information D supplied to input terminals Ti1 and Ti4. FIG. 4(B) shows input information supplied to input terminals Ti2 and Ti3.

[0041]

[Math 7]

[0042] is shown. In addition, FIG. 4(C) shows the input terminal Ti
Transistor Tr25 generated in response to signal D at 4
and the on/off timing of Tr6. Figure 4(C)
As shown in FIG. 3, the on/off state of the transistors Tr25 and Tr6 substantially coincides with the rising and falling edges of the input information D.

On the other hand, FIG. 4(D) shows the transistor Tr25.
The on/off timing of the transistor Tr27 in response to the base voltage of the transistor Tr27 is shown. As shown in FIG. 4(D),
There is a delay in turning on and off the transistor Tr27,
Such delay is caused by the operation of transistor Tr28. Note that the transistor Tr28 is the transistor T
While detecting the base voltage of r25, the transistor T
Drive r27. When the input information D returns to the low level corresponding to the falling of the waveform in FIG. 4(A), the transistor Tr23 is turned off and the transistor Tr23 is turned off.
The voltage level at the collector becomes high. In response to this, the transistor Tr28 is turned on,
The transistor Tr27 is turned off after the delay shown in FIG. 4(D).

Transistor Tr27 is transistor T
When the base currents of r12 and Tr3 are released to the ground, the transistors Tr12 and Tr3, which are turned off in response to the high level of the input signal D, will turn off even if the input signal D is at the low level in the falling state in FIG. 4(A). Even if I return,
It remains off during the period shown in FIG. 4(E). As a result, the power MOS transistor Tr1 is replaced with the transistor Tr12 and Tr3 as shown in FIG. 4(F).
It will not turn on until it turns on in response to r27 turning off. At this time, the transistor Tr1 responds to the rising edge of the input signal D shown in FIG. 6(A), which coincides with the falling edge of the input signal D shown in FIG. Control and turn off immediately.

FIG. 4(G) shows transistors Tr4 and Tr.
15 states are shown. As shown in the figure, the on/off of these transistors occurs substantially in synchronization with the input signals D and D shown in FIGS. 4(A) and 4(B). In addition, Figure 4 (
H) shows the operation of the transistor Tr17 in response to the base voltage of the transistor Tr15. As shown in FIG. 4(H), the transistor Tr15 operates with a delay with respect to the input signals D and D in FIGS. 4(A) and 4(B). This is because the transistor Tr16, which actually drives the transistor Tr17, operates with a delay.

FIG. 4(I) shows the input signal at input terminal Ti3.

[0047]

[Math. 8]

Transistors Tr22 and T
The operation of r5 is shown. As shown in FIG. 4(I), transistors Tr22 and Tr5 are off while transistor Tr17 is on. When transistor Tr17 is turned off, transistors Tr22 and Tr5 are turned on, and the input signal of FIG. 4(B) is

[0049]

[Math. 9]

It turns off substantially in response to the rising edge of . In response to the operations of transistors Tr22 and Tr5, power MOS transistor Tr2 is turned on and off as shown in FIG. 4(J). Power MOS transistor Tr1
Figure 4 (F) showing the operation of the power MOS transistor T
When compared with FIG. 4(J) showing that of r2, it is noticed that there is an interval in which both transistors Tr1 and Tr2 are turned off corresponding to the delay caused by transistors Tr18 and Tr28. Therefore, as explained in FIG. 1, the power MOS transistors Tr1 and Tr2 are never turned on at the same time.

FIG. 6 shows a detailed circuit diagram of the second embodiment corresponding to FIG. 2.

In this circuit, the gate voltage of the MOS transistor Tr1 is detected by the NPN transistor Tr31 via a voltage divider including a series connection of resistors R31 and R32. Transistor Tr31 is transistor T
It has a collector connected to the base of r22 and a grounded emitter. Therefore, the MOS transistor Tr
When MOS transistor Tr1 is turned on, the gate voltage of MOS transistor Tr1 increases, transistor Tr31 is turned on, and transistors Tr22 and Tr5 are turned off. Similarly, an NPN transistor Tr32 is provided which detects the gate voltage of the MOS transistor Tr2 via a voltage divider including resistors R33 and R34 connected in series. The transistor Tr32 has a collector connected to the base of the transistor Tr12 and a grounded emitter. Transistor Tr32 turns off transistor Tr12 and transistor Tr3 in response to an increase in the gate voltage of transistor Tr2.

FIGS. 7A to 7D show time charts of the circuit operation of FIG. 6. FIG. 7A shows changes in the gate voltage of power MOS transistor Tr1 at node TOa. FIG. 7C shows changes in the gate voltage of power MOS transistor Tr2 at node TOb. Figure 7(A)
In the figure, the threshold level for on/off of the power MOS transistor Tr1 is expressed as VTHa. Similarly, the threshold level of power MOS transistor Tr2 is VTHb
It is expressed as

Here, the threshold level for the operation of the transistor Tr31 is the MO of FIG. 7(A) indicated by the line Vra.
It is set lower than that of the S transistor Tr1. Similarly, the threshold level for the operation of transistor Tr32 is set lower than that of MOS transistor Tr2 in FIG. 7C, indicated by line Vrb. As a result, the operation of the transistor Tr31 is shown in FIG.
), when the power MOS transistor Tr1 is turned on, the voltage level of the contact TOa changes from the low level (VEE) to the high level (VCC), and the transistor Tr31 becomes the transistor Tr1.
turns on before it turns on. Similarly, contact TO
When the voltage level of b increases from the low level (VEE) to the high level (VCC), the transistor Tr32 turns on as shown by the rise in FIG. 7(D), and the power MOS transistor Tr2 turns on the transistor Tr32. It turns on afterward.

The power MOS transistor Tr1 cannot be turned on while the transistor Tr32 is on. Therefore, the power MOS transistor Tr1 is the transistor T
Before r2 is turned on, it is turned off by transistor Tr32. Similarly, the power MOS transistor Tr2 cannot be turned on while the transistor Tr31 is on. Therefore, the transistor Tr2 is turned off by the transistor Tr31 before the transistor Tr1 is turned on. Therefore, even if there are variations in circuit constants and transistor threshold values, the power MOS transistors Tr1 and Tr
2 are never on at the same time. Furthermore, no through current flows through the transistors Tr1 and Tr2.

FIG. 7 shows a modification of the circuit of FIG. As shown in the figure, NPN transistors Tr33 and Tr34 are provided to turn off transistors Tr12 and Tr3 in response to the voltage at contact TOa. The transistor Tr33 has a base connected to the contact of a voltage divider in which resistors R31 and R32 are connected to each other to detect the voltage level at the contact TOa, and a constant current source 3.
It has a collector connected to voltage source VCC via d and an emitter connected to ground. On the other hand, transistor Tr3
4 has a base connected to the collector of the transistor Tr33, a collector connected to the base of the transistor Tr12, and a grounded emitter.

Transistor Tr34 turns on in response to the low voltage level at contact TOa, and input terminal Ti1
While the input to the supplementary input terminal Ti2 is at a high level and the input to the supplementary input terminal Ti2 is at a low level, the transistors Tr12 and Tr3 are turned off. When the signal levels at input terminals Ti1 and Ti2 are inverted, transistor Tr34 becomes transistor Tr34.
33, the transistor T
Prohibit r12 and Tr3 from turning on immediately. Transistors Tr12 and Tr3 can be turned on only when transistors Tr15 and Tr4 are turned off. The feature of the circuit shown in FIG. 7 that can prevent wasted current from flowing through the transistors Tr3 and Tr4 is intended to improve the power consumption of the circuit. Input terminals Ti1 and T
When the input signal level at i2 is inverted again, transistors Tr12 and Tr3 are immediately turned off and transistors Tr15 and Tr4 are turned on. Here, the transistor Tr34 is turned on with a delay. In this case, even if the transistor Tr34 is turned on, the transistor T
r12 and Tr3 remain off.

In order to prevent transistors Tr5 and Tr6 from being turned on at the same time, a transistor Tr35 and a transistor Tr36 are provided in the driving section 2b. The operation of this circuit is similar to that described above, so repeated explanation will be omitted. According to the circuit of FIG. 7, the power consumption of the output circuit can be saved, and the power MOS transistors Tr1 and Tr2 are not turned on at the same time.

If the output circuits shown in FIGS. 5 to 7 are used, the output circuit shown in FIG.
The power consumption of the digital audio system can be saved and the system can provide higher sound quality. Furthermore, the present output circuit is not limited to digital audio systems. For example, it can be used to reduce power consumption when driving electronic motors and electromagnetic actuators.

[0060]

According to the present invention, it is possible to reliably prevent power MOS transistors from being turned on at the same time, thereby reducing power consumption and distortion in the output signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts of a first embodiment of the present invention.

FIG. 2 is a block diagram showing main parts of a second embodiment of the present invention.

FIG. 3 is a detailed circuit diagram showing a drive circuit of a first embodiment according to the present invention.

FIG. 4 is a time chart showing the operation of the transistor in the circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a modification of the circuit in FIG. 3;

FIG. 6 is a detailed circuit diagram showing a drive circuit of a second embodiment according to the present invention.

FIG. 7 is a time chart showing the operation of the transistor in the circuit of FIG. 5;

FIG. 8 is a diagram showing a modification of the circuit of FIG. 6;

FIG. 9 is a block diagram showing the configuration of a digital audio system according to the present invention.

10 is a block diagram showing the configuration of a conventional digital drive circuit used in the audio system of FIG. 9. FIG.

[Explanation of symbols]

1 Digital signal source 2 Optical fiber cable 3 Modulator 4 Converter 5 Digital drive circuits 6a, 6b Output circuits 7a, 7b Low-pass filter 8 Speaker 10 Circuits 11a, 11b, 11c, 11d Drive circuit Ti1,
Ti2, Ti3, Ti4 Input terminal VCC Voltage source VEE Ground plane Tr1, Tr2, Tr3, Tr4, Tr5, Tr6
Transistors Tr11, Tr12, Tr13, T
r14, Tr15 Transistors Tr16, Tr17, Tr18, Tr19, T
r20 Transistors Tr21, Tr22, Tr23, Tr24, T
r25 transistors Tr26, Tr27, Tr28, Tr29, T
r30 Transistors Tr31, Tr32, Tr33, Tr34, T
r35 Transistor T0 Output terminals n1, n2, n3 Contacts TC1, TC2 Control transistors D, D Input information DIV1, DIV2 Voltage divider Rx, Ry, Rx', Ry' Resistance

Claims (9)

[Claims] Claim 1: A first logic level and a lower second logic level.
a first receiving an input logic signal having alternating logic levels;
a second input terminal for receiving a logic inverted value of the input logic signal, a first voltage source for providing a first drive voltage, and a second drive voltage different from the first drive voltage. A first voltage source that is connected in series with a second voltage source that supplies a voltage, is supplied with the input logic signal and its logical inversion value from the first and second input terminals, and is turned on and off in response to the input logic signal and its logic inverted value. and a second transistor connected in series between a third voltage source supplying a third drive voltage and a fourth voltage source supplying a fourth drive voltage different from the third drive voltage. and third and fourth transistors that are supplied with the input logic signal and the logic inversion thereof from the first and second input terminals, respectively, and are turned on and off in response to the input logic signal, and the first
The first and second transistors are connected to the input logic such that when the transistor is on, the second transistor is off, and when the second transistor is on, the first transistor is off. It turns on and off in response to a signal and its logical inverse value, and when the third transistor is on, the fourth transistor is off, and when the fourth transistor is on, the third transistor is off. The third and fourth transistors are turned on and off in response to the input logic signal and its logic inversion, and further supply a fifth voltage source that supplies a fifth drive voltage and a sixth drive voltage. a first power transistor that is connected in series with a sixth voltage source different from a fifth drive voltage that is turned on when the first transistor is turned on; and a first power transistor that is turned on when the first transistor is turned on; detects the on-off state of the second power transistor, and after detecting that the second power transistor is turned off, transitions the first transistor to the on state; a first drive control circuit that detects an on/off state of the first power transistor and, after detecting that the first power transistor is turned off, a first drive control circuit that transitions a third transistor to an on state; an output circuit comprising: two drive control circuits, which is supplied with an input digital signal and generates an output digital signal having increased output power; 2. The first transistor has a collector connected to the first voltage source, an emitter, and a collector connected to the first voltage source.
a first bipolar transistor having a base to which a signal based on an input digital signal is supplied from an input terminal of the transistor, the second transistor having a collector connected to the emitter of the first bipolar transistor; a second bipolar transistor including an emitter connected to a second voltage source and a base supplied with a signal based on the logical inversion value of the input digital signal from the second input terminal; The transistor includes a third bipolar transistor having a collector connected to the third voltage source, an emitter, and a base to which a signal based on the input digital signal is supplied from the second input terminal, and A transistor No. 4 has a collector connected to the emitter of the third bipolar transistor, an emitter connected to the fourth voltage source, and is supplied with a signal based on the input digital signal from the first input terminal. consisting of a base and a fourth bipolar transistor,
The first power transistor is a first MOS transistor including a drain connected to the fifth voltage source, a gate connected to the emitter of the first bipolar transistor, and a source. The second power transistor has a drain connected to the source of the first MOS transistor, a gate connected to the emitter of the third bipolar transistor, and a source connected to the sixth voltage source. The first drive control circuit is composed of a fifth bipolar transistor having a collector connected to the base of the first bipolar transistor and an emitter connected to the second voltage source, 2. The output circuit according to claim 1, wherein the second drive control circuit comprises a sixth bipolar transistor having a collector connected to the base of the third bipolar transistor and an emitter connected to the fourth voltage source. . 3. The first drive control circuit is supplied with an input signal from the base of the fourth bipolar transistor, and the first bipolar transistor is supplied with the input signal from the base of the fourth bipolar transistor.
a first delay circuit that supplies a drive current to the base of the fifth bipolar transistor with a predetermined delay so that the fifth bipolar transistor is turned on after the second bipolar transistor is turned on; The circuit is configured such that an input signal is supplied from the base of the second bipolar transistor, and the third bipolar transistor is supplied from the base of the second bipolar transistor.
after the sixth bipolar transistor is turned on.
so that it is turned on by a bipolar transistor of
2. The output circuit according to claim 1, further comprising a second delay circuit that supplies a drive current to the base of said sixth bipolar transistor with a predetermined delay. 4. The output circuit according to claim 3, wherein said first and second delay circuits each include an inverter that generates a drive current as a logical inversion value of an input signal. 5. The first delay circuit has a base connected to a base of the fourth bipolar transistor;
The second delay circuit includes a seventh bipolar transistor having a collector connected to the base of the fifth bipolar transistor and an emitter connected to the fourth voltage source, and the second delay circuit is connected to the second bipolar transistor. 5. An eighth bipolar transistor comprising a base connected to the base of the transistor, a collector connected to the base of the sixth bipolar transistor, and an emitter connected to the second voltage source. output circuit. 6. The first drive control circuit is configured to control the first drive control circuit.
a first voltage detection means connected to the gate of the MOS transistor to detect the gate voltage thereof and supply the detected gate voltage to the base of the fifth bipolar transistor, the second drive control circuit; is the second
a second voltage detection means connected to the gate of the MOS transistor to detect the gate voltage thereof and supply the detected gate voltage to the base of the sixth bipolar transistor; The fifth bipolar transistor has a threshold level set to turn on before the second MOS transistor turns on, and the sixth bipolar transistor has a threshold level set to turn on before the second MOS transistor turns on. M of
3. The output circuit of claim 2, having a threshold level set to turn on before the OS transistor turns on. 7. The first voltage detection means is configured to detect the first voltage.
The second voltage detection means includes a voltage divider connected between the gate of the second MOS transistor and the fourth voltage source, and the second voltage detection means is configured to connect the gate of the second MOS transistor and the fourth voltage source. 7. The output circuit according to claim 6, comprising a voltage divider connected between. 8. The first, third, and fifth voltage sources are a common voltage source that supplies a first predetermined voltage as the first, third, and fifth voltages; , 4th and 6th
8. The output circuit according to claim 7, wherein the voltage source is a common voltage source that supplies the second predetermined voltage as the second, fourth, and sixth voltages. 9. The output circuit according to claim 2, wherein each of the first, second, third, and fourth bipolar transistors is a pair of bipolar transistors forming a Darlington pair.